CN112016263B - Method for realizing data delay equalization - Google Patents
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- CN112016263B CN112016263B CN202011135538.5A CN202011135538A CN112016263B CN 112016263 B CN112016263 B CN 112016263B CN 202011135538 A CN202011135538 A CN 202011135538A CN 112016263 B CN112016263 B CN 112016263B
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Abstract
The invention includes a method for implementing data delay equalization. The method comprises the following steps: providing a controller to perform placing a start point and an end point unit on an equalization path; placing a combinational logic unit on the equalization path; replacing the type and driving strength of the sequential unit in the equalization path; permuting the type and strength of combinational logic cells in the equalization path; enclosing a shielding area; repairing design rule violations for each balanced path; and fine-tuning the unit delay and the line delay. By adopting the method for realizing data delay equalization provided by the invention, the unit devices are placed in advance, the types and the driving strength of the unit devices are replaced, so that the delay of the unit devices on the equalization path tends to be consistent, the line delay tends to be consistent, and the deviation of the equalization path is greatly reduced, thereby greatly shortening the iteration period of the back-end realization.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a method for realizing data delay equalization.
Background
With the increasing complexity of the digital chip production process, the requirements for the digital chip back end design are also increasing. In a typical integrated circuit chip back-end design, the two most important tasks are timing closure and physical closure. Timing convergence refers to that all logic units in a circuit can meet all preset timing requirements, the requirements generally include setup time (setup time) and hold time (hold time) set in a digital logic unit design library, and special timing requirements set by a chip front-end developer according to actual use requirements of a chip, and if the requirements cannot be met, the produced chip cannot realize correct logic functions under specified temperature and voltage. The physical convergence refers to that all the layouts and wirings must meet Design Rule Checks (DRC), which need to Check whether all the logical connections are physically connected, and meet the requirements of connection constraints, and once the requirements are not met, the chip may be shorted or disconnected in the production, so that the chip cannot normally operate.
The parallel data receiving and transmitting interface path is an important means for improving the data transmission efficiency, but as the signals are transmitted and received by the same time sequence and the signals are received by the same time sequence, the clock frequency of the digital chip is higher and the number of devices in the parallel data receiving and transmitting interface path is increased, the layout and the wiring are slightly different, so that larger delay is possibly generated on different paths, and the problem of time sequence is possibly caused.
Therefore, not only the parallel transceiving data interface paths need to meet the requirements of normal setup time and hold time, but also the requirements of clock and data path equalization become more and more important. There are three main types of path equalization checks: (1) clock balance (clock balance), i.e., the clock path of a particular set or sets of registers needs to meet a certain range of clock skew; (2) data balance (data balance), i.e. for a specific group or groups of parallel data, the time deviation of the data from the starting point of the path to the end point of the path needs to satisfy a certain range; (3) and (4) balancing the clock and the data, wherein the clock and the data simultaneously need to meet a certain deviation to reach the end point of the path. In the above three types of path equalization checks, different PVT (Process and Temperature) modes generally need to be considered, and Process, Voltage and Temperature are three basic factors affecting circuit performance. Since the delay models of different types of unit devices are not consistent under different PVT conditions, a certain challenge is brought to the back-end for implementing path equalization.
The front-end and back-end tools can realize clock equalization under different PVT conditions by designating unit devices on the clock path as fixed VT (threshold voltage) types. For data equalization and clock data equalization, a common practice in the industry at present is to manually adjust a backend tool after the backend tool is implemented to meet a path deviation (skew) requirement, but because no manual intervention is performed in the early stage, the backend tool has a large difference between data paths in an automatic layout and wiring process, so that the later stage equalization path is difficult to approach a range under different PVT conditions, and often a long time of multiple iterations is needed to meet the requirement. The current parallel transceiving data interface path is difficult to approach a range under different PVT conditions, and the following reasons mainly exist: (1) a plurality of combinational logic units are usually arranged on a data equalization path, the types of the units are various, and different unit devices are under different PVT conditions, so that the difficulty of path equalization is increased; (2) if the equalization path spans a long distance, the combinational logic is too decentralized, and the backend is typically solved by inserting buffers or inverters (buffers/inverters) in order to repair the maximum transition (max transition) and maximum capacitance (max capacitance) violations in the DRV (design rule violation). After the buffer is inserted, on one hand, the gate numbers of the inserted units on the equalization paths are inconsistent, namely the logic levels on different paths have different values, so that the delay on different paths is greatly different; on the other hand, it will cause a large difference in line delay between different cell gates, which will cause the path delay to vary greatly under different PVT conditions. Both of these factors will increase the variation of the path delay deviation under different PVT conditions.
Therefore, there is a need for a method capable of implementing data delay equalization, which can ensure that delays in various paths tend to be consistent under different PVT conditions, and ratios of device unit delay and routing delay tend to be consistent under various PVT conditions, and which can reduce iteration times and shorten implementation period of the chip design back end.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for realizing data delay equalization, which can replace the combinational logic units on the paths to be equalized to a specific VT type in advance, place the combinational logic units in advance, insert a phase inverter or a buffer with specific series, and lead the ratio of the device delay to the line delay on all the equalization paths to approach a specific value, thereby achieving the requirement of quickly iterating and realizing the data equalization. By adopting the method, the iteration times are greatly reduced, the realization period of the rear end of the chip design is shortened, and the situation that the expected effect is difficult to achieve through multiple iterations when the traditional rear end realizes the balance of data and clock paths is avoided.
In order to achieve the above object, the present invention provides a method for implementing data delay equalization, comprising the following steps: providing a controller to perform placing a start point and an end point unit on an equalization path; placing a combinational logic unit on the equalization path; replacing the type and driving strength of the sequential unit in the equalization path; permuting the type and strength of combinational logic cells in the equalization path; enclosing a shielding area; repairing design rule violations for each balanced path; and fine-tuning the unit delay and the line delay. According to the method for realizing data delay equalization, the time sequence unit and the combinational logic unit are placed in advance, the unit device type and the driving strength are replaced, so that the deviation on an equalization path is greatly reduced, and the iteration period realized by a back end is greatly shortened.
Preferably, the location of the combinational logic cell on each path is the same, and the placement of the combinational logic cell is one of the following: near the start point, near the end point, or in an intermediate node area of the path. By placing the combinational logic cells at the same location, design rule violations caused by improper placement of the combinational logic cells by the backend tools can be reduced.
Preferably, by permuting the type and drive strength of the sequential cells in the equalization path and permuting the type and strength of the combinational logic cells in the equalization path, DRV problems in the equalization path due to cell type and drive strength are relieved and each equalization path is made to meet design expectations.
Preferably, when the design rule violation is repaired for each equalization path, the repair is performed by inserting a buffer or an inverter on the path.
Preferably, when the buffer or the inverter is inserted into the equalization path, the buffer or the inverter is equidistantly placed on the equalization path, and the number of the buffer or the inverter is equal, and the type and the driving strength are consistent. The drivers or the inverters are equidistantly arranged on the balanced paths, so that the difference of the winding lengths among different paths is reduced, and the line delay difference among different paths is further reduced; and the number of stages of the buffer or the inverter is equal, and when the type is consistent with the driving strength, the difference between the cell type and the logic level value on different paths can be reduced, and path balance can be achieved more easily.
Preferably, the method for realizing data delay equalization further comprises selecting a routing metal layer on the equalization path so that the line delay has drift consistency under different PVT conditions.
Preferably, when selecting a routing metal layer on the equalization path, the same routing metal layer or an adjacent routing metal layer is selected. By selecting the specific winding metal layer, the phenomenon that the number of layers of different paths is greatly different due to the fact that a rear-end tool automatically selects the winding metal layer is avoided, and further the line delay difference of different paths is increased.
Preferably, the method for realizing data delay equalization is suitable for parallel transceiving data interface paths. Because the parallel transceiving data interface path has higher requirements on clock balance and path balance, the parallel transceiving data interface path can be more easily balanced by adopting the method.
Drawings
Fig. 1 is a flow chart of a method for implementing data delay equalization according to the present invention.
Fig. 2 is a schematic diagram of an electronic device implementing the method for data delay equalization according to the present invention.
Detailed Description
The technical means adopted by the invention to achieve the preset purpose are further described below by combining the accompanying drawings and the preferred embodiment of the invention.
The invention provides a method for realizing data delay equalization, which is characterized in that a time sequence unit and a combinational logic unit on an equalization path are placed in advance, a phase inverter or a buffer with a specific grade is inserted, and the ratio of device delay and line delay on all the equalization paths approaches to a specific value, so that the requirement of realizing data equalization by fast iteration is met, the iteration times are greatly reduced, and the realization period of the rear end of a chip design is shortened.
The implementation of the path equalization goal can be represented by a polynomial model:
wherein the content of the first and second substances,x ji in order to delay the time of the unit,a ji the cell delay is scaled by a factor that varies under various PVT conditions, different PVT conditions,a ji the factors are different.y ji Is a line delay, a connection delay between units,b ji the line delay is factored for variations in various PVT conditions,b ji the factors are different.d j Is a sheetThe total delay of the paths is equalized by a strip,n j is the number of logic unit stages of the equalization path. J is more than or equal to 0 and less than m +1, and m is the number of data clock equalization paths. The aim of the equalization is to realized j And approaching to a specific value under all conditions, and meeting the requirement of balanced path deviation (skew).
To meet the requirement of balancing the path deviation, the total delay of all paths under different PVT conditionsd j The delay and winding delay ratio of the device unit tends to be consistent under various PVT conditions, namely (1) the delay of the device unit is required to be kept to be consistent; (2) the winding length needs to be uniform. I.e. the ratio of the delay of the device unit to the delay of the routing in each path
The requirements tend to be consistent under different PVT conditions, wherein n represents the logic unit progression in each path. By controlling the ratio of the delay of the device unit in each path to the delay of the routing, the variation of each path under different PVT conditions tends to be consistent, and the path balance of different data paths under different PVT conditions is easier to realize.
Compared with a Clock Tree Synthesis (CTS) process with mature Clock equalization, data equalization needs human intervention in advance so as to achieve consistency of ratio of delay of device units to delay of routing delay.
According to an aspect of the present invention, there is provided a method for implementing clock data equalization, as shown in fig. 1, including:
step 1: the starting point and the end point units on the equalization path are placed, the positions of the starting point and the end point are determined by placing the starting point and the end point units on the equalization path in advance, so that the starting point and the end point of the equalization path tend to be equidistant physically, and the series of logic units in the polynomial can be ensuredn j Are equal. The units placed at the start and end of the equalization path include registers, interface device units, etc.
Step 2: and placing the combinational logic units on the balanced path, and placing the combinational logic units in the vicinity of the starting point or the end point of the path or in the middle node area in advance. According to different situations, the combinational logic cells in different equalization paths are placed at the same position, for example, in the case of an SRAM (Static Random Access Memory) in the path, because the combinational logic cells are in the path and occupy a larger area, the combinational logic cells in all equalization paths can be placed near the starting point or near the ending point. The combinational logic cells are placed at the same position according to the actual balanced path situation, and the combinational logic cells can be placed near the starting point or the end point of the path or in the middle node area. By placing the combinational logic units at the same position in advance, the problem of Design Rule Violation (DRV) caused by improper placement of the combinational logic units of the back-end tool can be effectively reduced.
And step 3: the type (cell type) and driving strength (driving strength) of the timing cells and the combinational logic cells in the permutation and equalization path. Firstly, the problem of design rule violation caused by inappropriate cell types and driving strengths of a time sequence unit and a combinational logic unit in a balanced path is solved by replacing the cell types and the driving strengths of the time sequence unit and the combinational logic unit; secondly, each equalization path is made to meet the design expectation by replacing the cell type and the driving strength of the sequential cell and the combinational logic cell. In chip design, there is a certain requirement for the delay of the equalization path, such as the maximum delay max [ max ] of each pathd j ]500ps, that is, each equalization path can also satisfy the above requirement under the worst case (worst case). The worst-case PVT conditions of the equalization path may vary from process to process. After the sequential unit and the combinational logic unit are replaced, each equalization path can reach the design expectation. In addition, by replacing the sequential cell type and driving strength and replacing the type and driving strength of the combinational logic cell, it can be ensured that the cell types on all equalization paths are consistent, i.e. all cell delays in the polynomialx ji Tend to be consistent.
And 4, step 4: enclosing a shielded area (block). In order for the back-end tool to place the buffers or inverters in the desired locations, the desired effect is achieved by creating appropriate masking regions that prohibit the tool from placing the cell in the masking regions. In addition, the shielding area is built in a circle, and the condition that the wiring path of each equalizing path is inconsistent and the line delay is increased when the rear-end tool is used for wiring can be prevented.
And 5: for each equalization path to repair a DRV, design rule violations are typically repaired by inserting buffers or inverters on the path. If the equalization paths are far across domains, the inserted buffers or inverters need to be placed on the equalization paths equidistantly, the number of the inserted buffers or inverters on all the equalization paths is equal, and the types and the driving strengths of the inserted units are consistent. By inserting buffers or inverters equidistantly, the cells in the polynomial can be delayedx ji And the equalization tends to be consistent, reducing the difference between equalization paths.
Step 6: the appropriate routing metal layer is selected for the lines in the equalization path. The existing integrated circuits are all provided with a plurality of metal layers, and the increase of the number of the metal layers can increase the wiring density in a unit area of a chip, thereby reducing the total area of the chip and being beneficial to reducing the problem of wiring congestion. However, for balanced paths with particularly high design requirements, the delays of the different paths may differ by no more than 60ps, i.e. max, under different PVT conditionsd j ]-min[d j ]Less than or equal to 60 ps. At this time, if human intervention is not performed in advance, the backend tool may select different numbers of metal layers for different equalization paths, and the routing across multiple metal layers may introduce a large line delay drift due to a certain difference in routing delay of different metal layers. Therefore, for the equalization path with a particularly high requirement, the same routing metal layer or a closer routing metal layer needs to be selected to reduce the drift of the routing delay, thereby ensuring the consistency of the drift of the line delay under different PVT conditions.
And 7: and carrying out fine adjustment on the unit delay and the line delay. Since the number of equalization paths is usually large, it is inevitable that the path distances are slightly different, and even if the buffers are placed equidistantly, some paths are wound far and some paths are wound close. Therefore, the ratio of cell device delay to line delay needs to be fine tuned to be consistent under each PVT condition.
Through the steps, the method for realizing the data delay equalization provided by the invention has the following advantages: (1) the physical distances of the balanced paths tend to be consistent by placing the unit devices in advance, and the problem of design rule violation caused by improper placement of the combinational logic is reduced by selecting the placement positions; (2) by replacing the types and the driving strengths of the unit elements, the unit types on the equalization path tend to be consistent, and DRV problems caused by the types and the driving strengths of the unit elements can be solved in advance; (3) inserting buffers or inverters on the equalization paths at equal distances so that the number of the buffers or inverters inserted on all the equalization paths is equal; (4) in the method, the unit device delays on the equalization paths tend to be consistent, the line delays tend to be consistent, and the ratio of the device delay to the line delay on each path tends to be consistent, so that the deviation of the equalization paths is greatly reduced, the iteration period of the back-end implementation is greatly shortened, and the situation that the expected result is difficult to achieve through multiple iterations when the traditional back-end implements the equalization of data and clock paths is avoided.
Referring to fig. 2, fig. 2 is a schematic diagram of an electronic device implementing a data delay equalization method according to the present invention. The electronic device 1 comprises a controller 10 and a memory element 12. The controller 10 may be configured to perform a method flow as shown in fig. 1. The memory element 12 is coupled to the controller 10 and can be used to store various information required by the operation of the controller 10.
In this embodiment, the controller 10 may be any type of processor (processor) having computing capability. The storage element 12 may be any type of memory, hard disk drive, or optical disk, without limitation, as known to those skilled in the art.
By the method for realizing data delay equalization, the controller 10 can enable the ratio of device delay and line delay on all equalization paths to approach a specific value on the premise of not influencing correctness, thereby achieving the requirement of realizing data equalization by fast iteration, greatly reducing the iteration times and shortening the realization period of the rear end of the chip design.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A method for implementing data delay equalization, comprising:
providing a controller to perform:
placing a start point and an end point unit on the equalization path, wherein the start point and the end point of the equalization path tend to be equidistant physically;
placing the combinational logic units on the equalization paths, and placing the combinational logic units on different equalization paths at the same position;
replacing the type and driving strength of the sequential unit in the equalization path; permuting the type and strength of combinational logic cells in the equalization path;
enclosing a shielding area;
repairing design rule violations for each balanced path; and
and finely adjusting the proportion of the unit delay to the line delay to ensure that the ratio of the unit delay to the line delay in each path tends to be consistent under different PVT conditions.
2. The method for implementing data delay equalization of claim 1 wherein the location of the combinational logic cell on each path is the same, and the placement of the combinational logic cell is one of the following locations: near the start point, near the end point, or in an intermediate node area of the path.
3. The method of implementing data delay equalization as claimed in claim 1 wherein DRV problems in the equalization path due to cell type and drive strength are relieved and each equalization path is made to meet design expectations by permuting the type and drive strength of the timing cells in the equalization path and permuting the type and strength of the combinational logic cells in the equalization path.
4. The method for implementing data delay equalization of claim 1, wherein, when the design rule violation is repaired for each equalization path, the repair is performed by inserting a buffer or an inverter in the path.
5. The method for implementing data delay equalization as claimed in claim 4, wherein when the buffers or inverters are inserted in the equalization path, the buffers or inverters are equidistantly placed on the equalization path, and the number of the buffers or inverters is equal, and the type and the driving strength are the same.
6. The method of claim 1 further comprising selecting routing metal layers in the equalization path such that the routing delays have drift consistency under different PVT conditions.
7. The method of claim 6 wherein the routing metal layer in the equalization path is selected to be either the same routing metal layer or an adjacent routing metal layer.
8. The method for implementing data delay equalization of claim 1, wherein the method for implementing data delay equalization is adapted to parallel transmit-receive data interface paths.
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| CN202011135538.5A CN112016263B (en) | 2020-10-22 | 2020-10-22 | Method for realizing data delay equalization |
| TW110121148A TWI769852B (en) | 2020-10-22 | 2021-06-10 | Method of balancing data delay |
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| US8966425B1 (en) * | 2012-06-03 | 2015-02-24 | Pulsic Limited | Clock tree generation and routing |
| US9613175B2 (en) * | 2014-01-28 | 2017-04-04 | Globalfoundries Inc. | Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit |
| CN107862154A (en) * | 2017-11-29 | 2018-03-30 | 成都锐成芯微科技股份有限公司 | A kind of timing adjusting method |
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