CN112015336B

CN112015336B - RRAM-based capacity-adjustable memory and capacity adjustment and data transmission method thereof

Info

Publication number: CN112015336B
Application number: CN202010747634.9A
Authority: CN
Inventors: 梁晓祯; 雷晓艺; 高佳锐; 白永林; 王乐; 王博; 李然; 吕林蔚
Original assignee: XiAn Institute of Optics and Precision Mechanics of CAS
Current assignee: XiAn Institute of Optics and Precision Mechanics of CAS
Priority date: 2020-07-28
Filing date: 2020-07-28
Publication date: 2021-08-17
Anticipated expiration: 2040-07-28
Also published as: CN112015336A

Abstract

The invention relates to a semiconductor memory, in particular to a capacity-adjustable memory based on an RRAM (resistive random access memory) and a capacity adjusting and data transmission method thereof. The problems that in a traditional storage scheme, because an interface power supply occupies a chip space, the storage capacity of a storage module is small, the storage capacities of two storage modules are fixed and not adjustable, effective utilization is difficult to achieve, data transmission between the two storage modules is slow and the like are solved. The device comprises a volatile storage module, a nonvolatile storage module and a control module; the volatile memory module and the nonvolatile memory module adopt the same RRAM as a memory unit and share the same control module; the volatile memory unit corresponds to different addresses of the nonvolatile memory unit; the control module is provided with one group or two groups of IO interfaces and one group of power interfaces and is communicated with the CPU through the IO interfaces; is connected with an external power supply through a power interface; the capacity adjustment and data transmission of the volatile memory unit and the nonvolatile memory unit are realized through the control module.

Description

RRAM-based capacity-adjustable memory and capacity adjustment and data transmission method thereof

Technical Field

The invention relates to a semiconductor memory, in particular to a capacity-adjustable memory based on an RRAM (resistive random access memory) and a capacity adjusting and data transmission method thereof.

Background

At present, almost all electronic devices with reading and memory functions adopt a storage scheme of combining volatile memory and nonvolatile memory. Volatile memories such as Dynamic Random Access Memories (DRAMs) are generally used for memories with high requirements for memory rate (DDR (double data rate) synchronous dynamic random access memories, LPDDR (low voltage double data rate) synchronous dynamic random access memories, etc.); for hard disks or U disks with low requirements on storage rate, nonvolatile memories are generally adopted, and NAND flash is widely applied.

In conventional memory schemes, the memory cells and the operating mechanisms of the volatile and nonvolatile memory modules are different, thus requiring two different interfaces and power supplies. For example, DDR and hard disk in a computer are two completely independent units, two different data interfaces and power supplies must be used, and both the interfaces and power lines need to occupy chip space, and the larger the number is, the smaller the memory cell manufacturing space in the chip is, thereby reducing the total capacity of the memory module.

Meanwhile, in the traditional storage scheme, the physical storage spaces of the two storage modules are fixed, and the two storage modules cannot be functionally converted. According to the storage scheme, once the type of the stored chip is selected, the storage capacity cannot be further expanded in any mode, and the two storage units cannot convert the storage function. The same type of product is used, and if some users want larger volatile storage capacity, the requirement on the nonvolatile storage capacity is not high; on the contrary, some users want the nonvolatile memory to have a large capacity and have low requirements on the volatile memory capacity, and if the conventional memory scheme is adopted, the product cannot fully meet the requirements. When the traditional storage scheme is used, if a large-area bad block occurs in a certain storage unit, the system cannot operate normally, and the storage capacity cannot be increased. Meanwhile, in the conventional storage scheme, two different storage units are adopted, two different storage modules are required, and even two storage modules are completely and independently packaged, so that the physical space utilization rate in the system is limited, and the space utilization maximization is not realized. Meanwhile, data transmission between two memory modules is slow, and reading and writing processes are required.

Although the current common memory used in terminal devices such as mobile phones adopts the scheme of embedded multi-chip package memory EMCP (or universal multi-chip package memory upmcp) which packages embedded multimedia memory card EMMC (or universal flash memory UFS) and LPDDR together, the purpose is to reduce the chip size. In this type of memory, the EMMC (or UFS) and the LPDDR are also two independently operating modules, the memory cells of the two modules are completely different, and the memory spaces of the memory cells are not changed and are independent fixed memory spaces. Although the method improves a certain physical space utilization rate and reduces one package, the original two memories are physically integrated together, and a power supply, an IO input/output interface and a controller are not completely shared and are not completely integrated. Moreover, the physical integration causes the size, the IO number and the power supply number of the integrated chip to be much lower than those of a single volatile memory and a single nonvolatile memory, so that the difficulty of PCB design is increased, the difficulty of outgoing lines of the chip on the PCB is increased, and the integrity and the reliability of signals are reduced. In addition, such memories also face the problem of the storage capacity being unalterable as mentioned above. This problem is particularly acute in consumer products where the user has a wide variety of memory requirements, and where volatile and non-volatile memory capacity is required. Based on this storage scheme, the types of storage capacity that can be provided by each product are very limited, and once a certain model is selected by a user, the storage capacity cannot be changed any more.

Although memory manufacturers now solve the capacity problem through 3D, multi-layer, etc., MCP memory capacity is greatly limited due to the memory architecture and operating mechanism. These methods only solve the problem of the storage unit capacity of one memory, and the two memories are still two different modules or even two independent packages, and the utilization of the physical space is still not maximized.

Disclosure of Invention

The invention aims to provide a capacity-adjustable memory based on RRAM (resistive random access memory), which aims to solve the problems that the storage capacity of a storage module is small, the storage capacities of two storage modules are fixed and not adjustable, the effective utilization is difficult to realize, the data transmission between the two storage modules is slow and the like due to the fact that an interface power supply occupies a chip space in the traditional storage scheme.

The conception of the invention is as follows:

the RRAM is a Resistive Random Access Memory, namely a Resistive Random Access Memory, which belongs to a nonvolatile Memory, but compared with the traditional nonvolatile Memory, the RRAM has the characteristics of simple structure, small volume, low cost, low power consumption, high speed and the like, and has the characteristics of a plurality of volatile memories.

Based on these features of RRAM, the inventors considered the use of RRAM for non-volatile memory modules, as well as for volatile memory modules. The two storage modules are integrated in one memory, the volatile storage module and the nonvolatile storage module adopt the same RRAM as a storage unit, so that the driving power supply and the IO interface share one group, high integration of storage space is realized, and the number of the interfaces can be reduced. After the interfaces and the power supply are reduced, more space inside the chip can be used for manufacturing the storage unit, and therefore the total capacity of the storage is increased.

In order to effectively utilize the storage space, in the storage scheme of the invention, the capacities of the volatile storage module and the nonvolatile storage module can be controlled by software, and the unused storage unit area can be randomly adjusted into volatile storage or nonvolatile storage according to different application scenes. As for the demand of large-capacity nonvolatile storage, unused memory cell areas can be preferentially divided to nonvolatile memory modules; for a scene with high memory requirement similar to a large-scale game, the unused memory cell area can be divided into the volatile memory modules.

In order to improve the data transmission rate between the two memories, in the storage scheme of the invention, because the two memory modules share the memory cell, the corresponding part of the address of the memory cell where the data in the volatile memory module is located can be directly marked as the address corresponding to the nonvolatile memory cell, and the corresponding part of the memory cell where the nonvolatile memory data with the same size is located is supplemented as the volatile memory cell, so that the data transmission can be instantly completed. The larger the data volume, the more obvious the advantages of the novel transmission mode are. For extracting data from the nonvolatile memory module to the nonvolatile memory module, only the reverse operation is needed, and the ultra-fast transmission can be realized.

The technical scheme of the invention is to provide a capacity-adjustable memory based on RRAM, which is characterized in that: the device comprises a volatile storage module, a nonvolatile storage module and a control module;

the volatile memory module and the nonvolatile memory module are integrated in one chip; the volatile memory module and the nonvolatile memory module adopt the same RRAM as a memory unit and share the same control module;

a storage unit area corresponding to the volatile storage module is made to be a volatile storage unit, and a storage unit area corresponding to the nonvolatile storage module is made to be a nonvolatile storage unit; the volatile memory unit corresponds to different addresses of the nonvolatile memory unit;

the control module is provided with one group or two groups of IO interfaces and one group of power interfaces and is communicated with the CPU through the IO interfaces; is connected with an external power supply through a power interface;

if the memory comprises a group of IO interfaces, the CPU simultaneously addresses the volatile memory unit and the nonvolatile memory unit through the IO interfaces;

if the two groups of IO interfaces are included, the CPU addresses the volatile memory unit and the nonvolatile memory unit respectively through the two groups of IO interfaces; the read and write rates can be further increased.

The control module is used for controlling the volatile memory unit and the nonvolatile memory unit to realize buffering and data storage management.

Further, the data storage management includes:

(1) initializing;

according to the CPU instruction, a volatile memory unit and a nonvolatile memory unit are designated in the RRAM memory unit, and different addresses are marked for the volatile memory unit and the nonvolatile memory unit; feeding back the initial address information of the RRAM storage unit to the CPU;

(2) reallocating storage capacity;

according to the CPU instruction, marking the address of the unused memory cell area as the address corresponding to the volatile memory cell or the nonvolatile memory cell, and completing the reallocation of the capacity of the volatile memory cell and the nonvolatile memory cell; the unused memory cell area is an unused area in a volatile memory cell or a nonvolatile memory cell;

(3) feeding back address information;

feeding back the address information of the RRAM storage unit with the reallocated storage capacity to the CPU through the IO interface;

(4) data transmission;

and according to the data transmission instruction sent by the CPU, finishing data transmission by modifying the address of the storage unit area corresponding to the data to be transmitted.

Further, the reallocation of the storage capacity specifically includes:

when the storage capacity of the volatile storage unit needs to be increased, the CPU judges whether an unused storage unit area exists in the nonvolatile storage unit, if the unused storage unit area exists in the nonvolatile storage unit, a corresponding instruction is sent to the control module through the IO interface, the control module modifies the initial address information of the RRAM storage unit according to the CPU instruction, and the address of the unused storage unit area in the nonvolatile storage unit is marked as an address corresponding to the volatile storage unit;

when the capacity of the nonvolatile memory unit needs to be increased, the CPU judges whether an unused memory unit area exists in the volatile memory unit, if the unused memory unit area exists, a corresponding instruction is sent to the control module through the IO interface, the control module modifies the initial address information of the RRAM memory unit according to the CPU instruction, and the address of the unused memory unit area in the volatile memory unit is marked as the address corresponding to the nonvolatile memory unit.

Further, the data transmission specifically includes:

after receiving the data transmission instruction and the data address sent by the CPU, the control module marks the address corresponding to the storage unit of the data to be transmitted in the volatile storage unit as the address corresponding to the nonvolatile storage unit again, and marks the regional address with the same size in the original nonvolatile storage unit as the address corresponding to the volatile storage unit to finish data transmission.

Further, the data storage management may further include:

(1) initializing;

according to the CPU instruction, a volatile memory unit, a nonvolatile memory unit and an unused memory unit are designated in the RRAM memory unit, and different addresses are marked for the volatile memory unit, the nonvolatile memory unit and the unused memory unit; feeding back the initial address information of the RRAM storage unit to the CPU;

(2) reallocating storage capacity;

according to the CPU instruction, marking the address of the unused memory cell area as the address corresponding to the volatile memory cell or the nonvolatile memory cell, and completing the reallocation of the capacity of the volatile memory cell and the nonvolatile memory cell;

(3) feeding back address information;

(4) data transmission;

Further, the reallocation of the storage capacity specifically includes:

when the capacity of the volatile memory unit needs to be increased, receiving a corresponding instruction sent by a CPU through an IO interface, modifying initial address information of the RRAM memory unit according to the instruction, and marking an unused memory unit address as an address corresponding to the volatile memory unit;

when the capacity of the nonvolatile memory unit needs to be increased, a corresponding instruction sent by the CPU is received through the IO interface, the initial address information of the RRAM memory unit is modified according to the instruction, and the address of the unused memory unit is marked as the address corresponding to the nonvolatile memory unit.

The invention also provides a capacity adjustable memory capacity adjusting method based on the RRAM, which is characterized by comprising the following steps:

step 1, initializing;

step 1.1, a control module receives an initial instruction sent by a CPU through an IO interface, specifies a volatile memory unit and a nonvolatile memory unit in an RRAM memory unit according to the initial instruction, and marks different addresses for the volatile memory unit and the nonvolatile memory unit;

step 1.2, the control module feeds back initial address information of the RRAM storage unit to a CPU through an IO interface to serve as an initial value;

step 2, redistributing the storage capacity;

the control module marks the address of the unused memory cell area as the address corresponding to the volatile memory cell or the nonvolatile memory cell according to the CPU instruction, and completes the reallocation of the capacity of the volatile memory cell and the nonvolatile memory cell; the unused memory cell area is an unused area of a volatile memory cell or a nonvolatile memory cell;

step 3, feeding back address information;

the control module feeds back the address information of the RRAM storage unit with the reallocated storage capacity to the CPU through the IO interface;

and 4, repeating the steps 2 and 3 when the storage capacity needs to be reallocated again.

Further, step 2 specifically comprises:

when the capacity of the nonvolatile memory unit needs to be increased, the CPU judges whether an unused memory unit area exists in the volatile memory unit, if the unused memory unit area exists, a corresponding instruction is sent to the control module through the IO interface, the control module modifies the initial address information of the RRAM memory unit according to the CPU instruction, and the address of the unused memory unit area in the volatile memory unit is marked as the address corresponding to the nonvolatile memory unit;

the invention also provides another capacity-adjustable memory capacity adjusting method based on the RRAM, which is characterized by comprising the following steps:

step 1, initializing;

step 1.1, a control module receives an initial instruction sent by a CPU through an IO interface, specifies a volatile memory unit, a nonvolatile memory unit and an unused memory unit in an RRAM memory unit according to the initial instruction, and marks different addresses for the volatile memory unit, the nonvolatile memory unit and the unused memory unit;

step 2, capacity reallocation

The control module marks the address of the unused memory cell area as the address corresponding to the volatile memory cell or the nonvolatile memory cell according to the CPU instruction, and completes the reallocation of the capacity of the volatile memory cell and the nonvolatile memory cell;

step 3, feeding back address information;

Further, step 2 specifically comprises: when the capacity of the volatile memory unit needs to be increased, the control module receives a corresponding instruction sent by the CPU through an IO interface, modifies the initial address information of the RRAM memory unit according to the instruction, and marks the address of the unused memory unit as the address corresponding to the volatile memory unit;

when the capacity of the nonvolatile memory unit needs to be increased, the control module receives a corresponding instruction sent by the CPU through an IO interface, modifies the initial address information of the RRAM memory unit according to the instruction, and marks the address of the unused memory unit as the address corresponding to the nonvolatile memory unit;

the invention also provides a capacity-adjustable memory data transmission method based on the RRAM, which is characterized in that:

after receiving the data transmission instruction and the data address sent by the CPU, the control module marks the address corresponding to the memory cell needing data transfer in the volatile memory cell as the address corresponding to the nonvolatile memory cell again, and marks the regional address with the same size in the original nonvolatile memory cell as the address corresponding to the volatile memory cell to complete data transmission.

Through the steps, the data can be rapidly transmitted between the volatile memory module and the nonvolatile memory module. It is of course also possible to read data first and then write data for data transmission in a conventional manner.

The invention has the beneficial effects that:

1. the structure is simple, and the memory capacity is large;

the memory, the volatile memory module and the nonvolatile memory module share the memory cell and the IO interface and the power supply, so that the structure is simplified, the physical space required by the power supply and the interface of the memory is greatly reduced, more space is used for the memory cell, and the total capacity of the memory is improved.

2. The effective utilization rate of the storage unit is high;

the capacity of the storage units of the volatile storage module and the nonvolatile storage module in the memory is adjustable, the memory can adapt to different storage requirements, and the effective utilization rate of the storage space is greatly improved.

3. The data transmission speed is high;

the two memory modules in the memory share the memory unit, the address of the memory unit corresponding to the data in the volatile memory module can be directly marked as the address corresponding to the nonvolatile memory unit, and the data transmission between the two memory modules can be completed at a high speed.

4. The volume of the memory is small;

compared with the traditional EMCP, the memory provided by the invention has the advantages that a group of power supplies is reduced, a group of IO interfaces is also reduced, the isolation between two memory units is reduced, the utilization of the internal space of the EMCP chip is maximized, and the size of the memory is greatly reduced.

Drawings

FIG. 1 is a basic structure diagram of a RRAM resistive random access memory;

FIG. 2 illustrates RRAM resistive switching modes of operation;

FIG. 3 is a block diagram of a conventional EMCP memory architecture;

FIG. 4 is an internal structure diagram of the RRAM-based scalable memory of the present invention;

FIG. 5 is a schematic diagram of the capacity adjustment method of the volatile and nonvolatile memory units of the RRAM-based capacity-adjustable memory according to the present invention;

FIG. 6 is a schematic diagram of data transmission between volatile and nonvolatile memory cells of the RRAM-based scalable memory of the present invention.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.

The RRAM resistive random access memory achieves the purpose of storing data by utilizing the mutual conversion between different resistance states of a thin film material under the action of electric excitation. The basic structure is shown in fig. 1, and is a simple Metal-Insulator-Metal (MIM) or Metal-Insulator-Semiconductor (MIS) sandwich structure, in which Top and Bottom electrodes (Top/Bottom Electrode: TE/BT) are provided, and an insulating Resistance Switching Layer (RSL) is provided in the middle.

There are two modes of operation to achieve RRAM resistance transition: one is Unipolar switching (Unipolar), i.e., the resistance state of the device is switched by voltage excitation of the same polarity, as shown in fig. 2 (a). The SET process device is switched from a high resistance state to a low resistance state, and is switched from the low resistance state to the high resistance state in the RESET process device, and the applied voltage excitation polarity is the same. The other is Bipolar transition (SET) in which the voltage polarity is opposite to that of the RESET process, as shown in FIG. 2 (b).

In a conventional memory or storage scheme, a volatile memory and a nonvolatile memory are completely independent, and a storage unit, a power supply and an IO interface are also completely independent. Taking an EMCP memory commonly used by the terminal device as an example, as shown in fig. 3. The storage unit of the volatile memory is DRAM, the storage unit of the nonvolatile memory is FLASH, the storage density of the FLASH is much lower than that of the RRAM, the two storage units of the FLASH and the DRAM need to be isolated, two groups of different power supplies and IO interfaces are needed, and the power supply line and the IO interface also occupy larger physical space. Resulting in an EMCP memory structure that is complex and has a small storage capacity.

As shown in fig. 4, the novel memory of the present invention includes a volatile memory module, a non-volatile memory module and a control module; the memory units in the volatile memory module and the nonvolatile memory module adopt the same RRAM as a basic memory unit, the two memory modules are integrated in one chip, share the memory unit and share one group of interfaces and power supplies. Compared with the traditional EMCP memory, the memory provided by the invention has the advantages that a group of power supplies and IO interfaces are reduced, the isolation between two memory units is reduced, the utilization of the internal space of the EMCP chip is maximized, and the size of the memory can be greatly reduced. The use of such integrated memory allows for greater storage capacity within the same physical space than conventional storage schemes.

In the memory, the corresponding addresses of the memory units of the volatile memory module and the nonvolatile memory module are different, and the functions can be distinguished through the addresses. For convenience of description, the memory cells corresponding to the volatile memory module are defined as volatile memory cells, and the memory cells corresponding to the nonvolatile memory module are defined as nonvolatile memory cells. If the reading and writing rates are further improved, two groups of IO can be adopted to respectively address the volatile memory unit and the nonvolatile memory unit. No matter which scheme is adopted, the power supply can be completely shared, and only one group is needed.

Both volatile and nonvolatile memory units may implement buffering and data storage management through the control module. Data storage management may include initialization, reallocation of storage capacity, feedback of address information, and data transfer portions.

Initialization:

firstly, a CPU designates a part of area of an RRAM storage unit as a nonvolatile storage unit through a control module for storing bottom layer driving software required by system operation. Meanwhile, another partial area of the RRAM storage unit is designated as a volatile storage unit for meeting the basic requirement of system operation. The functions of these two areas cannot be changed to ensure that the system can operate properly each time. The control module marks different addresses for the volatile memory unit and the nonvolatile memory unit; and feeding back the initial address information of the RRAM storage unit to the CPU through the IO interface to be used as a default value of the system.

Reallocation of storage capacity:

after the system is loaded successfully, the CPU instruction is received through the IO interface, the control module finishes the free allocation of the capacities of the volatile memory module and the nonvolatile memory module, the conversion and allocation of the memory function can be finished only by marking the address corresponding to the unused memory unit correspondingly, and thus the unused memory unit can be randomly allocated to the volatile memory unit or the nonvolatile memory unit. At this time, the unused memory cell is an unused area of the volatile memory cell or the nonvolatile memory cell.

The initialization and storage capacity reallocation mode is as shown in fig. 5, after the system is started, the CPU sends an initial instruction to the control module through the IO interface according to a common usage scenario, the control module specifies regions corresponding to the volatile memory unit and the nonvolatile memory unit in the RRAM memory unit, allocates different addresses for the volatile memory unit and the nonvolatile memory unit, and the control module feeds back initial address information of the RRAM memory unit to the CPU through the IO interface as a default value of the system.

If the capacity of the volatile memory unit and the nonvolatile memory unit is to be adjusted, the capacity adjusting mechanism is triggered, and the CPU sends an instruction to reallocate the capacity of the volatile memory unit and the capacity of the nonvolatile memory unit through the control module.

When the storage capacity of the volatile storage unit needs to be increased, the CPU judges whether an unused storage unit area exists in the nonvolatile storage unit, if the unused storage unit area exists, a corresponding instruction is sent to the control module through the IO interface, the control module modifies the initial address information of the RRAM storage unit according to the CPU instruction, and the address of the unused storage unit area in the nonvolatile storage unit is marked as an address corresponding to the volatile storage unit; without any hardware changes.

For example, the total storage capacity is also 128GB, 8GB can be allocated to the volatile memory module, and the remaining 120GB can be allocated to the nonvolatile memory module; 12GB may also be allocated to the volatile memory module, with the remaining 116GB being allocated to the non-volatile memory module. During the use process, the capacities of the two parts can be randomly distributed or the user selects to distribute the capacities according to different users and different application scenes. Conventional storage schemes cannot achieve this capacity and function transition.

Or in the initialization process, the CPU designates a part of the area in the RRAM memory unit as a nonvolatile memory unit through the control module, so as to store the bottom-layer driver software required by the system operation. And meanwhile, a part of areas are designated as volatile memory units for meeting the basic requirements of system operation. The remaining portion area is designated as an unused memory cell area. Different addresses are distributed to the volatile memory unit, the nonvolatile memory unit and the unused memory unit, and the control module feeds back initial address information of the RRAM memory unit to the CPU through the IO interface to serve as a default value of the system.

Upon reallocation of storage capacity:

when the storage capacity of the volatile storage unit needs to be increased, the CPU sends a corresponding instruction to the control module through the IO interface, the control module receives the instruction sent by the CPU, modifies the initial address information of the RRAM storage unit according to the instruction, and marks the address of the unused storage unit as the address corresponding to the volatile storage unit;

when the capacity of the nonvolatile memory unit needs to be increased, the CPU sends a corresponding instruction to the control module through the IO interface, the control module receives the instruction sent by the CPU, the initial address information of the RRAM memory unit is modified according to the instruction, and the address of the unused memory unit is marked as the address corresponding to the nonvolatile memory unit.

Feeding back address information;

as shown in fig. 5, after the storage capacity is reallocated, the control module feeds back the address information of the RRAM storage unit of the reallocated storage capacity to the CPU through the IO interface.

In addition, in the running process of the system, the control module can also perform various bad block management, key data retention and other processing, thereby realizing a complete MCP function.

The memory can complete the data transmission from the volatile memory to the nonvolatile memory and from the nonvolatile memory to the volatile memory at an ultra-fast speed by re-marking the address of the memory cell. No matter how large the data amount is, only the mark information of the address needs to be changed as long as enough storage space is available, and the data transmission can be completed instantly. The data transmission mode has the same short time for transmission no matter how large the data transmission quantity is. For some applications with a large data volume transmission scene, the novel storage mode can achieve a very good effect.

The data transitions between volatile and non-volatile memory cells are shown in fig. 6. After a control module (a storage controller in the figure) in the memory receives a data transmission command and a data address sent by a CPU (a system controller in the figure), an address corresponding to a storage unit area needing data transfer in a volatile storage unit is marked as an address corresponding to a nonvolatile storage unit again, and an area address with the same size in the original nonvolatile storage is marked as a volatile storage function in a supplementing mode, so that data transmission can be completed instantly.

Claims

1. An RRAM-based scalable memory, comprising: the device comprises a volatile storage module, a nonvolatile storage module and a control module;

the volatile memory module and the nonvolatile memory module are integrated in one chip; the volatile memory module and the nonvolatile memory module adopt the same RRAM as a memory unit;

defining a storage unit area corresponding to a volatile storage module as a volatile storage unit, and defining a storage unit area corresponding to a nonvolatile storage module as a nonvolatile storage unit; the volatile memory unit corresponds to different addresses of the nonvolatile memory unit;

if the two groups of IO interfaces are included, the CPU addresses the volatile memory unit and the nonvolatile memory unit respectively through the two groups of IO interfaces;

2. The RRAM-based scalable memory of claim 1, wherein the data storage management comprises:

(1) initializing;

according to the CPU instruction, a volatile memory unit and a nonvolatile memory unit are designated in the RRAM memory unit, and different addresses are marked for the volatile memory unit and the nonvolatile memory unit; feeding back the address information of the RRAM storage unit to the CPU through an IO interface;

(2) reallocating storage capacity;

(3) feeding back address information;

(4) data transmission;

3. The RRAM-based scalable memory of claim 2, wherein the reallocated storage capacity is specifically:

4. The RRAM-based capacity tunable memory according to claim 3, wherein the data transmission is specifically:

5. The RRAM-based scalable memory of claim 1, wherein the data storage management comprises:

(1) initializing;

according to the CPU instruction, a volatile memory unit, a nonvolatile memory unit and an unused memory unit are designated in the RRAM memory unit, and different addresses are marked for the volatile memory unit, the nonvolatile memory unit and the unused memory unit; feeding back the address information of the RRAM storage unit to the CPU through an IO interface;

(2) reallocating storage capacity;

(3) feeding back address information;

(4) data transmission;

6. The RRAM-based scalable memory of claim 5, wherein the reallocated storage capacity is specifically:

7. The RRAM-based capacity tunable memory according to claim 6, wherein the data transmission is specifically:

8. The RRAM-based capacity tunable memory capacity adjustment method of claim 1, comprising the steps of:

step 1, initializing;

step 1.2, the control module feeds back the address information of the RRAM storage unit to a CPU through an IO interface as an initial value;

step 2, redistributing the storage capacity;

step 3, feeding back address information;

9. The RRAM-based capacity-tunable memory capacity adjustment method according to claim 8, wherein step 2 specifically is:

10. The RRAM-based capacity tunable memory capacity adjustment method of claim 1, comprising the steps of:

step 1, initializing;

step 2, redistributing the storage capacity;

step 3, feeding back address information;

11. The RRAM-based capacity-tunable memory capacity adjustment method according to claim 10, wherein step 2 specifically includes:

when the capacity of the volatile memory unit needs to be increased, the control module receives a corresponding instruction sent by the CPU through an IO interface, modifies the initial address information of the RRAM memory unit according to the instruction, and marks the address of the unused memory unit as the address corresponding to the volatile memory unit;

when the capacity of the nonvolatile memory unit needs to be increased, the control module receives a corresponding instruction sent by the CPU through the IO interface, modifies the initial address information of the RRAM memory unit according to the instruction, and marks the address of the unused memory unit as the address corresponding to the nonvolatile memory unit.

12. A data transmission method for a scalable RRAM-based memory according to claim 1, wherein: