CN112003621A - Digital-to-analog conversion control method, digital-to-analog converter, integrated circuit and equipment - Google Patents
Digital-to-analog conversion control method, digital-to-analog converter, integrated circuit and equipment Download PDFInfo
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- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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Abstract
The invention relates to the technical field of digital-to-analog conversion, in particular to a digital-to-analog conversion control method, a digital-to-analog converter, an integrated circuit and equipment, wherein the digital-to-analog conversion control method is used for N-bit digital-to-analog conversion and comprises the following steps: sampling, wherein 1 st capacitors of the two capacitor arrays are both connected with a reference level, and the rest capacitors are grounded; according to the 1 st comparison result, grounding the first capacitor of the capacitor array with high output voltage; according to the result of the previous comparison, at least one capacitor of the capacitor array with low output voltage is connected with a reference level; repeating the steps until the N-2 comparison is completed; determining the reference level of two bit capacitors at the tail end of the capacitor array according to the comparison results of the Nth-2 th time and the Nth-3 rd time; and determining the reference level of the last two-bit capacitor of the capacitor array according to the comparison results of the Nth time-1 and the Nth time-3 to complete N-bit digital-to-analog conversion. The method provided by the embodiment of the invention has the advantages of reduced capacitance quantity and reduced energy consumption.
Description
Technical Field
The present invention relates to the field of digital-to-analog conversion technologies, and in particular, to a digital-to-analog conversion control method, a digital-to-analog converter, an integrated circuit, and an apparatus.
Background
With the development of science and technology, electronic terminals such as personal computers, notebook computers, smart phones, tablet computers, portable wearable devices and the like greatly facilitate the production and the life of people. The analog-to-digital converter is one of the core components of the electronic terminal, and the analog-to-digital converter can convert an analog signal into a digital signal. Among Analog-to-Digital converters with various structures, SAR ADCs (Successive Approximation Analog-to-Digital converters) are widely used due to advantages such as simple structure and few modules.
The SAR ADC comprises a capacitor array DAC (Digital to Analog Converter), a comparator and a successive approximation shift register, wherein when the SAR ADC works, the capacitor array DAC samples and holds an Analog input signal, converts a Digital signal before each comparison into an Analog voltage, outputs the Analog voltage to the comparator for comparison, and further obtains an output number of the Analog-to-Digital Converter.
According to the power consumption analysis of the SAR ADC, the capacitor array DAC is one of important sources of the energy consumption of the SAR ADC. When the SARADC works, the successive approximation of the DAC output voltage is realized through the switching of the capacitor array DAC capacitor reference level. The switching scheme influences the energy consumption of the capacitor array DAC, and the switching scheme adopted by the SAR ADC with the traditional structure has the problem of overhigh power consumption.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a digital-to-analog conversion control method, a digital-to-analog converter, an integrated circuit, and an apparatus.
The embodiment of the invention is realized by a digital-to-analog conversion control method, which is used for N-bit digital-to-analog conversion and comprises the following steps:
sampling, wherein 1 st capacitors of the two capacitor arrays are both connected with a reference level, the rest capacitors are grounded, and the comparator performs 1 st comparison and outputs a comparison result;
according to the 1 st comparison result, the 1 st capacitor of the capacitor array with high output voltage is grounded, and the comparator performs the 2 nd comparison and outputs the comparison result;
according to the previous comparison result, at least one capacitor of the capacitor array with low output voltage is connected with a reference level, and the comparator compares and outputs a comparison result; repeating the steps until the N-2 comparison is completed;
determining the reference level of two-bit capacitors at the tail of the capacitor array according to the comparison results of the Nth time-2 and the Nth time-3, and comparing the reference level for the Nth-1 time by using a comparator and outputting a comparison result;
determining the reference level of the last two-bit capacitor of the capacitor array according to the comparison results of the Nth time and the Nth-3 th time, and performing Nth time comparison and outputting the comparison result by the comparator to finish N-bit digital-to-analog conversion;
wherein the capacitance order is counted from the side far away from the input end of the comparator.
In one embodiment, the present invention further provides a digital-to-analog converter, where the digital-to-analog converter includes a capacitor array DAC, and the capacitor array DAC is configured to implement digital-to-analog conversion by executing the digital-to-analog conversion control method according to the present invention.
In one embodiment, an embodiment of the present invention further provides an integrated circuit, where the integrated circuit includes the digital-to-analog converter according to the embodiment of the present invention.
In one embodiment, the embodiment of the present invention further provides a data processing apparatus, where the data processing apparatus includes a digital-to-analog converter or an integrated circuit according to the embodiment of the present invention.
The digital-to-analog conversion control method provided by the embodiment of the invention adjusts the reference level of the corresponding capacitor according to the comparison sequence and the obtained comparison result, reduces the energy consumption of the capacitor array DAC, reduces the number of capacitors in the method and further optimizes the structure.
Drawings
FIG. 1 is a diagram illustrating an exemplary embodiment of a digital-to-analog conversion control method;
fig. 2 is a schematic diagram of an implementation of digital-to-analog conversion control provided in an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms unless otherwise specified. These terms are only used to distinguish one element from another. For example, a first xx script may be referred to as a second xx script, and similarly, a second xx script may be referred to as a first xx script, without departing from the scope of the present application.
As shown in fig. 1, in one embodiment, a digital-to-analog conversion control method for N-bit digital-to-analog conversion is provided, which includes steps S102 to S110:
and S102, sampling, wherein the 1 st capacitors of the two capacitor arrays are both connected with a reference level, the rest capacitors are grounded, and the comparator compares the 1 st capacitors and outputs a comparison result.
In the embodiment of the invention, the capacitor array DAC samples and holds the input signal, converts the digital signal before each comparison into the analog voltage and outputs the analog voltage to the comparator for comparison, thereby obtaining the output digit of the analog-to-digital converter. In the embodiment of the invention, the reference voltage of the first capacitor of two capacitor arrays is connected with the reference level provided by the system, while the reference voltages of the other capacitors are grounded, and the input signal is directly collected to the top plates of all the capacitors of the capacitor arrays through the sampling switch. Due to the adoption of the top plate sampling technology, the capacitor array does not generate switching energy.
In the embodiment of the present invention, it should be understood that the 1 st capacitor refers to the 1 st capacitor of the capacitor array from the position far away from the input end of the comparator, and descriptions about the order of the capacitors, such as the 1 st, the ith, the last, the second last, the last bit, the last two bits, and the like, in any embodiment of the present invention are determined in this manner, and are not repeated in the following of the present invention.
In the embodiment of the present invention, it should be noted that, the capacitor grounded or connected to the reference level refers to the reference end of the capacitor; in the embodiment of the invention, the reference end of the capacitor at least comprises three modes of grounding, connecting with a reference level provided by a system, connecting with a reference voltage of a specific value and the like; the embodiment of the invention does not relate to the improvement of the connection mode of the capacitance sampling input end.
And step S104, according to the 1 st comparison result, the 1 st capacitor of the capacitor array with high output voltage is grounded, and the comparator performs the 2 nd comparison and outputs the comparison result.
In the embodiment of the invention, before the 2 nd comparison, the reference level of the 1 st capacitor is grounded during the sampling and holding of the capacitor array, specifically, the 1 st capacitor of which capacitor array is grounded is determined according to the result of the 1 st comparison. Therefore, the capacitance reference voltage is dynamically adjusted.
Step S106, according to the previous comparison result, at least one capacitor of the capacitor array with low output voltage is connected with a reference level, and the comparator compares and outputs the comparison result; this step was repeated until the N-2 th comparison was completed.
In the embodiment of the present invention, at least one capacitor of the capacitor array with a low output voltage is grounded, and it should be understood that the grounding herein refers to the transition from non-grounding to grounding. And specific one of the capacitors is grounded, which is determined by the previous comparison result, so that the dynamic adjustment of the reference level of the corresponding capacitor is realized.
And S108, determining the reference level of the two-bit capacitor at the tail end of the capacitor array according to the comparison results of the Nth time-2 and the Nth time-3, and comparing the reference level of the two-bit capacitor at the tail end of the capacitor array by the comparator for the Nth-1 time and outputting the comparison result.
In the embodiment of the invention, the reference levels of the last two bits of the capacitor array are determined by comparing the relationship of the two comparison results.
Step S110, determining the reference level of the last two-bit capacitor of the capacitor array according to the comparison results of the Nth time and the Nth time to 3 th time, and performing Nth time comparison and outputting the comparison result by the comparator to finish N-bit digital-to-analog conversion;
wherein the capacitance order is counted from the side far away from the input end of the comparator.
In the embodiment of the invention, before the comparison is carried out for the last time, the change of the reference levels of the last two bits of the capacitor array is determined according to the comparison results of the N-1 th and the N-3 th.
According to the digital-to-analog conversion control method provided by the embodiment of the invention, the reference level of the corresponding capacitor is adjusted according to the comparison sequence and the obtained comparison result, the energy consumption of the capacitor array DAC is reduced through the dynamic adjustment of the capacitor reference voltage, and the number of the capacitors is reduced in such a way, so that the structure is further optimized; fig. 2 shows a schematic diagram of the implementation process of the method provided by the present invention.
In one embodiment of the present invention, the output voltage of the two capacitor arrays at the 1 st comparison is determined by the following equation:
wherein: vDACP(1) And VDACN(1) Respectively output voltages of the two capacitor matrixes during the 1 st comparison; vipAnd VinThe collected input voltages of the two capacitor matrices are respectively.
In the embodiment of the invention, the output value of the capacitor array can be determined according to the adjusted reference level of the capacitor.
In one embodiment of the present invention, the output voltage of the two capacitor arrays at the 2 nd comparison is determined by the following equation:
wherein: vDACP(2) And VDACN(2) The output voltages of the two capacitor matrixes during the 2 nd comparison are respectively; vipAnd VinCollecting input voltages of the two capacitor matrixes respectively; vrefIs a reference level; d1The result is output for the 1 st comparison.
In the embodiment of the present invention, according to the adjusted reference level of the capacitor, the output voltage of the capacitor array may be determined by the above formula, where the output voltage refers to the voltage output to the comparator.
In an embodiment of the present invention, the comparing and outputting the comparison result by the comparator, based on the comparison result at least one capacitor of the capacitor array with a low output voltage being connected to the reference level, includes the following steps:
for the ith comparison, according to the result of the ith-1 comparison, the ith-1 capacitor of the capacitor array with low output voltage is connected with the reference level; wherein i is more than or equal to 3 and less than or equal to N-2.
In the embodiment of the invention, for the comparison from 3 rd time to N-2 time, the (i-1) th capacitor of the capacitor array with low output voltage is connected with the reference level; this way a dynamic adjustment of the capacitive reference voltage is achieved as the changed capacitance differs as the comparison proceeds.
In one embodiment of the present invention, the output voltage of the two capacitor arrays at the ith comparison is determined by the following equation:
wherein: vDACP(i) And VDACN(i) Respectively output voltages of the two capacitor matrixes during ith comparison; vipAnd VinCollecting input voltages of the two capacitor matrixes respectively; vrefIs a reference level; d1Outputting the result for the 1 st comparison; djThe result is output for the jth comparison.
In the embodiment of the present invention, according to the adjusted reference level of the capacitor, the output voltage of the capacitor array may be determined by the above formula, where the output voltage refers to the voltage output to the comparator.
In an embodiment of the present invention, the determining the reference level of the last two bits of capacitance of the capacitor array according to the comparison results of the N-2 th time and the N-3 rd time comprises the following steps:
when the comparison results of the N-2 th time and the N-3 rd time are equal, the reference level of the last two-bit capacitor of the capacitor array with high output voltage is VrefAnd/4, the reference level of the last capacitor of the capacitor array with low output voltage is Vref；
When the comparison results of the N-2 th time and the N-3 rd time are not equal, the reference level of the last two-bit capacitor of the capacitor array with low output voltage is Vref/4；
Wherein, VrefIs the reference level.
In the embodiment of the present invention, it should be understood that the reference level of the capacitor is Vref、Vref/4 or ground, all of which refer to a change of the reference level to Vref、VrefOr/4, ground, etc.
In an embodiment of the present invention, the determining the reference level of the last two bit capacitors of the capacitor array according to the comparison results of the N-1 st time and the N-3 rd time specifically includes the following steps:
when the comparison results of the Nth time-1 and the Nth time-3 are equal, the last capacitor of the capacitor array with high output voltage is grounded;
when the comparison results of the N-1 th time and the N-3 rd time are not equal, the 2 nd capacitance reference level of the capacitor array with high output voltage is Vref/4, and the last two-bit capacitance of the capacitor array with low output voltage is grounded;
wherein, VrefIs the reference level.
In the embodiment of the present invention, it should be understood that the reference level of the capacitor is Vref、Vref/4 or ground, all of which refer to a change of the reference level to Vref、VrefOr/4, ground, etc.
An embodiment of the present invention further provides a digital-to-analog converter, where the digital-to-analog converter includes a capacitor array DAC, and the capacitor array DAC is configured to implement digital-to-analog conversion by executing the digital-to-analog conversion control method according to the embodiment of the present invention.
In the embodiment of the invention, the digital-to-analog converter realizes the dynamic adjustment of the capacitor reference voltage by the method provided by the embodiment of the invention, thereby achieving the effects of reducing the energy consumption of the capacitor array and reducing the number of the capacitor array.
An embodiment of the present invention further provides an integrated circuit, where the integrated circuit includes the digital-to-analog converter according to the embodiment of the present invention.
In the embodiment of the present invention, specific functions of the integrated circuit are not limited, and the main point of the integrated circuit is that the digital-to-analog converter provided in the embodiment of the present invention is used, and the use of the digital-to-analog converter reduces the energy consumption of the integrated circuit, and optimizes the structure of the digital-to-analog converter.
An embodiment of the present invention further provides a data processing apparatus, which includes the digital-to-analog converter or the integrated circuit according to the embodiment of the present invention.
In the embodiment of the present invention, specific functions of the data processing device are not limited, and the data processing device is characterized in that the digital-to-analog converter provided in the embodiment of the present invention is used, and the use of the digital-to-analog converter reduces the energy consumption of the data processing device, and optimizes the structure of the digital-to-analog converter.
It should be understood that, although the steps in the flowcharts of the embodiments of the present invention are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in various embodiments may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a non-volatile computer-readable storage medium, and can include the processes of the embodiments of the methods described above when the program is executed. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A digital-to-analog conversion control method, characterized in that said digital-to-analog conversion control method is used for N-bit digital-to-analog conversion, comprising the steps of:
sampling, wherein 1 st capacitors of the two capacitor arrays are both connected with a reference level, the rest capacitors are grounded, and the comparator performs 1 st comparison and outputs a comparison result;
according to the 1 st comparison result, the 1 st capacitor of the capacitor array with high output voltage is grounded, and the comparator performs the 2 nd comparison and outputs the comparison result;
according to the previous comparison result, at least one capacitor of the capacitor array with low output voltage is connected with a reference level, and the comparator compares and outputs a comparison result; repeating the steps until the N-2 comparison is completed;
determining the reference level of two-bit capacitors at the tail of the capacitor array according to the comparison results of the Nth time-2 and the Nth time-3, and comparing the reference level for the Nth-1 time by using a comparator and outputting a comparison result;
determining the reference level of the last two-bit capacitor of the capacitor array according to the comparison results of the Nth time and the Nth-3 th time, and performing Nth time comparison and outputting the comparison result by the comparator to finish N-bit digital-to-analog conversion;
wherein N is a positive integer; the capacitance order is counted from the side remote from the comparator input.
2. The digital-to-analog conversion control method according to claim 1, wherein at the time of the 1 st comparison, the output voltages of the two capacitor arrays are determined by the following formula:
wherein: vDACP(1) And VDACN(1) Respectively output voltages of the two capacitor matrixes during the 1 st comparison; vipAnd VinThe collected input voltages of the two capacitor matrices are respectively.
3. The digital-to-analog conversion control method according to claim 1, wherein at the 2 nd comparison, the output voltages of the two capacitor arrays are determined by the following formula:
wherein: vDACP(2) And VDACN(2) The output voltages of the two capacitor matrixes during the 2 nd comparison are respectively; vipAnd VinCollecting input voltages of the two capacitor matrixes respectively; vrefIs a reference level; d1The result is output for the 1 st comparison.
4. The digital-to-analog conversion control method according to claim 1, wherein the comparator compares at least one capacitor of the capacitor array having a low output voltage with a reference level according to the previous comparison result and outputs the comparison result, and comprises the steps of:
for the ith comparison, according to the result of the ith-1 comparison, the ith-1 capacitor of the capacitor array with low output voltage is connected with the reference level; wherein i is more than or equal to 3 and less than or equal to N-2.
5. The digital-to-analog conversion control method according to claim 4, wherein the output voltages of the two capacitor arrays at the ith comparison are determined by the following formula:
wherein: vDACP(i) And VDACN(i) Respectively output voltages of the two capacitor matrixes during ith comparison; vipAnd VinCollecting input voltages of the two capacitor matrixes respectively; vrefIs a reference level; d1Outputting the result for the 1 st comparison; djThe result is output for the jth comparison.
6. The DAC control method according to claim 1, wherein the determining the reference levels of the last two capacitors of the capacitor array according to the N-2 th and N-3 rd comparison results comprises the following steps:
when the comparison results of the N-2 th time and the N-3 rd time are equal, the reference level of the last two-bit capacitor of the capacitor array with high output voltage is VrefAnd/4, the reference level of the last capacitor of the capacitor array with low output voltage is Vref；
When the comparison results of the N-2 th time and the N-3 rd time are not equal, the reference level of the last two-bit capacitor of the capacitor array with low output voltage is Vref/4；
Wherein, VrefIs the reference level.
7. The digital-to-analog conversion control method according to claim 1, wherein the determining the reference level of the last two-bit capacitor of the capacitor array according to the comparison results of the N-1 st time and the N-3 rd time specifically comprises the following steps:
when the comparison results of the Nth time-1 and the Nth time-3 are equal, the last capacitor of the capacitor array with high output voltage is grounded;
when the comparison results of the N-1 th time and the N-3 rd time are not equal, the 2 nd capacitance reference level of the capacitor array with high output voltage is Vref/4, and the last two-bit capacitance of the capacitor array with low output voltage is grounded;
wherein, VrefIs the reference level.
8. A digital-to-analog converter, characterized in that it comprises a capacitor array DAC for performing digital-to-analog conversion by performing the digital-to-analog conversion control method of any one of claims 1 to 7.
9. An integrated circuit comprising the digital-to-analog converter of claim 8.
10. A data processing device, characterized in that the data processing device comprises a digital-to-analog converter as claimed in claim 8 or an integrated circuit as claimed in claim 9.
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| CN107147393A (en) * | 2017-05-09 | 2017-09-08 | 中国电子科技集团公司第二十四研究所 | ADC self-correcting positive circuits based on successive approximation algorithm |
| CN107231153A (en) * | 2017-05-09 | 2017-10-03 | 大连理工大学 | Gradually-appoximant analog-digital converter for monolithic integrated sensor |
| CN111327324A (en) * | 2020-04-10 | 2020-06-23 | 上海交通大学 | Capacitor array structure suitable for successive approximation type analog-to-digital converter |
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