CN112002709A - Array substrate, array substrate manufacturing method and display panel - Google Patents
Array substrate, array substrate manufacturing method and display panel Download PDFInfo
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- CN112002709A CN112002709A CN202010801836.7A CN202010801836A CN112002709A CN 112002709 A CN112002709 A CN 112002709A CN 202010801836 A CN202010801836 A CN 202010801836A CN 112002709 A CN112002709 A CN 112002709A
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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Abstract
The embodiment of the application provides an array substrate, an array substrate manufacturing method and a display panel, wherein the array substrate comprises: the semiconductor device comprises a substrate, a semiconductor layer, a grid layer and a source drain layer. According to the method, the semiconductor layer and the source-drain layer are adopted to replace a second gate layer (GE2) for forming the first voltage line in the related technology, so that the processes of film forming, exposure, development, etching and stripping of GE2 can be omitted in the manufacturing process, the manufacturing process of the array substrate is simplified, and the production efficiency can be improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate, an array substrate manufacturing method, and a display panel.
Background
AMOLEDs are rapidly being developed due to their unique advantages. The array substrate with which the AMOLED is collocated is mainly an LTPS array substrate. In order to solve the problem of poor polysilicon uniformity of the AMOLED LTPS, a pixel compensation circuit is required to be adopted in a sub-pixel driving circuit of the AMOLED LTPS array substrate, and in order to form the pixel compensation circuit, the film formation, exposure, development, etching and photoresistive stripping of each layer of a polysilicon (Poly) layer graph, a first grid electrode (GE1) layer graph, a second grid electrode layer (GE2) layer graph and a Source Drain (SD) layer graph and the deposition of an insulating layer between conducting layers are required, so that the manufacturing process is complex.
Disclosure of Invention
The embodiment of the application provides an array substrate, an array substrate manufacturing method and a display panel, which reduce the arrangement of a film layer and simplify the manufacturing process.
The application provides an array substrate, includes:
the substrate comprises a first surface and a second surface which are oppositely arranged;
a semiconductor layer disposed on the first surface, the semiconductor layer for forming a signal line;
the gate layer is arranged on one side, far away from the first face, of the semiconductor layer and is used for forming a scanning line;
the source-drain layer is arranged on one side, far away from the semiconductor layer, of the gate layer and is used for forming a data line, a first voltage line and a second voltage line;
the signal line is electrically connected to the first voltage line, and the signal line provides a first voltage signal to the first voltage line.
In some embodiments, the gate layer is further used for forming a first capacitor plate and a first jumper wire, and the source drain layer is further used for forming a second capacitor plate and a second jumper wire; the first capacitor plate and the second capacitor plate form a capacitor plate, and the capacitor plate is electrically connected with the capacitor plate through the first jumper wire and the second jumper wire.
In some embodiments, the signal line, the scan line, the first jumper line, and the second jumper line are arranged in a column direction, the data line, the first voltage line, and the second voltage line are arranged in a row direction, the first jumper line overlaps the first voltage line and the data line, the first jumper line is connected to the second jumper line, one end of the second jumper line is connected to the first jumper line, and the other end of the second jumper line is connected to the second capacitor plate to form a network structure.
In some embodiments, the second voltage line is electrically connected to the capacitor plate through the second capacitor plate.
In some embodiments, the scan lines cross the data lines to define sub-pixel driving regions, and the capacitor plates are correspondingly disposed in the sub-pixel driving regions.
In some embodiments, the semiconductor device further includes an interlayer insulating layer disposed between the semiconductor layer and the gate layer, and between the gate layer and the source and drain layers.
In some embodiments, the semiconductor device further includes a plurality of via holes disposed on the interlayer insulating layer, and the semiconductor layer, the gate layer, and the source/drain layer are electrically connected through the via holes.
The embodiment of the application provides an array substrate processing method, which comprises the following steps:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged;
providing a semiconductor layer on the first surface, the semiconductor layer forming a signal line;
arranging a grid layer on one side of the semiconductor layer, which is far away from the first surface, wherein the grid layer forms a scanning line;
arranging a source-drain layer on one side of the gate layer, which is far away from the semiconductor layer, wherein the source-drain layer forms a data line, a first voltage line and a second voltage line;
the signal line is electrically connected to the first voltage line, and the signal line provides a first voltage signal to the first voltage line.
In some embodiments, further comprising: the gate layer forms a first capacitor plate and a first crossover line; the source and drain layers form a second capacitor plate and a second jumper wire;
the first capacitor plate and the second capacitor plate form a capacitor plate, and the capacitor plate is electrically connected with the capacitor plate through the first jumper wire and the second jumper wire.
The embodiment of the application provides a display panel, which comprises the array substrate.
The array substrate provided by the embodiment of the application comprises: the semiconductor device comprises a substrate, a semiconductor layer, a grid layer and a source drain layer. The array substrate adopts the semiconductor layer and the source-drain layer to replace a second gate layer (GE2) for forming the first voltage line in the related technology, so that the processes of film forming, exposure, development, etching and stripping of GE2 can be omitted in the manufacturing process, the manufacturing process of the array substrate is simplified, and the production efficiency can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a first structure of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a first top-view structure of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic view of a second structure of an array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a second top-down structure of an array substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic partial side view of an array substrate according to an embodiment of the present disclosure;
FIG. 6 is a first flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure;
FIG. 7 is a second flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present application.
Embodiments of the present invention provide an array substrate, a method for manufacturing the array substrate, and a display panel.
Referring to fig. 1 and fig. 2, fig. 1 is a first structural diagram of an array substrate 10 according to an embodiment of the present disclosure, fig. 2 is a first top-view structural diagram of the array substrate 10 according to the embodiment of the present disclosure, and fig. 2 does not show a substrate 101. The array substrate 10 includes a substrate 101, a semiconductor layer 102, a gate layer 103, and a source/drain layer 104. The substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to each other. The semiconductor layer 102 is provided on the first surface 101a, and the semiconductor layer 101 is used to form a signal line 201. The gate layer 103 is disposed on a side of the semiconductor layer 102 away from the first face 101a, and the gate layer 103 is used to form a scan line 202. The source-drain layer 104 is provided on a side of the gate layer 103 away from the semiconductor layer 102, and the source-drain layer 104 is used to form a data line 203, a first voltage line 204, and a second voltage line 205. The signal line 201 is electrically connected to the first voltage line 204, and the signal line 201 provides the first voltage signal to the first voltage line 204. In the pixel compensation circuit, a plurality of signal lines 201, a plurality of scan lines 202, a plurality of data lines 203, a plurality of first voltage lines 204, and a plurality of second voltage lines 205 may be disposed according to different requirements of different display panels, and the arrangement and number of the signal lines 201, the scan lines 202, the data lines 203, the first voltage lines 204, and the second voltage lines 205 in fig. 2 are only examples and are not intended to limit the present application.
The first surface 101a may be an upper surface of the substrate 101, and the second surface 101b may be a lower surface of the substrate 101. Of course, the first surface 101a may be a lower surface of the substrate 101, and the second surface 101b may be an upper surface of the substrate 101. In the embodiment of the present application, it is assumed that the first surface 101a is the upper surface of the substrate 101 and the second surface 101b is the lower surface of the substrate 101 without specific description.
The semiconductor layer 102 is made of Low Temperature Polysilicon (LTPS), and the Low Temperature Polysilicon (LTPS) is used to fabricate the array substrate, so that the product cost is Low and the electron mobility of the device is high.
In the embodiment of the application, the semiconductor layer 101 is adopted to form the signal line 201 and the source-drain layer 104 is adopted to form the first voltage line 204, the signal line 201 is electrically connected with the first voltage line 204, and the first voltage signal is provided for the pixel compensation circuit together to replace the first voltage line formed by the second gate layer (GE2) in the related art. The material resistance of the source-drain layer 104 is small, and meanwhile, the signal line 201 formed by the semiconductor layer 101 and the first voltage line 204 formed by the source-drain layer 104 are arranged at an angle, and are electrically connected in different film layers to form a network structure, so that the voltage Drop (IR Drop) can be reduced. In addition, the array substrate 10 provided in the embodiment of the present application can omit the preparation of the GE2 layer in the manufacturing process, i.e., a series of processes of film formation, exposure, development, etching, and peeling of the GE2 layer, so that the manufacturing process of the array substrate can be effectively simplified, the production progress is accelerated, and the production efficiency is improved.
Referring to fig. 3, fig. 3 is a schematic diagram of a second structure of the array substrate 10 according to the embodiment of the present disclosure. The array substrate 10 in this embodiment further includes an interlayer insulating layer 105, and the interlayer insulating layer 105 is disposed between the semiconductor layer 102 and the gate layer 103, and between the gate layer 103 and the source/drain layer 104.
Referring to fig. 4, fig. 4 is a schematic diagram of a second top view structure of the array substrate 10 according to the embodiment of the present application, and fig. 4 does not show the substrate 101. The array substrate 10 further includes a plurality of via holes 106, the via holes 106 are disposed on the interlayer insulating layer 105, and the semiconductor layer 102, the gate layer 103, and the source-drain layer 104 are electrically connected through the via holes 106.
The gate layer 103 is further used to form a first capacitor plate 2061 and a first jumper line 207, and the source-drain layer 104 is further used to form a second capacitor plate 2062 and a second jumper line 208. The first capacitor plate 2061 and the second capacitor plate 2062 form a capacitor plate 206, and the capacitor plate 206 is electrically connected to the capacitor plate 206 through a first jumper wire 207 and a second jumper wire 208. In this case, since the first jumper line 207 and the second jumper line 208 are disposed at different film layers, the first jumper line 207 and the second jumper line 208 can be connected through the via hole 106. As in the related art, the second capacitor plate is formed using GE2 layer. In the embodiment of the application, the source/drain layer 104 is used to form the second capacitor plate 2062, and the source/drain layer 104 is used to further replace the GE2 layer, so that the effect of comprehensively replacing the GE2 layer is achieved.
The scanning lines 202 and the data lines 203 intersect to define a sub-pixel driving region 20a, and the capacitor plates 206 are correspondingly disposed in the sub-pixel driving region 20 a. Such an arrangement may facilitate connection of the capacitive plate 206 in the pixel compensation circuit, simplifying circuit design.
The signal line 201 and the first voltage line 204 provide the pixel compensation circuit with a first voltage signal, which may be a reset voltage signal V1. The second voltage line 205 supplies a second voltage signal, which may be a high voltage VDD, to the pixel compensation circuit. The scan line 202 supplies the scan signal scan (n) of the present row to the pixel compensation circuit, and the Data line 203 supplies the Data signal Data to the pixel compensation circuit. The specific arrangement of the pixel compensation circuit is not limited, and may be, for example, the conventional arrangement of 7T1C (i.e. 7 TFTs and one capacitor C).
Among them, the gate layer 103 also forms an emission control line 209, and the emission control line 209 is used to supply an emission control signal EM to the pixel compensation circuit.
The signal line 201, the scanning line 202, the first jumper line 207, the second jumper line 208, and the light emission control line 209 are arranged in a column direction, and the data line 203, the first voltage line 204, and the second voltage line 205 are arranged in a row direction. Where the column direction is the direction extending along the y-axis in fig. 4 and the row direction is the direction extending along the x-axis in fig. 4. The extension and angle of the x-axis and y-axis in the figures are only examples and should not be construed as limiting the present application.
The array substrate 10 is provided with an effective display area and a non-effective display area, the structure is arranged in the effective display area, signal routing formed by the GE2 layer in the non-effective display area is replaced by forming signal routing by using the gate layer 103, and a capacitance plate formed by the GE2 layer in the non-effective display area is replaced by using the semiconductor layer 102 and the source-drain layer 104. The substitution method refers to the substitution method in the effective display area, and is not described herein again.
Specifically, referring to fig. 5, fig. 5 is a schematic partial side view of the array substrate 10 according to the embodiment of the present disclosure. The first jumper line 207 overlaps the first voltage line 204 and the data line 203, the first jumper line 207 is connected to the second jumper line 208, one end of the second jumper line 208 is connected to the first jumper line 207, and the other end of the second jumper line 208 is connected to the second capacitor plate 2062 to form a network structure. The second voltage line 205 is electrically connected to the capacitor plate 206 through a second capacitor plate 2062. After the network structure is formed, when a second voltage line 205 in the circuit is disconnected or a via hole from the second voltage line 205 to the capacitor plate 206 is abnormal, the pixel compensation circuit can also work normally. Meanwhile, the network structure can reduce the resistance of the second voltage line 205, and the second voltage signal provided by the second voltage line 205 is more uniformly distributed in the plane, thereby preventing uneven display.
In the array substrate 10 provided in the embodiment of the application, the semiconductor layer 101 is used to form the signal line 201 and the source-drain layer 104 is used to form the first voltage line 204, and the signal line 201 is electrically connected to the first voltage line 204, so as to provide the first voltage signal to the pixel compensation circuit together, so as to replace the first voltage line formed by the second gate layer (GE2) in the related art. The source-drain layer 104 has low material resistance, and the semiconductor layer 101 and the source-drain layer 104 form a network in a plane, which can reduce a voltage Drop (IR Drop). Further, the GE2 layer can be completely eliminated in the effective display region by replacing the second capacitor plate formed by the second gate layer (GE2) in the related art with the second capacitor plate 2062 formed by the source/drain layer 104. The GE2 signal traces and the capacitor substrate in the inactive display area can be replaced by the same method, thereby completely eliminating the GE2 layer on the array substrate 10. The preparation of a GE2 layer in the manufacturing process can be omitted, a series of processes of film forming, exposure, development, etching and stripping of the GE2 layer can be omitted, the deposition of an interlayer insulating layer is omitted, the manufacturing process of the array substrate is simplified more effectively, the production progress is accelerated, and the production efficiency is improved.
Referring to fig. 6, fig. 6 is a first flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure.
301. A substrate is provided, and the substrate comprises a first surface and a second surface which are oppositely arranged.
302. A semiconductor layer is provided on the first surface, the semiconductor layer forming a signal line.
Specifically, an organic film is formed on the first surface by adopting a deposition, evaporation or ink-jet printing method, then a patterned photoresist layer is arranged on the organic film, and the exposure, the development and the etching treatment are sequentially carried out, and then the patterned photoresist layer is stripped to form a semiconductor layer.
Wherein, a semiconductor layer is arranged on the first surface by adopting a deposition method. Specifically, in one embodiment, amorphous silicon (α -Si) is deposited on the first side using Chemical Vapor Deposition (CVD). After the amorphous silicon film is formed, the amorphous silicon film is irradiated by Excimer Laser through an Excimer Laser Annealing (Excimer Laser Annealing) process, so that the conversion from the alpha-Si film to the organic silicon film (Poly Si) is realized, and a semiconductor layer is formed by the organic silicon film. The semiconductor layer of the semiconductor layer adopts a deposition method, has high speed, compact film layer and good adhesiveness, and is very suitable for large-scale and high-efficiency industrial production.
Wherein, a semiconductor layer is arranged on the first surface by adopting an evaporation method. Specifically, the semiconductor layer material is evaporated or sublimated into gaseous particles, the gaseous particles are conveyed to the first surface, the gaseous particles are attached to the surface of the first surface to be nucleated and grow into a solid film, and then atoms of the solid film are reconstructed or chemically bonded to form the semiconductor layer. The evaporation method is simple, and the film layer has high purity and compactness.
Wherein a semiconductor layer is provided on the first surface by an ink-jet printing method. Specifically, a semiconductor layer material is inkjet printed on the first face, subjected to planarization treatment and drying, and baked to obtain a semiconductor layer. The ink jet printing method can accurately control the film forming area, save materials, reduce the cost and improve the yield of products.
303. And arranging a gate layer on the side of the semiconductor layer far away from the first surface, wherein the gate layer forms a scanning line.
Specifically, the method for forming the scan lines in the gate layer is the same as the method for forming the signal lines in the semiconductor layer and the semiconductor layer, and the description thereof is omitted.
304. And arranging a source drain layer on one side of the gate layer, which is far away from the semiconductor layer, wherein the source drain layer forms a data line, a first voltage line and a second voltage line. The signal line is electrically connected with the first voltage line, and the signal line provides a first voltage signal to the first voltage line.
Specifically, the method for forming the scan lines in the gate layer is the same as the method for forming the signal lines in the semiconductor layer and the semiconductor layer, and the description thereof is omitted.
The signal line is electrically connected with the first voltage line by arranging the communication hole.
Referring to fig. 7, fig. 7 is a second flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure.
401. A substrate is provided, and the substrate comprises a first surface and a second surface which are oppositely arranged.
402. A semiconductor layer is provided on the first surface, the semiconductor layer forming a signal line.
403. And arranging a grid layer on one side of the semiconductor layer, which is far away from the first surface, wherein the grid layer forms a scanning line, a first capacitor plate and a first bridging line.
404. And arranging a source drain layer on one side of the gate layer, which is far away from the semiconductor layer, wherein the source drain layer forms a data line, a first voltage line, a second capacitor plate and a second jumper line. The signal line is electrically connected with the first voltage line, and the signal line provides a first voltage signal to the first voltage line.
The specific process is the same as the previous embodiment, and is not described herein again.
The semiconductor device further comprises an interlayer insulating layer arranged between the semiconductor layer and the grid layer and between the grid layer and the source drain layer, a communication hole is arranged on the interlayer insulating layer according to circuit connection requirements, and the communication hole is electrically connected with the semiconductor layer, the grid layer and the source drain layer.
According to the array substrate processing method provided by the embodiment of the application, as the preparation of the GE2 layer is omitted, namely a series of processes of film forming, exposure, development, etching and stripping of the film layer are omitted, and the preparation of the interlayer insulating layer is omitted, the array substrate processing process can be effectively simplified, the production progress is accelerated, and the production efficiency is improved.
The present embodiment provides a display panel 100, and fig. 8 is a schematic structural diagram of the display panel 100 in the present embodiment. The display panel 100 includes the array substrate 10 and the package structure 20, and the display panel 100 may further include other devices. The package structure 20 and other devices and their assembly in the embodiments of the present application are well known to those skilled in the art and will not be described herein in detail.
The display panel 100 provided in the embodiment of the present application includes an array substrate 10 and a package structure 20, where the array substrate 10 includes a substrate, a semiconductor layer, a gate layer, and a source/drain layer. The display panel replaces a second gate layer (GE2) forming the first voltage lines in the related art with a semiconductor layer and source-drain layers. The preparation of the GE2 layer in the manufacturing process can be omitted, a series of processes of film forming, exposure, development, etching and stripping of the film layer can be omitted, the manufacturing process of the array substrate can be effectively simplified, the production progress is accelerated, and the production efficiency is improved.
The array substrate, the array substrate manufacturing method and the display panel provided in the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein using specific examples, and the description of the embodiments above is only used to help understanding the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An array substrate, comprising:
the substrate comprises a first surface and a second surface which are oppositely arranged;
a semiconductor layer disposed on the first surface, the semiconductor layer for forming a signal line;
the gate layer is arranged on one side, far away from the first face, of the semiconductor layer and is used for forming a scanning line;
the source-drain layer is arranged on one side, far away from the semiconductor layer, of the gate layer and is used for forming a data line, a first voltage line and a second voltage line;
the signal line is electrically connected to the first voltage line, and the signal line provides a first voltage signal to the first voltage line.
2. The array substrate of claim 1, wherein the gate layer is further configured to form a first capacitor plate and a first jumper line, and the source drain layer is further configured to form a second capacitor plate and a second jumper line; the first capacitor plate and the second capacitor plate form a capacitor plate, and the capacitor plate is electrically connected with the capacitor plate through the first jumper wire and the second jumper wire.
3. The array substrate of claim 2, wherein the signal line, the scan line, the first jumper line, and the second jumper line are arranged in a column direction, the data line, the first voltage line, and the second voltage line are arranged in a row direction, the first jumper line overlaps the first voltage line and the data line, the first jumper line is connected to the second jumper line, one end of the second jumper line is connected to the first jumper line, and the other end of the second jumper line is connected to the second capacitor plate to form a network structure.
4. The array substrate of claim 3, wherein the second voltage line is electrically connected to the capacitor plate through the second capacitor plate.
5. The array substrate of claim 2, wherein the scan lines cross the data lines to define sub-pixel driving regions, and the capacitor plates are correspondingly disposed in the sub-pixel driving regions.
6. The array substrate of claim 1, further comprising an interlayer insulating layer disposed between the semiconductor layer and the gate layer, and between the gate layer and the source drain layer.
7. The array substrate of claim 6, further comprising a plurality of via holes disposed on the interlayer insulating layer, wherein the semiconductor layer, the gate layer, and the source/drain layer are electrically connected through the via holes.
8. A method for manufacturing an array substrate includes:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are oppositely arranged;
providing a semiconductor layer on the first surface, the semiconductor layer forming a signal line;
arranging a grid layer on one side of the semiconductor layer, which is far away from the first surface, wherein the grid layer forms a scanning line;
arranging a source-drain layer on one side of the gate layer, which is far away from the semiconductor layer, wherein the source-drain layer forms a data line, a first voltage line and a second voltage line;
the signal line is electrically connected to the first voltage line, and the signal line provides a first voltage signal to the first voltage line.
9. The array substrate processing method of claim 8, further comprising: the gate layer forms a first capacitor plate and a first crossover line; the source and drain layers form a second capacitor plate and a second jumper wire;
the first capacitor plate and the second capacitor plate form a capacitor plate, and the capacitor plate is electrically connected with the capacitor plate through the first jumper wire and the second jumper wire.
10. A display panel comprising an array substrate according to any one of claims 1 to 7.
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Cited By (1)
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| CN113192977A (en) * | 2021-04-09 | 2021-07-30 | 武汉华星光电半导体显示技术有限公司 | Array substrate and display panel |
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| CN112002709B (en) | 2022-09-27 |
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