CN112002692A - Transistor for electrostatic protection and manufacturing method thereof - Google Patents

Transistor for electrostatic protection and manufacturing method thereof Download PDF

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Publication number
CN112002692A
CN112002692A CN202010783760.XA CN202010783760A CN112002692A CN 112002692 A CN112002692 A CN 112002692A CN 202010783760 A CN202010783760 A CN 202010783760A CN 112002692 A CN112002692 A CN 112002692A
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region
type
transistor
type region
type well
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CN112002692B (en
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陆阳
王炜槐
韩广涛
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Joulwatt Technology Hangzhou Co Ltd
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Joulwatt Technology Hangzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to the field of electrostatic protection, and provides a transistor for electrostatic protection and a manufacturing method thereof. Compared with the prior art, the drain structure of the transistor is newly adjusted, a metal silicide barrier layer is omitted, the manufacturing cost is saved, the size is reduced to a certain extent, and the same ESD current discharge capacity can be achieved.

Description

Transistor for electrostatic protection and manufacturing method thereof
Technical Field
The invention relates to the field of electrostatic protection, in particular to a transistor for electrostatic protection and a manufacturing method thereof.
Background
Electrostatic discharge (ESD) is an objectively occurring natural phenomenon that accompanies the entire cycle of a product. In the manufacturing, packaging and testing stages of the chip, certain charges are accumulated in the external environment and the internal structure of the chip, and the chip is threatened by static electricity at any time. There are two approaches to electrostatic protection of integrated circuits: one is to control and reduce the generation of static electricity and discharge, such as using static protective clothing, static-free wrist straps, etc.; secondly, a static electricity leakage device is designed at the periphery of the chip to provide a leakage path for static electricity. The electrostatic discharge device in the second approach is equivalent to a "lightning rod" in an Integrated Circuit (IC), and prevents current from flowing into an internal circuit of the IC to cause damage during electrostatic discharge, which is the most direct and common protection measure at present. However, as the feature size of the device is continuously reduced and the feature size of the device is continuously improved, the design window of the ESD device is smaller and more difficult, and an ESD protection device with small chip area and good electrostatic discharge capability is required, which becomes a challenge for the integrated circuit engineer.
Therefore, in chip design, ESD protection devices are required to be placed at each pin for protecting the chip from power-off and power-on states. In conventional designs, the fet is often used as an ESD protection device, which is compatible with most CMOS (Complementary Metal Oxide Semiconductor) processes.
Fig. 1 is a circuit diagram showing a conventional field effect transistor for ESD protection, fig. 2 is an equivalent circuit diagram of fig. 1, referring to fig. 1, in which cathodes are electrically connected to a metal silicide layer 108 on a first P-type region 103, a first N-type region 104 and a polysilicon layer 107, respectively, and the first P-type region 103, the first N-type region 104 and the polysilicon layer 107, and a third N-type region 105 are all located in a P-type well region 102 on a substrate 101, a gate oxide layer 106 and a polysilicon layer 107 stacked in sequence on the surface of the substrate 101 form a gate structure, an anode is connected to the metal silicide layer 108 on the third N-type region 105, and a field oxide region 109 on the surface of the substrate 101 is spaced to isolate the first P-type region 103, the first N-type region 104 and the polysilicon layer 107, and the third N-type region 105, and when ESD protection is implemented using the field effect transistor for a lead, a drain region (the third N-type region 105) needs to be pulled apart by a distance, and a ballast resistor R0 is formed by removing part of the metal silicide layer in the area by using the metal silicide barrier mask in the manufacturing process, as shown in FIG. 2, the ballast resistor R0 is connected between the cathode and the drain of the transistor T11, and the P-well resistor R11 is connected between the gate and the source (anode) of the transistor T11, so as to improve the uniformity of the field effect transistor in ESD current discharge.
However, in the above scheme, a metal silicide mask is also used in the manufacturing of the field effect transistor for the pin ESD protection device, which increases the production cost, and the width of the formed drain region (the third N-type region 105) is limited, so that the size of the formed device is difficult to reduce, and the application is limited.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a transistor for electrostatic protection and a method for manufacturing the same, which can save the manufacturing cost and reduce the size of the formed device while achieving ESD protection.
In one aspect, the present invention provides a transistor for electrostatic protection, comprising:
the device comprises a P-type well region and an N-type well region which are positioned in a substrate, wherein the P-type well region is connected with the N-type well region;
the first P-type region, the first N-type region and the grid structure are sequentially arranged on the P-type well region at intervals, and the grid structure comprises a grid oxide layer and a polycrystalline silicon layer which are sequentially stacked on a substrate;
the second N-type region and the third N-type region are sequentially arranged on the N-type well region at intervals, the second N-type region crosses over the junction of the N-type well region and the P-type well region, and the first N-type region and the second N-type region are positioned on two sides of the grid structure;
and the metal silicide layer is positioned on the substrate and distributed on the upper surfaces of the first P-type region, the first N-type region, the grid structure, the second N-type region and the third N-type region.
Preferably, the transistor further includes:
and a plurality of field oxide regions spaced apart from each other on the substrate, the plurality of field oxide regions being disposed on both sides of the first P-type region and the third N-type region and separating the first P-type region and the first N-type region and the second N-type region and the third N-type region.
Preferably, the metal silicide layers on the first P-type region, the first N-type region and the grid structure are electrically connected together and led out to be used as a cathode of the transistor;
the metal silicide layer on the third N-type region is led out to be used as an anode of the transistor,
the anode is an electrostatic inlet end, and the cathode is an earth end.
Preferably, a discharge path of the electrostatic current is formed from the anode to the second N-type well region through the third N-type region.
Preferably, the substrate is a P-type substrate.
Preferably, the transistor is a field effect transistor.
In another aspect, the present invention further provides a method for manufacturing a transistor for electrostatic protection, including:
sequentially performing ion implantation on the substrate to form a P-type well region and an N-type well region, wherein the formed P-type well region is connected with the N-type well region;
forming a plurality of field oxide regions arranged at intervals on the substrate, wherein the field oxide regions sequentially define a source end region and a gate end region which are positioned in the P-type well region and a drain end region which is positioned in the N-type well region:
sequentially depositing a gate oxide layer and a polysilicon layer on a gate end region on a substrate to form a gate structure, etching two sides of the gate structure to define a first injection region and a second injection region, and enabling the second injection region to cross the junction of the N-type well region and the P-type well region;
sequentially performing ion implantation on the source end region and the first implantation region to form a first P-type region and a first N-type region;
sequentially performing ion implantation on the second implantation region and the drain region to form a second N-type region and a third N-type region;
and forming a metal silicide layer on the substrate, wherein the formed metal silicide layer is distributed on the upper surfaces of the first P-type region, the first N-type region, the gate structure, the second N-type region and the third N-type region.
Preferably, the manufacturing method further comprises, after forming the metal silicide layer on the substrate:
electrically connecting and leading out the metal silicide layers positioned on the first P-type area, the first N-type area and the grid structure to be used as a cathode of the transistor;
and leading out the metal silicide layer on the third N-type region as the anode of the transistor.
Preferably, the transistor formed is a field effect transistor.
Preferably, the manufacturing method forms a discharge path of the electrostatic current from the anode to the second N-well region through the third N-type region.
The invention has the beneficial effects that: the method for manufacturing a transistor for electrostatic protection, provided by the embodiment of the invention, comprises the steps of sequentially forming a P-type well region and an N-type well region connected with the P-type well region on a substrate, performing ion implantation by utilizing a plurality of field oxide regions and gate structures which are arranged on the surface of the substrate at intervals to sequentially form a first P-type region and a first N-type region which are positioned in the P-type well region, a second N-type region and a third N-type region which are positioned in the N-type well region, electrically connecting and leading out a metal silicide layer distributed on the first P-type region, the first N-type region and the gate structures to be used as a cathode of the transistor, leading out a metal silicide layer positioned on the third N-type region to be used as an anode of the transistor, thereby forming the transistor for electrostatic protection, compared with the prior art, carrying out new adjustment on a drain end structure of the transistor, omitting a metal silicide blocking layer, the manufacturing cost is saved and the size is reduced, and the same ESD current discharge capacity can be achieved.
In the transistor for electrostatic protection provided in the embodiment of the present invention, the second N-type region, the N-type well region, and the third N-type region, in the equivalent circuit of the transistor, serve as an N-well resistor and are connected between the anode and the drain terminal, and the second N-type region crosses over the boundary between the N-type well region and the P-type well region, which serves as the drain terminal of the transistor on one hand and also serves as a connection terminal of the N-well resistor on the other hand, so that a leakage path is formed for electrostatic current from the anode to the second N-type well region through the third N-type region via the N-type well region.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a circuit configuration diagram showing a conventional field effect transistor for ESD protection;
FIG. 2 shows an equivalent circuit diagram of the FET of FIG. 1;
fig. 3 is a circuit diagram of a field effect transistor for ESD protection according to an embodiment of the present invention;
FIG. 4 shows an equivalent circuit diagram of the FET of FIG. 3;
FIG. 5 is a flow chart illustrating a method for manufacturing a field effect transistor for ESD protection according to an embodiment of the present invention;
fig. 6a to 6f are schematic cross-sectional views illustrating the structure formed at various stages of the manufacturing method of the field effect transistor in fig. 5.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another area, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
Unless otherwise specified below, various layers or regions of a semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge. The gate conductor, electrode layer may be formed of various conductive materials such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" refers to extending in a direction substantially perpendicular to the depth direction of the trench.
The following describes the embodiments of the present invention in further detail with reference to the drawings and examples.
Fig. 3 is a circuit diagram of a field effect transistor for ESD protection according to an embodiment of the present invention, and fig. 4 is an equivalent circuit diagram of the field effect transistor in fig. 3.
Referring to fig. 3, a field effect transistor 200 for ESD protection according to an embodiment of the present invention includes: a P-type substrate 201, a P-type well region 202, an N-type well region 203, a first P-type region 204, a first N-type region 205, a gate structure, a second N-type region 207, a third N-type region 208, a metal silicide layer 210 and a plurality of field oxide regions 211, in particular, the P-type well region 202 and the N-type well region 203 in the substrate are connected, the first P-type region 204, the first N-type region 205 and the gate structure are sequentially arranged on the P-type well region 202 at intervals, the gate structure comprises a gate oxide layer 206 and a polysilicon layer 209 sequentially stacked on the P-type substrate 201, the second N-type region 207 and the third N-type region 208 are sequentially arranged on the N-type well region 203 at intervals, the second N-type region 207 crosses the boundary of the N-type well region 203 and the P-type well region 202, the first N-type region 205 and the second N-type region 207 are arranged at two sides of the gate structure, the metal silicide layer 210 is arranged on the P-type substrate 201, distributed on the upper surfaces of the first P-type region 204, the first N-type region 205, the gate structure, the second N-type region 207 and the third N-type region 208, a plurality of field oxide regions 211 are disposed on the P-type substrate 201 at intervals, the plurality of field oxide regions 211 are distributed on both sides of the first P-type region 204 and the third N-type region 208, and separate the first P-type region 204 from the first N-type region 205, and the second N-type region 207 from the third N-type region 208.
Furthermore, the metal silicide layer 210 on the first P-type region 204, the first N-type region 205 and the gate structure are electrically connected together and led out to serve as a cathode of the fet 200, the metal silicide layer 211 on the third N-type region 208 is led out to serve as an anode of the fet 200, the anode is an electrostatic inlet, and the cathode is a ground.
In the present embodiment, the second N-type region 207, the N-type well region 203, and the third N-type region 208 function as an N-well resistor R22 in the equivalent circuit of the fet 200, as shown in fig. 4, the N-well resistor R22 is connected between the cathode and the drain of the fet T21, and the P-well resistor R21 is connected between the gate and the source (anode) of the fet T21.
In this embodiment, the second N-type region 207 crosses over the boundary between the N-type well region 203 and the P-type well region 202, which serves as the drain of the fet 200 on one hand and also as one connection terminal of the N-well resistor R22 on the other hand, so that a leakage path is formed from the anode through the third N-type region 208 from the N-type well region 203 to the second N-type well region 207, and a ballast resistor formed by removing a portion of metal silicide through a metal silicide blocking layer as a mask in the prior art is changed to an N-well resistor, thereby saving the mask, and since the N-well resistor is larger than the N + resistor and there is no need to limit the forming width of the drain region of the device, the size of the device can be reduced, and the same ballast resistor can be formed, thereby achieving the same ESD current discharge capability.
In an integrated circuit (chip) applying the field effect transistor for electrostatic protection, when an anode and a cathode are connected into the integrated circuit (chip) through a connecting pin, the size of leakage current is changed through voltage clamping by an N-well resistor positioned at the front end of the pin, so that the ESD protection is realized, and the damage of electrostatic current to the inside of a device is avoided.
Fig. 5 is a schematic flow chart illustrating a method for manufacturing a field effect transistor for ESD protection according to an embodiment of the present invention, and fig. 6a to 6f are schematic cross-sectional views illustrating structures formed at various stages of the method for manufacturing the field effect transistor in fig. 5.
The following embodiments also take the field effect transistor for ESD protection as an example, and refer to fig. 6a to 6f to describe the manufacturing process of the field effect transistor for ESD protection provided by the embodiment of the present invention shown in fig. 5.
Step S110: a P-type well region and an N-type well region connected to each other are formed on a substrate.
In step S110, a P-type well region 202 and an N-type well region 203 in contact with an edge region of the P-type well region 202 are formed by sequentially performing ion implantation on a P-type substrate 201, and a cross section of a structure formed thereby is shown in fig. 6 a.
Step S120: a plurality of field oxide regions are formed on the substrate at intervals.
In step S120, silicon oxide is sequentially grown on the surface of the P-type substrate 201 and silicon nitride is deposited by Low Pressure Chemical Vapor Deposition (LPCVD), and then a plurality of field oxide regions 211 are formed in the corresponding regions by controlling the Chemical reaction through the blocking of the photolithography mask, the field oxide regions sequentially define a source region and a gate region located in the P-type well region and a drain region located in the N-type well region, and the cross-section of the formed structure is as shown in fig. 6 b.
Step S130: and sequentially depositing a gate oxide layer and a polysilicon layer on the gate region on the substrate to form a gate structure.
In step S130, a gate oxide layer 206 and a polysilicon layer 209 are sequentially deposited on the gate terminal region of the P-type substrate 201 to form a gate structure, then the gate oxide layer 206 and the polysilicon layer 209 are sequentially etched to control the width of both sides of the gate structure, so as to define a first implantation region and a second implantation region, and the second implantation region is made to cross the boundary between the N-type well region and the P-type well region under the control of the etching process, and the cross-section of the formed structure is as shown in fig. 6 c.
Step S140: and sequentially performing ion implantation on the source end region and the first implantation region to form a first P-type region and a first N-type region, and sequentially performing ion implantation on the second implantation region and the drain end region to form a second N-type region and a third N-type region.
In step S140, a self-aligned process is performed on the source region and the first implanted region by using the field oxide region 211 and the gate structure to sequentially perform ion implantation to form a first P-type region 204 and a first N-type region 205, and a self-aligned process is performed on the second implanted region and the drain region to sequentially perform ion implantation to form a second N-type region 207 and a third N-type region 208, which form a structure with a cross-section as shown in fig. 6 d.
Step S150: a metal silicide layer is formed on a substrate.
In step S150, a metal silicide (silicide), typically TiSi2 (titanium silicide) film, is formed on the P-type substrate 201 by depositing a polysilicon layer on the surface of the P-type substrate 201, depositing a metal layer (typically Ti, Co or Ni) on the surfaces of the polysilicon layer and the gate structure (polysilicon layer 212) by sputtering, and performing Rapid Thermal Annealing (RTA) to react the polysilicon surface with the deposited metal to form a metal silicide layer 210, where the metal silicide layer 210 is formed on the upper surfaces of the first P-type region 204, the first N-type region 205, the gate structure, the second N-type region 207 and the third N-type region 208, and the cross-section of the formed structure is shown in fig. 6 e.
Step S160: the cathode and the anode which form the field effect transistor are led out.
In step S160, the metal silicide layer 210 on the first P-type region 204, the first N-type region 205 and the gate structure is electrically connected to be led out as the cathode of the fet, and the metal silicide layer 210 on the third N-type region 208 is led out as the anode of the fet, and the cross-section of the resulting structure is shown in fig. 6 f.
And the anode of the field effect transistor is led out as an electrostatic inlet end, and the cathode is an earth end.
In summary, in the method for manufacturing a field effect transistor for electrostatic protection according to the embodiments of the present invention, a P-type well region 202 and an N-type well region 203 connected to the P-type well region 202 are sequentially formed on a P-type substrate 201, a plurality of field oxide regions 211 and gate structures are disposed on a surface of the P-type substrate 201 at intervals, and ion implantation is performed through a self-aligned implantation process to sequentially form a first P-type region 204 and a first N-type region 205 located in the P-type well region 202, a second N-type region 207 and a third N-type region 208 located in the N-type well region 203, and then metal silicide layers 210 distributed on the first P-type region 204, the first N-type region 205 and the gate structures are electrically connected to be led out as a cathode of the field effect transistor to be formed, and the metal silicide layer 210 located on the third N-type region 208 is led out as an anode of the field effect transistor to be formed, compared with the prior art, the field effect transistor 200 for electrostatic protection is formed, the drain structure of the field effect transistor 200 is newly adjusted, a metal silicide barrier layer mask is omitted, the manufacturing cost is saved, the forming width of the drain region of the device is not limited, the size of the formed device can be reduced, and the same ESD current discharge capacity can be achieved.
In addition, the Local Oxidation of Silicon (LOCOS) process is taken as an example in this embodiment, but a part or all of the steps in the manufacturing method provided in the above embodiment may also be applied to the manufacturing process of the field effect transistor device in which the field oxide region is formed by other processes, such as a Shallow Trench Isolation (STI) process, and is not limited herein. Compared with the manufacturing method in the prior art, the manufacturing method aims to change the ballast resistor formed by removing part of metal silicide through the metal silicide barrier layer into the N-well resistor, saves the mask plate, reduces the production cost, does not need to limit the forming width of the drain end area of the device, can reduce the size of the formed device, and can achieve the same ESD current discharge capacity.
Although the embodiments have been described and illustrated separately, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and reference may be made to one of the embodiments without explicit recitation to another embodiment.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims (10)

1. A transistor for electrostatic protection, comprising:
the device comprises a P-type well region and an N-type well region which are positioned in a substrate, wherein the P-type well region is connected with the N-type well region;
the first P-type region, the first N-type region and the grid structure are sequentially arranged on the P-type well region at intervals, and the grid structure comprises a grid oxide layer and a polycrystalline silicon layer which are sequentially stacked on the substrate;
the second N-type region and the third N-type region are sequentially arranged on the N-type well region at intervals, the second N-type region spans the junction of the N-type well region and the P-type well region, and the first N-type region and the second N-type region are positioned on two sides of the gate structure;
and the metal silicide layer is positioned on the substrate and distributed on the upper surfaces of the first P-type region, the first N-type region, the grid structure, the second N-type region and the third N-type region.
2. The transistor of claim 1, further comprising:
and the field oxide regions are distributed on two sides of the first P type region and the third N type region and separate the first P type region from the first N type region and the second N type region from the third N type region.
3. The transistor of claim 1, wherein metal silicide layers located on the first P-type region, first N-type region, and gate structure are electrically connected together and serve as a cathode of the transistor;
the metal silicide layer on the third N-type region is led out to be used as an anode of the transistor,
and the anode is an electrostatic inlet end, and the cathode is an earth end.
4. The transistor of claim 3, wherein a leakage path for electrostatic current is provided from the anode to the second N-type well region via the third N-type region.
5. The transistor of claim 1, wherein the substrate is a P-type substrate.
6. The transistor of claim 1 wherein the transistor is a field effect transistor.
7. A method of fabricating a transistor for electrostatic protection, comprising:
sequentially performing ion implantation on a substrate to form a P-type well region and an N-type well region, wherein the formed P-type well region is connected with the N-type well region;
forming a plurality of field oxide regions arranged at intervals on the substrate, wherein the field oxide regions sequentially define a source end region and a gate end region which are positioned in the P-type well region, and a drain end region which is positioned in the N-type well region:
sequentially depositing a gate oxide layer and a polysilicon layer on the gate region on the substrate to form a gate structure, etching two sides of the gate structure to define a first injection region and a second injection region, and enabling the second injection region to cross the junction of the N-type well region and the P-type well region;
sequentially performing ion implantation on the source end region and the first implantation region to form a first P-type region and a first N-type region;
sequentially performing ion implantation on the second implantation region and the drain end region to form a second N-type region and a third N-type region;
and forming a metal silicide layer on the substrate, wherein the formed metal silicide layer is distributed on the upper surfaces of the first P-type region, the first N-type region, the gate structure, the second N-type region and the third N-type region.
8. The manufacturing method according to claim 7, further comprising, after forming a metal silicide layer on the substrate:
electrically connecting and leading out the metal silicide layers positioned on the first P-type region, the first N-type region and the grid structure to be used as a cathode of the transistor;
and leading out the metal silicide layer positioned on the third N-type region to be used as an anode of the transistor.
9. The manufacturing method according to claim 7, wherein the transistor formed is a field effect transistor.
10. The method of manufacturing of claim 7, wherein the method of manufacturing forms a bleed path for electrostatic current from the anode through the third N-type region from the N-type well region to the second N-type well region.
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