CN112002674A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN112002674A CN112002674A CN202011176040.3A CN202011176040A CN112002674A CN 112002674 A CN112002674 A CN 112002674A CN 202011176040 A CN202011176040 A CN 202011176040A CN 112002674 A CN112002674 A CN 112002674A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000005468 ion implantation Methods 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims description 23
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 30
- 230000000903 blocking effect Effects 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 description 84
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 229920005591 polysilicon Polymers 0.000 description 14
- 239000000463 material Substances 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
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- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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Abstract
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate; the semiconductor substrate at least comprises a medium voltage area, and the medium voltage area comprises a first medium voltage area and a second medium voltage area; forming a gate structure on the first middle voltage region and the second middle voltage region; forming side wall structures on two sides of the grid structure; forming a photoresist layer on the semiconductor substrate, wherein the photoresist layer comprises at least one opening, and the opening exposes the first middle pressure region or the second middle pressure region; and carrying out ion doping to form a source electrode and a drain electrode, thinning the photoresist layer, and forming a first light doped region in the first intermediate pressure region or the second intermediate pressure region in an inclined ion implantation mode. The manufacturing method of the semiconductor device can improve the blocking effect of the light resistance on the ion implantation, improve the performance of the device, save the cost and simplify the process.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a method for manufacturing a semiconductor device.
Background
In a driver integrated circuit, transistors having different withstand voltage capabilities are generally formed over the same substrate, and for example, a medium-voltage transistor and a low-voltage transistor are formed over the same substrate. Either the medium voltage transistor or the low voltage transistor is formed first on a substrate, and the other is formed on the same substrate. When a medium voltage transistor or a low voltage transistor is formed by separate processes, efficiency and cost are high due to a large number of manufacturing processes.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a method for manufacturing a semiconductor device to simplify the manufacturing process of the semiconductor device.
To achieve the above and other objects, the present invention provides a method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate; the semiconductor substrate at least comprises a medium voltage area, wherein the medium voltage area comprises a first medium voltage area and a second medium voltage area, and the first medium voltage area and the second medium voltage area are separated by an isolation structure;
forming a gate structure on the first middle voltage region and the second middle voltage region;
forming side wall structures on two sides of the grid structure;
forming a photoresist layer on the semiconductor substrate, wherein the photoresist layer comprises at least one opening, and the opening exposes the first middle pressure region or the second middle pressure region, wherein the width of the opening is a first width, and the thickness of the opening is a first thickness;
performing an ion doping step to form a source and a drain in the first middle voltage region or the second middle voltage region, the source and the drain being located at two sides of the gate structure;
thinning the photoresist layer to change the width of the opening to a second width and the thickness of the opening to a second thickness, wherein the first width is smaller than the second width, and the first thickness is larger than the second thickness;
and forming a first light doping region in the first intermediate voltage region or the second intermediate voltage region in an inclined ion implantation mode, wherein the first light doping region is positioned on two sides of the grid structure and is respectively contacted with the source electrode and the drain electrode.
Further, the semiconductor substrate further includes a low-voltage region separated from the medium-voltage region by the isolation structure, the low-voltage region including a first low-voltage region and a second low-voltage region separated by the isolation structure.
Further, after forming the gate structure on the first low-voltage region and the second low-voltage region and before forming the sidewall structures on the first low-voltage region and the second low-voltage region, forming a second lightly doped region in the first low-voltage region and the second low-voltage region, and forming at least a first pocket region and a second pocket region in the first low-voltage region and the second low-voltage region.
Further, the second pocket region is located outside the second lightly doped region and is in contact with the second lightly doped region; the first pocket region is in contact with the second pocket region and the second lightly doped region respectively.
Further, when the photoresist layer simultaneously exposes the first middle voltage region and the first low voltage region, the ion doping step is performed to form the source electrode and the drain electrode in the first middle voltage region and to form the source electrode and the drain electrode in the first low voltage region.
Further, when the photoresist layer simultaneously exposes the second middle voltage region and the second low voltage region, the ion doping step is performed to form the source electrode and the drain electrode in the second middle voltage region and to form the source electrode and the drain electrode in the second low voltage region.
Further, performing tilted ion implantation on the first low-voltage region while performing tilted ion implantation on the first medium-voltage region; performing angled ion implantation on the second low-voltage region while performing angled ion implantation on the second medium-voltage region.
Further, the angle of the inclined ion implantation is 25-50 degrees.
Further, the ion doping type of the first lightly doped region located in the first intermediate voltage region is different from the ion doping type of the first lightly doped region located in the second intermediate voltage region.
Further, the light resistance layer is thinned through oxygen plasma.
In summary, the present invention provides a method for manufacturing a semiconductor device, in which a low-voltage region is formed and then a medium-voltage region is formed. When forming the middle pressure area, firstly forming a grid structure and a side wall structure on the first middle pressure area and the second middle pressure area, then exposing the first middle pressure area or the second middle pressure area through the opening of the photoresist layer, then forming a source electrode and a drain electrode in the first middle pressure area or the second middle pressure area respectively, then thinning the photoresist layer to enlarge the width of the opening and reduce the thickness of the photoresist layer, and then performing inclined ion implantation to form a first light doped area in the first middle pressure area or the second middle pressure area. The width of the opening is increased, and the thickness of the photoresist layer is reduced, so that the angle of the inclined ion implantation is increased, and a first light doped region can be formed in a first intermediate pressure region or a second intermediate pressure region after the side wall structure is formed, so that the blocking effect of the photoresist layer on the ion implantation can be improved, and the performance of a device is improved. Meanwhile, the invention does not need to remove the photoresistive layer after forming the source electrode and the drain electrode, thereby omitting a photomask process, simplifying the process and reducing the cost.
Drawings
FIG. 1: the present embodiment provides a flowchart of a method for manufacturing a semiconductor device.
FIG. 2: the structure of the semiconductor substrate is schematically shown.
FIG. 3: and the structure of the grid oxide layer and the polycrystalline silicon layer on the semiconductor substrate is shown schematically.
FIG. 4: the structure of the gate structure on the semiconductor substrate is shown schematically.
FIG. 5: and a second lightly doped region is formed in the first well region of the low-voltage region, and the first pocket region and the second pocket region are in a structural schematic diagram on the semiconductor substrate.
FIG. 6: and a second lightly doped region is formed in the second well region of the low-voltage region, and the first pocket region and the second pocket region are in a structural schematic diagram on the semiconductor substrate.
FIG. 7: and the structure of the side wall dielectric layer on the semiconductor substrate.
FIG. 8: the structure of the side wall structure on the semiconductor substrate.
FIG. 9: the first well region forms a structure of a source and a drain on the semiconductor substrate.
FIG. 10: and the structure diagram on the semiconductor substrate after the photoresist layer is thinned.
FIG. 11: the structure of the first lightly doped region on the semiconductor substrate.
FIG. 12: the second well region forms a structure of a source and a drain on the semiconductor substrate.
FIG. 13: and the structure diagram on the semiconductor substrate after the photoresist layer is thinned.
FIG. 14: the present embodiment proposes a structure diagram of a semiconductor device.
Description of the symbols
101: a semiconductor substrate; 102: a shallow trench isolation structure; 103: a first well region; 104: a second well region; 105: a gate oxide layer; 105 a: a gate dielectric layer; 106: a polysilicon layer; 106 a: a gate electrode layer; 107: a gate structure; 108: a photoresist layer; 1081: a first opening; 1082: a second opening; 109: a second lightly doped region; 110: a first pocket region; 111: a second pocket region; 112: a side wall dielectric layer; 112 a: a side wall structure; 113: a source electrode; 114: drain electrode: 115 a first lightly doped region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present embodiment proposes a method for manufacturing a semiconductor device, including:
s1: providing a semiconductor substrate, isolating a first well region and a second well region which are arranged at intervals in the semiconductor substrate through a shallow trench isolation structure, and defining a medium-voltage region and a low-voltage region;
s2: forming a gate structure over the first well region and the second well region;
s3: forming a second lightly doped region, a first pocket region and a second pocket region within the low-voltage region;
s4: forming a side wall structure on the first well region and the second well region;
s5: forming a photoresist layer on the middle-voltage region and the low-voltage region to form a source electrode and a drain electrode in the middle-voltage region and the low-voltage region;
s6: and thinning the photoresist layer, and forming a first light doped region in the medium-voltage region.
As shown in fig. 2, in step S1, a semiconductor substrate 101 is first provided, a plurality of shallow trench isolation structures 102 are then formed in the semiconductor substrate 101, the shallow trench isolation structures 102 separate a plurality of active regions arranged at intervals in the semiconductor substrate 101, and then the active regions are ion-doped to form a plurality of first well regions 103 and a plurality of second well regions 104 in the semiconductor substrate 101.
As shown in fig. 2, in the present embodiment, the material of the semiconductor substrate 101 may include, but is not limited to, a single crystal or polycrystalline semiconductor material, and the semiconductor substrate 101 may also include an intrinsic single crystal silicon substrate or a doped silicon substrate; the semiconductor substrate 101 includes a substrate of a first doping type, which may be a P-type substrate or an N-type substrate, and in this embodiment, only the first doping type is the P-type substrate, that is, in this embodiment, the semiconductor substrate 101 only uses the P-type substrate as an example.
As shown in fig. 2, in the present embodiment, the shallow trench isolation structure 102 may be formed by forming a trench (not shown) in the semiconductor substrate 101 and then filling the trench with an isolation material layer. The material of the shallow trench isolation structure 102 may include silicon nitride, silicon oxide, silicon oxynitride, or the like. In this embodiment, the material of the shallow trench isolation structure 102 includes silicon oxide. The shape of the longitudinal section of the shallow trench isolation structure 102 may be set according to actual needs, and the shape of the longitudinal section of the shallow trench isolation structure 102 including an inverted trapezoid is taken as an example in fig. 2. Of course, in some embodiments, the longitudinal section of the shallow trench isolation structure 11 may also be U-shaped, and so on.
As shown in fig. 2, in the present embodiment, after the active region is formed by the shallow trench isolation structure 102, different types of ion doping are then performed on the active region to form the first well region 103 and the second well region 104. In the embodiment, the first well 103 is formed by doping active regions with P-type ions, for example, and the first well 103 is a P-type well, for example, that is, a NMOS transistor is formed. The second well region 104 is formed by doping an active region with N-type ions, for example, and the second well region 104 is an N-type well region, for example, which is used to form a PMOS transistor. In the present embodiment, the first well region 103 and the second well region 104 on the left side are defined as medium-voltage regions, and the first well region 103 and the second well region 104 on the right side are defined as low-voltage regions; i.e., the medium voltage region and the low voltage region are separated by the shallow trench isolation structure 102. After the middle-voltage region and the low-voltage region are defined, the first well region 103 in the middle-voltage region can be further defined as a first middle-voltage region, and the second well region 104 in the middle-voltage region can be further defined as a second middle-voltage region; the first well region 103 within the low-voltage region may also be defined as a first low-voltage region and the second well region 104 within the low-voltage region may also be defined as a second low-voltage region. Of course, in some embodiments, a high voltage region may also be defined within the semiconductor substrate 101, i.e., the semiconductor substrate 101 includes a high voltage region, a medium voltage region, and a low voltage region.
The high-voltage region may be referred to as a high-voltage transistor region, the medium-voltage region may be referred to as a medium-voltage transistor region, and the low-voltage region may be referred to as a low-voltage transistor region.
It should be noted that the first well regions 103 and the second well regions 104 may be arranged in parallel at intervals, or may be arranged arbitrarily according to actual needs.
As shown in fig. 3, in step S2, a gate oxide layer 105 and a polysilicon layer 106 are first formed on the semiconductor substrate 101, the gate oxide layer 105 covers the first well region 103 and the second well region 104, and the polysilicon layer 106 covers the gate oxide layer 105. The material of the gate oxide layer 105 may include, but is not limited to, silicon oxide or silicon oxynitride. The gate oxide layer 105 may be formed by a furnace oxidation process, a chemical vapor deposition process, a spin-on-glass process, or other suitable methods. The thickness of the gate oxide layer 105 may be between 3 nm and 10nm, and the thickness of the gate oxide layer 105 may also be set according to actual requirements. In this embodiment, the polysilicon layer 106 may be a polysilicon layer of a second doping type, that is, the doping type of the polysilicon layer 106 is different from that of the semiconductor substrate 101; the second doping type may be a P type or an N type, and when the first doping type is a P type, the second doping type is an N type, and when the first doping type is an N type, the second doping type is a P type. The thickness of the polysilicon layer 106 may be between 300 nm and 400nm, and the thickness of the polysilicon layer 106 may be set according to actual requirements.
As shown in fig. 3 to 4, after the polysilicon layer 106 is formed, a photoresist is first formed on the polysilicon layer 106, and then the photoresist is exposed and developed; exposing the polysilicon layer 106 to be etched, and then etching the polysilicon layer 106 by a dry etching process, a wet etching process or a combination of the dry etching process and the wet etching process; the polysilicon layer 106 is sequentially anisotropically etched, for example, by a dry etching process, to form a gate electrode layer 106 a. In this embodiment, the gate oxide layer 105 may serve as an etch stop layer for the polysilicon layer 106. After the gate electrode layer 106a is formed, a new photoresist needs to be formed, and then the photoresist is exposed and developed; exposing the gate oxide layer 105 to be etched, and then etching the gate oxide layer 105 by a dry etching process, a wet etching process or a combination of the dry etching process and the wet etching process; the gate oxide layer 105 is sequentially anisotropically etched, for example, using a dry etching process, to form a gate dielectric layer 105 a.
As shown in fig. 4, in the present embodiment, a gate dielectric layer 105a is located over the first well region 103 and the second well region 104, a gate electrode layer 106a is located over the first well region 103 and the second well region 104, and the gate electrode layer 106a is located over the gate dielectric layer 105 a. The width of gate dielectric layer 105a is equal to the width of gate electrode layer 106a, and the thickness of gate electrode layer 106a is greater than the thickness of gate dielectric layer 105 a. The present embodiment defines the gate dielectric layer 105a and the gate electrode layer 106a as a gate structure 107. As can be seen from fig. 4, the gate structures 107 are located on the first well region 103 and the second well region 104, that is, the gate structures 107 may be arranged in parallel at intervals.
As shown in fig. 5, in step S3, after the gate structure 107 is formed, a photoresist layer 108 is first formed on the semiconductor substrate 101, and then the photoresist layer 108 is exposed and developed; to form at least one opening that exposes the first well region 103 in the low-voltage region and also exposes the gate structure 107 located over the first well region 103. Then, ion doping is performed into the first well 103 according to the opening to form a second lightly doped region 109 in the first well 103, the second lightly doped region 109 is located at two sides of the gate structure 107, an ion doping type of the second lightly doped region 109 is different from an ion doping type of the first well 103, and an ion doping type of the second lightly doped region 109 is, for example, an N type, such as a P type.
As shown in fig. 5, in the present embodiment, the second lightly doped region 109 is located at two sides of the gate structure 107 and is adjacent to the gate structure 107. After the second lightly doped region 109 is formed, ion doping is performed again to form a first pocket region 110 and a second pocket region 111 in the first well region 103 of the low voltage region. The ion doping type of the first pocket region 110 and the second pocket region 111 is different from that of the second lightly doped region 109, the doping ions of the first pocket region 110 and the second pocket region 111 are, for example, B, and the ion doping type of the first pocket region 110 and the second pocket region 111 may be the same as that of the first well region 103. In the present embodiment, the first pocket regions 110 are located at two sides of the gate structure 107, the first pocket regions 110 are in contact with the second lightly doped region 109, and the first pocket regions 110 may be located at a middle position of the second lightly doped region 109. The second pocket regions 111 are located at two sides of the gate structure 107, and the second pocket regions 111 are located at the outer sides of the second lightly doped regions 109. The upper half of the second pocket region 111 is located below the gate structure 107 and contacts the second lightly doped region 109 and the gate structure 107. The lower portion of the second pocket region 111 is in contact with the second lightly doped region 109 and the first pocket region 110. In the present embodiment, the first pocket region 110 may function to prevent the second lightly doped region 109 from being connected, that is, to prevent leakage. In this embodiment, for example, the second lightly doped region 109, the first pocket region 110 and the second pocket region 111 are formed by oblique ion implantation. The arrows in fig. 5 indicate the direction of ion implantation.
As shown in fig. 5-6, in the present embodiment, after forming the second lightly doped region 109, the first pocket region 110 and the second pocket region 111 in the first well 103 of the low-voltage region, after removing the photoresist layer 108, another photoresist layer 108 is formed on the semiconductor substrate 101, and then the photoresist layer 108 is exposed and developed; to form at least one opening that exposes the second well region 104 in the low-voltage region and also exposes the gate structure 107 located over the second well region 104. Then, ion doping is performed into the second well region 104 according to the opening to form a second lightly doped region 109 in the second well region 104, the second lightly doped region 109 is located at two sides of the gate structure 107, an ion doping type of the second lightly doped region 109 is different from an ion doping type of the second well region 104, and an ion doping type of the second lightly doped region 109 is, for example, a P type, such as B. It should be noted that the ion doping type of the second lightly doped region 109 located in the first well 103 is different from the ion doping type of the second lightly doped region 109 located in the second well 104. The arrows in fig. 6 indicate the direction of ion implantation.
As shown in fig. 6, in the present embodiment, the second lightly doped region 109 is located at two sides of the gate structure 107 and is adjacent to the gate structure 107. After the second lightly doped region 109 is formed, ion doping is performed again to form a first pocket region 110 and a second pocket region 111 within the second well region 104 within the low-voltage region. The ion doping type of the first pocket region 110 and the second pocket region 111 is different from that of the second lightly doped region 109, the doping ions of the first pocket region 110 and the second pocket region 111 are P, for example, and the ion doping type of the first pocket region 110 and the second pocket region 111 may be the same as that of the second well region 104. In the present embodiment, the first pocket regions 110 are located at two sides of the gate structure 107, the first pocket regions 110 are in contact with the second lightly doped region 109, and the first pocket regions 110 may be located at a middle position of the second lightly doped region 109. The second pocket regions 111 are located at two sides of the gate structure 107, and the second pocket regions 111 are located at the outer sides of the second lightly doped regions 109. The upper half of the second pocket region 111 is located below the gate structure 107 and contacts the second lightly doped region 109 and the gate structure 107. The lower portion of the second pocket region 111 is in contact with the second lightly doped region 109 and the first pocket region 110. The first pocket region 110 and the second pocket region 111 are in contact. In the present embodiment, the first pocket region 110 may function to prevent the second lightly doped region 109 from being connected, that is, to prevent leakage. In this embodiment, for example, the second lightly doped region 109, the first pocket region 110 and the second pocket region 111 are formed by oblique ion implantation.
As shown in fig. 6, in the present embodiment, the ion doping type of the second lightly doped region 109 in the first well 103 in the low-voltage region is, for example, N-type, the ion doping type of the first pocket region 110 in the first well 103 is, for example, P-type, and the ion doping type of the second pocket region 111 is, for example, P-type. The ion doping type of the second lightly doped region 109 in the second well region 104 in the low-voltage region is, for example, P-type, and the ion doping type of the first pocket region 110 and the second pocket region 111 in the second well region 104 is, for example, N-type. After the second lightly doped region 109, the first pocket region 110 and the second pocket region 111 are formed in the first well region 103 and the second well region 104, the low voltage region is substantially formed. The first well 103 is, for example, an N-type low voltage transistor region, and the second well 104 is, for example, a P-type low voltage transistor region.
As shown in fig. 7-8, in step S4, a sidewall dielectric layer 112 is first formed on the semiconductor substrate 101, and the sidewall dielectric layer 112 covers the gate structure 107. The material of the sidewall dielectric layer 112 may include, but is not limited to, at least one of silicon oxide and silicon nitride; the thickness of the sidewall dielectric layer 112 may be set according to actual needs, and in this embodiment, the thickness of the sidewall dielectric layer 112 may be between 20nm and 30 nm. After the sidewall dielectric layers 112 are formed, a photolithography-etching process may be used to remove the sidewall dielectric layers 112 located between the gate structures 107 and a portion of the sidewall dielectric layers 112 located at the top of the gate structures 107, and the sidewall dielectric layers 112 located at two sides of the gate structures 107 are remained, so that sidewall structures 112a are formed at two sides of the gate structures 107. For example, the sidewall dielectric layer 112 is anisotropically etched using a dry etching process, and the vertical downward arrow in fig. 7 indicates the direction of plasma during the dry etching process.
As shown in fig. 8, in the present embodiment, the sidewall structures 112a are located at two sides of the gate structure 107. The height of the sidewall structure 112a is equal to the height of the gate structure 107, and the width of the sidewall structure 112a gradually increases from the top to the bottom of the gate structure 107. The sidewall structures 112a are used for protecting the gate structure 107. In this embodiment, the sidewall structure 112a is arc-shaped, and in some embodiments, the sidewall structure 112a may also be triangular or L-shaped. When the sidewall structure 112a is located on the low-voltage region, the sidewall structure 112a is also located on the second lightly doped region 109.
As shown in fig. 9, in step S5, a photoresist layer 108 is first formed on the semiconductor substrate 101, and then the photoresist layer 108 is exposed and developed; at least a first opening 1081 and a second opening 1082 are formed. The first opening 1081 is used for exposing the first well region 103 of the medium voltage region, and the second opening 1082 is used for exposing the first well region 103 of the low voltage region. Then, ion doping is performed into the first well 103 according to the first opening 1081 and the second opening 1082 to form the source 113 and the drain 114. In the present embodiment, the ion doping type of the source 113 and the drain 114 in the first well 103 in the high-voltage region is the same as the ion doping type of the source 113 and the drain 114 in the first well 103 in the low-voltage region, such as N-type. The vertical arrows in fig. 9 indicate the direction of ion doping.
As shown in fig. 9, in the present embodiment, the source 113 and the drain 114 are located at two sides of the gate structure 107, and both the source 113 and the drain 114 are adjacent to the sidewall structure 112 a. The source 113 and drain 114 are also in contact with the shallow trench isolation structure 102. As can be seen from fig. 9, when the source 113 and the drain 114 are located in the low voltage region, the source 113 and the drain 114 are in contact with the second lightly doped region 109, respectively. The ion doping type of the source 113 and the drain 114 is the same as that of the second lightly doped region 109, and the ion doping energy of the source 113 and the drain 114 may be greater than that of the second doped region 109.
As shown in fig. 9-10, in step S6, after the source electrode 113 and the drain electrode 114 are formed, the photoresist layer 108 is thinned without removing the photoresist layer 108, so that one mask process can be saved. In this embodiment, the photoresist layer 108 is thinned by, for example, oxygen plasma. As shown in fig. 9, before the thinning process, the width of the first opening 1081 is a first width, and the thickness of the photoresist layer 108 is a first thickness, after the thinning process, the width of the first opening 1081 is changed to a second width, the second width is greater than the first width, and the thickness of the photoresist layer 108 is changed to a second thickness, which is smaller than the first thickness. Similarly, the width of the second opening 1082 becomes larger. Since the width of the first opening 1081 is increased and the thickness of the photoresist layer 108 is decreased, the angle of the ion tilt implantation can be increased, so as to improve the problem of smaller angle of the ion tilt implantation caused by the thickness of the photoresist layer 108 and the width of the first opening 1081, i.e. improve the blocking effect of the photoresist layer 108 on the ion implantation.
As shown in fig. 11, after the photoresist layer 108 is thinned, ions are implanted into the first well 103 of the middle voltage region through the first opening 1081 to form a first lightly doped region 115, and the first lightly doped region 115 is located at two sides of the gate structure 107. The first lightly doped region 115 is located under the sidewall structure 112a, and the first lightly doped region 115 is in contact with the source 113 and the drain 114. In the present embodiment, the ion doping type of the first lightly doped region 115 located in the first well region 103 of the middle voltage region is the same as the ion doping type of the source 113 and the drain 114 located in the first well region 103 of the low voltage region. In the present embodiment, since the two sides of the gate structure 107 include the sidewall structures 112a, the first lightly doped region 115 is formed by using an oblique ion implantation. Meanwhile, since the width of the first opening 1081 is increased and the thickness of the photoresist layer 108 is decreased, the angle of the ion tilt implantation is increased, and thus a portion of the first lightly doped region 115 may be located below the sidewall structure 112 a. In this embodiment, the angle of the angled ion implantation may be between 25 ° and 50 °, such as between 30 ° and 40 °. Similarly, ions are implanted into the first well 103 in the low voltage region through the second opening 1082.
As shown in fig. 11, in the present embodiment, since the photoresist layer 108 includes the first opening 1081 and the second opening 1082, that is, the first well 103 of the middle voltage region and the first well 103 of the low voltage region are exposed simultaneously, when ions are doped in the first well 103 of the middle voltage region, ions are also doped in the first well 103 of the low voltage region. Since the first well 103 in the low-voltage region includes the second pocket region 111, the doped ions can be prevented from penetrating through the second lightly doped region 109, thereby avoiding the leak problem.
As shown in fig. 10 to 11, in the present embodiment, after the photoresist layer 108 is formed, the source electrode 113 and the drain electrode 114 are first fabricated, then the photoresist layer 108 is thinned, and then the first lightly doped region 115 is formed. Therefore, the present invention can save one photomask process.
As shown in fig. 12, after the first lightly doped region 115 is formed in the first well 103 of the middle voltage region, the photoresist layer 108 is removed, another photoresist layer 108 is formed on the semiconductor substrate 101, and then the photoresist layer 108 is exposed and developed; thereby forming at least a first opening 1081 and a second opening 1082. The first opening 1081 exposes the second well region 104 of the middle voltage region, and the second opening 1082 exposes the second well region 104 of the low voltage region. Then, ion doping is performed into the second well region 104 according to the first opening 1081 and the second opening 1082 to form the source 113 and the drain 114. In the present embodiment, the ion doping type of the source 113 and the drain 114 in the second well region 104 in the high-voltage region is the same as the ion doping type of the source 113 and the drain 114 in the second well region 104 in the low-voltage region, such as P-type. The vertical arrows in fig. 12 indicate the direction of ion doping.
As shown in fig. 12, in the present embodiment, the source 113 and the drain 114 are located at two sides of the gate structure 107, and both the source 113 and the drain 114 are adjacent to the sidewall structure 112 a. The source 113 and drain 114 are also in contact with the shallow trench isolation structure 102. It should be noted that the source 113 and the drain 114 in the low-voltage region are both in contact with the second lightly doped region 109, and the ion doping type of the source 113 and the drain 114 is the same as that of the second lightly doped region 109.
As shown in fig. 12-13, in the present embodiment, after the source electrode 113 and the drain electrode 114 are formed, the photoresist layer 108 is thinned without removing the photoresist layer 108, so that one photo-masking process can be saved. In this embodiment, the photoresist layer 108 is thinned by, for example, oxygen plasma. As shown in fig. 12, before the thinning process, the width of the first opening 1081 is a first width, and the thickness of the photoresist layer 108 is a first thickness, after the thinning process, the width of the first opening 1081 is changed to a second width, the second width is greater than the first width, and the thickness of the photoresist layer 108 is changed to a second thickness, which is smaller than the first thickness. Similarly, the width of the second opening 1082 becomes larger. Since the width of the first opening 1081 is increased and the thickness of the photoresist layer 108 is decreased, the angle of the ion tilt implantation can be increased, so as to improve the problem of smaller angle of the ion tilt implantation caused by the thickness of the photoresist layer 108 and the width of the first opening 1081, i.e. improve the blocking effect of the photoresist layer 108 on the ion implantation.
As shown in fig. 13, after the photoresist layer 108 is thinned, ions are implanted into the second well region 104 of the middle voltage region through the first opening 1081 to form the first lightly doped region 115, and the first lightly doped region 115 is located at two sides of the gate structure 107. The first lightly doped region 115 is located below the sidewall structure 112a, and the first lightly doped region 115 is in contact with the source 113 and the drain 114. In the present embodiment, the ion doping type of the first lightly doped region 115 located in the second well region 104 of the middle voltage region is the same as the ion doping type of the source 113 and the drain 114 located in the second well region 104 of the low voltage region. In the present embodiment, since the two sides of the gate structure 107 include the sidewall structures 112a, the first lightly doped region 115 is formed by using an oblique ion implantation. Meanwhile, since the width of the first opening 1081 is increased and the thickness of the photoresist layer 108 is decreased, the angle of the ion tilt implantation is increased, and thus a portion of the first lightly doped region 115 may be located below the sidewall structure 112 a. In this embodiment, the angle of the angled ion implantation may be between 25 ° and 50 °, such as between 30 ° and 40 °, such as between 30 ° or 35 °. Similarly, ions are implanted into the second well region 104 in the low voltage region through the second opening 1082.
As shown in fig. 13, in the present embodiment, since the photoresist layer 108 includes the first opening 1081 and the second opening 1082, that is, the second well region 104 of the middle voltage region and the second well region 104 of the low voltage region are exposed simultaneously, when ions are doped in the second well region 104 of the middle voltage region, ions are also doped in the second well region 104 of the low voltage region. Since the second pocket region 111 is included in the second well region 104 of the low voltage region, the doped ions can be prevented from penetrating through the second lightly doped region 109, thereby avoiding the leak problem. After the first lightly doped region 115 is formed, the photoresist layer 108 is removed, i.e., a middle region and a low-pressure region are formed.
As shown in fig. 12 to 13, in the present embodiment, after forming the photoresist layer 108, the source electrode 113 and the drain electrode 114 are first fabricated, then the photoresist layer 108 is thinned, and then the first lightly doped region 115 is formed in the medium voltage region. Therefore, the present invention can save one photomask process.
As shown in fig. 14, the present embodiment further provides a semiconductor device, which includes a semiconductor substrate 101, the semiconductor substrate 101 includes a plurality of shallow trench isolation structures 102, the shallow trench isolation structures separate a first well region 103 and a second well region 104 arranged at intervals in the semiconductor substrate 101, the first well region 103 and the second well region 104 have different ion doping types, the ion doping type of the first well region 103 is, for example, a P type, and the ion doping type of the second well region 104 can be an N type. In this embodiment, the first well region 103 on the left side can be a first middle voltage region, such as an N-type middle voltage transistor region, and the second well region 104 on the left side can be a second middle voltage region, such as a P-type middle voltage transistor region. The first and second intermediate pressure zones form an intermediate pressure zone. The right first well 103 may be a first low voltage region, such as an N-type low voltage transistor region, and the right second well 104 may be a second low voltage region, such as a P-type low voltage transistor region. The first low-voltage region and the second low-voltage region form a low-voltage region.
As shown in fig. 14, a plurality of gate structures 107 are further included on the semiconductor substrate 101, and the gate structures 107 are respectively located on the first well region 103 and the second well region 104. The gate structure 107 further includes sidewall structures 112a on two sides. The height of the sidewall structure 112a is equal to or less than the height of the gate structure 107, and the sidewall structure 112a may protect the gate structure 107.
As shown in fig. 14, the first middle voltage region includes a source electrode 113 and a drain electrode 114, the source electrode 113 and the drain electrode 114 are located at two sides of the gate structure 107, the first middle voltage region further includes a first lightly doped region 115, the first lightly doped region 115 is located at two sides of the gate structure 107, and the source electrode 113 and the drain electrode 114 are in contact with the first lightly doped region 115. The ion doping type of the source 113 and the drain 114 in the first middle-voltage region is the same as that of the first lightly doped region 115, for example, N-type.
As shown in fig. 14, the second middle voltage region includes a source electrode 113 and a drain electrode 114, the source electrode 113 and the drain electrode 114 are located at two sides of the gate structure 107, the second middle voltage region further includes a first lightly doped region 115, the first lightly doped region 115 is located at two sides of the gate structure 107, and the source electrode 113 and the drain electrode 114 are in contact with the first lightly doped region 115. The ion doping type of the source 113 and the drain 114 in the second middle-voltage region is the same as that of the first lightly doped region 115, for example, P-type. The first and second intermediate voltage regions have the same structure, and are different in ion doping type. In this embodiment, the drain 114 in the first middle voltage region is close to the source 113 in the second middle voltage region.
As shown in fig. 14, the first low-voltage region includes a source 113 and a drain 114, the source 113 and the drain 114 are located at two sides of the gate structure 107, the first low-voltage region further includes a second lightly doped region 109, the second lightly doped region 109 is located at two sides of the gate structure 107, and the source 113 and the drain 114 are in contact with the second lightly doped region 109. The source 113 and drain 114 in the first low-voltage region are doped with ions of the same type as the second lightly doped ion region 109, for example, N-type.
As shown in fig. 14, the first low-voltage region further includes a first pocket region 110 and a second pocket region 111, the first pocket region 110 is located at two sides of the gate structure 107, the second pocket region 111 is located at two sides of the gate structure 107, the first pocket region 110 is located at a middle portion of the second lightly doped region 109, and the second lightly doped region 109 can prevent doped ions from passing through, thereby avoiding a leak problem. The upper half of the second pocket region 111 is located under the gate structure 107 and contacts the gate structure 107. The lower portion of the second pocket region 111 is located at the bottom of the second lightly doped region 109, and the first pocket region 110 and the second pocket region 111 are in contact. The second pocket region 111 is also in contact with the second lightly doped region 109. In the present embodiment, the first low-voltage region needs to be doped with ions tilted twice, and the doped ions can be prevented from passing through the second lightly doped region 109 by the second pocket region 111. In the present embodiment, the first pocket region 110 and the second pocket region 111 have the same ion doping type, but have a different ion doping type from the second lightly doped region 109, such as a P-type.
As shown in fig. 14, the second low-voltage region includes a source 113 and a drain 114, the source 113 and the drain 114 are located at two sides of the gate structure 107, the second low-voltage region further includes a second lightly doped region 109, the second lightly doped region 109 is located at two sides of the gate structure 107, and the source 113 and the drain 114 are in contact with the second lightly doped region 109. The ion doping type of the source 113 and the drain 114 in the second low-voltage region is the same as the ion doping type of the second lightly ion doped region 109, for example, P-type.
As shown in fig. 14, the second low-voltage region further includes a first pocket region 110 and a second pocket region 111, the first pocket region 110 is located at two sides of the gate structure 107, the second pocket region 111 is located at two sides of the gate structure 107, the first pocket region 110 is located at a middle portion of the second lightly doped region 109, and the second lightly doped region 109 can prevent doped ions from passing through, thereby avoiding a leak problem. The upper half of the second pocket region 111 is located under the gate structure 107 and contacts the gate structure 107. The lower portion of the second pocket region 111 is located at the bottom of the second lightly doped region 109. The second pocket region 111 is also in contact with the second lightly doped region 109, and the first pocket region 110 is in contact with the second pocket region 111. In this embodiment, the second low-voltage region needs to be doped with ions tilted twice, and the doped ions can be prevented from passing through the second lightly doped region 109 by the second pocket region 111. In the present embodiment, the first pocket region 110 and the second pocket region 111 have the same ion doping type, but have a different ion doping type from the second lightly doped region 109, such as N type. The first low-voltage region and the second low-voltage region have the same structure, except that the ion doping type is different.
As shown in fig. 14, in the present embodiment, the semiconductor device can be applied to various integrated circuits such as a memory circuit, for example, a random access memory, a dynamic random access memory, a synchronous random access memory, a static random access memory, a read only memory, or the like. The integrated circuit may also be a logic device such as a programmable logic array, an application specific integrated circuit, a combinational logic integrated circuit, a radio frequency circuit, or any other circuit device. The integrated circuit can also be used in, for example, consumer electronic products such as personal computers, portable computers, game machines, cellular phones, personal digital assistants, video cameras, digital cameras, cellular phones, and various other electronic products.
In summary, the present invention provides a method for manufacturing a semiconductor device, in which a low-voltage region is formed and then a medium-voltage region is formed. When forming the middle pressure area, firstly forming a grid structure and a side wall structure on the first middle pressure area and the second middle pressure area, then exposing the first middle pressure area or the second middle pressure area through the opening of the photoresist layer, then forming a source electrode and a drain electrode in the first middle pressure area or the second middle pressure area respectively, then thinning the photoresist layer to enlarge the width of the opening and reduce the thickness of the photoresist layer, and then performing inclined ion implantation to form a first light doped area in the first middle pressure area or the second middle pressure area. The width of the opening is increased, and the thickness of the photoresist layer is reduced, so that the angle of the inclined ion implantation is increased, and a first light doped region can be formed in a first intermediate pressure region or a second intermediate pressure region after the side wall structure is formed, so that the blocking effect of the photoresist layer on the ion implantation can be improved, and the performance of a device is improved. Meanwhile, the invention does not need to remove the photoresistive layer after forming the source electrode and the drain electrode, thereby omitting a photomask process and simplifying the process.
Reference throughout this specification to "one embodiment", "an embodiment", or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, respective appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It is to be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the present invention.
It will also be appreciated that one or more of the elements shown in the figures can also be implemented in a more separated or integrated manner, or even removed for inoperability in some circumstances or provided for usefulness in accordance with a particular application.
Additionally, any reference arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise expressly specified. Further, as used herein, the term "or" is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.
As used in the description herein and throughout the claims that follow, "a", "an", and "the" include plural references unless otherwise indicated. Also, as used in the description herein and throughout the claims that follow, unless otherwise indicated, the meaning of "in …" includes "in …" and "on … (on)".
The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The systems and methods have been described herein in general terms as the details aid in understanding the invention. Furthermore, various specific details have been given to provide a general understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Thus, although the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Thus, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate; the semiconductor substrate at least comprises a medium voltage area, wherein the medium voltage area comprises a first medium voltage area and a second medium voltage area, and the first medium voltage area and the second medium voltage area are separated by an isolation structure;
forming a gate structure on the first middle voltage region and the second middle voltage region;
forming side wall structures on two sides of the grid structure;
forming a photoresist layer on the semiconductor substrate, wherein the photoresist layer comprises at least one opening, and the opening exposes the first middle pressure region or the second middle pressure region, wherein the width of the opening is a first width, and the thickness of the opening is a first thickness;
performing an ion doping step to form a source and a drain in the first middle voltage region or the second middle voltage region, the source and the drain being located at two sides of the gate structure;
thinning the photoresist layer to change the width of the opening to a second width and the thickness of the opening to a second thickness, wherein the first width is smaller than the second width, and the first thickness is larger than the second thickness;
and forming a first light doping region in the first intermediate voltage region or the second intermediate voltage region in an inclined ion implantation mode, wherein the first light doping region is positioned on two sides of the grid structure and is respectively contacted with the source electrode and the drain electrode.
2. The method of manufacturing the semiconductor device according to claim 1, wherein the semiconductor substrate further comprises a low-voltage region, the low-voltage region and the medium-voltage region being separated by the isolation structure, the low-voltage region comprising a first low-voltage region and a second low-voltage region, the first low-voltage region and the second low-voltage region being separated by the isolation structure.
3. The method of claim 2, further comprising forming a second lightly doped region in the first and second low-voltage regions and forming at least first and second pocket regions in the first and second low-voltage regions after forming a gate structure over the first and second low-voltage regions and before forming sidewall structures over the first and second low-voltage regions.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the second pocket region is located outside the second lightly doped region and is in contact with the second lightly doped region; the first pocket region is in contact with the second pocket region and the second lightly doped region respectively.
5. The method of claim 2, wherein said ion doping step is performed while said photoresist layer simultaneously exposes said first middle voltage region and said first low voltage region to form said source and said drain in said first middle voltage region and to form said source and said drain in said first low voltage region.
6. The method of claim 2, wherein said ion doping step is performed while said photoresist layer simultaneously exposes said second middle voltage region and said second low voltage region to form said source and said drain in said second middle voltage region and to form said source and said drain in said second low voltage region.
7. The manufacturing method of a semiconductor device according to claim 2, wherein the first low-voltage region is subjected to oblique ion implantation simultaneously with the oblique ion implantation of the first medium-voltage region; performing angled ion implantation on the second low-voltage region while performing angled ion implantation on the second medium-voltage region.
8. The method for manufacturing a semiconductor device according to claim 1, wherein an angle of the angled ion implantation is 25 ° to 50 °.
9. The method for manufacturing a semiconductor device according to claim 1, wherein an ion doping type of the first lightly doped region located in the first intermediate voltage region is different from an ion doping type of the first lightly doped region located in the second intermediate voltage region.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the light-blocking layer is subjected to thinning treatment by oxygen plasma.
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| CN113506739A (en) * | 2021-06-09 | 2021-10-15 | 上海华虹宏力半导体制造有限公司 | Core MOS device and process method |
| CN114496925A (en) * | 2022-04-01 | 2022-05-13 | 晶芯成(北京)科技有限公司 | Semiconductor structure and preparation method thereof |
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| CN101863447B (en) * | 2009-04-15 | 2011-10-05 | 中国科学院半导体研究所 | Method for manufacturing sloped sidewall silicon dioxide structure by adopting photoetching and dry etching |
| CN104051344B (en) * | 2013-03-15 | 2017-05-10 | 台湾积体电路制造股份有限公司 | Semiconductor arrangement and formation thereof |
| US9123642B1 (en) * | 2013-07-22 | 2015-09-01 | Cypress Semiconductor Corporation | Method of forming drain extended MOS transistors for high voltage circuits |
| CN105070688B (en) * | 2015-07-21 | 2018-05-29 | 上海华力微电子有限公司 | A kind of CMOS trap forming methods for saving light shield |
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2020
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| CN113506739A (en) * | 2021-06-09 | 2021-10-15 | 上海华虹宏力半导体制造有限公司 | Core MOS device and process method |
| CN114496925A (en) * | 2022-04-01 | 2022-05-13 | 晶芯成(北京)科技有限公司 | Semiconductor structure and preparation method thereof |
| CN114496925B (en) * | 2022-04-01 | 2022-07-01 | 晶芯成(北京)科技有限公司 | Semiconductor structure and preparation method thereof |
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