CN112002634A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN112002634A CN112002634A CN202010719304.9A CN202010719304A CN112002634A CN 112002634 A CN112002634 A CN 112002634A CN 202010719304 A CN202010719304 A CN 202010719304A CN 112002634 A CN112002634 A CN 112002634A
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- 238000000034 method Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000005641 tunneling Effects 0.000 claims abstract description 30
- 238000002955 isolation Methods 0.000 claims description 40
- 230000008569 process Effects 0.000 claims description 37
- 230000003647 oxidation Effects 0.000 claims description 21
- 238000007254 oxidation reaction Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 16
- 238000003860 storage Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000005019 vapor deposition process Methods 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42352—Gate electrodes for transistors with charge trapping gate insulator with the gate at least partly formed in a trench
Abstract
The invention provides a method for forming a semiconductor structure, which comprises the steps of rounding the top corner of an active region in a semiconductor substrate, so that the corner of an ONO stack structure formed on the active region after rounding is in the shape of a circular arc, the thickness of a tunneling oxide layer on the corner of the active region is basically the same as that of the tunneling oxide layer in other regions, the problem that point discharge occurs at the corner of the active region when a programming voltage/an erasing voltage is applied to a corresponding memory cell is solved, the electric field strength at the corner of the active region is similar to that of other normal regions, the tunneling medium layer at the corner of the active region and the tunneling medium layer in other regions of the active region encounter the basically same electron/hole tunneling condition when data is stored, and the problem that the electron/hole stored in the ONO stack structure of the memory cell at the position is easy to lose is solved, thereby improving the reliability of the finally formed semiconductor memory device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor structure.
Background
Nonvolatile memory, which is an indispensable storage device in computers, plays an important storage function for processed information. The SONOS (Silicon-Oxide-Nitride-Oxide-Silicon ) memory has the characteristics of small unit size, good storage retentivity, low operating voltage, compatibility with a CMOS (complementary metal Oxide semiconductor) process and the like. The SONOS memory device is a charge trap type memory device using a gate stack structure of a semiconductor substrate, a tunneling oxide layer, a nitride layer, a blocking oxide layer, and a polysilicon gate layer (i.e., SONOS). When forming a SONOS memory, an ONO stack structure is required to be formed in a SONOS memory region. In addition, the SONOS memory usually employs a tunnel hot electron injection effect or a tunneling effect to trap the charge traps, thereby causing a change in the threshold voltage of the device unit and achieving the effect of data storage.
As SONOS memory devices continue to shrink in size, the contact area between the ONO stack structure and the active region formed in the semiconductor substrate continues to shrink, thereby resulting in fewer and fewer electrons or holes being stored in each memory cell. In order to enlarge or maintain a considerable window, it is an effective method to increase the contact area of the ONO stack structure with the active region. Under the existing process conditions, the tunneling oxide layer at the corner of the active region is thin, so that the damage is large during electron/hole tunneling when data is stored, and in addition, the curvature radius at the corner of the active region is small, so that when a programming voltage/an erasing voltage is applied to a corresponding memory cell, a point discharge phenomenon occurs at the corner of the active region, namely an electric field at the position is stronger than that in a normal region, so that electrons/holes stored in an ONO laminated structure of the memory cell are easy to lose, and the reliability problem of the SONOS memory is caused.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor structure, which aims to solve the problem that the reliability of a device is influenced because electrons/holes stored in an ONO laminated structure of a memory cell are easy to lose due to the fact that a tunneling oxide layer at the corner of an active region is thin.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
providing a semiconductor substrate, wherein at least one shallow trench and an active area limited by the shallow trench are arranged in the semiconductor substrate, a pad oxide layer and a hard mask layer are formed on the top surface of the active area, and the line width of the hard mask layer is smaller than that of the active area;
forming a first linear oxidation layer on the inner wall of the shallow trench through a first thermal oxidation process;
removing the first linear oxide layer and the liner oxide layer exposed by the hard mask layer by a wet method to expose the shallow trench and the top corner of the active region;
forming a second linear oxide layer on the inner wall of the shallow trench and the top corner of the active region through a second thermal oxidation process, wherein the top corner of the active region is in a round angle;
forming a shallow trench isolation structure filled in the shallow trench and removing the hard mask layer, wherein the top surface of the shallow trench isolation structure is lower than the top surface of the active region;
and forming an ONO lamination layer which at least covers the upper part of the active region and comprises a tunneling oxide layer, a nitride layer and a blocking oxide layer which are sequentially laminated.
Optionally, the step of providing the semiconductor substrate with the active region, the shallow trench and the hard mask layer may include:
providing a semiconductor substrate, and sequentially forming a pad oxide layer, a hard mask layer and a patterned photoresist layer on the semiconductor substrate;
taking the photoresist layer as a mask, and sequentially etching the hard mask layer, the pad oxide layer and the semiconductor substrate with partial thickness to form the shallow trench;
and removing the photoresist layer, and performing back etching on the hard mask layer to enable the line width of the hard mask layer to be smaller than the line width of the active region.
Optionally, the hard mask layer is etched back by using a wet etching process, and an etchant of the wet etching process may include phosphoric acid.
Optionally, the conditions of the first thermal oxidation process may include: the process temperature range is 800-1200 ℃.
Optionally, the thickness of the first linear oxide layer is 2nm to 10 nm.
Optionally, the conditions of the second thermal oxidation process include: the process temperature range is 800-1200 ℃.
Optionally, the thickness of the second linear oxide layer is 2nm to 10 nm.
Optionally, the step of forming the shallow trench isolation structure filled in the shallow trench may include:
filling an isolation medium layer in the shallow trench through a vapor deposition process, wherein the deposited isolation medium layer at least fills the shallow trench;
performing chemical mechanical planarization on the top of the isolation dielectric layer until the top surface of the pad oxide layer is exposed so as to remove the hard mask layer;
and carrying out back etching on the isolation medium layer to enable the top surface of the isolation medium layer to be lower than the top surface of the active region, so as to form the shallow trench isolation structure.
Optionally, after forming the shallow trench isolation structure and before forming the ONO stack, the method may further include:
performing channel ion implantation on the active region;
and removing the liner oxide layer.
Optionally, after forming the ONO stack, the method may further include:
patterning the ONO stack by photolithography and etching processes;
and forming a grid layer on the ONO laminated layer so as to form a storage unit of the SONOS device.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
in the method for forming the semiconductor structure, the top corner of the active region in the semiconductor substrate is rounded, so that the shape of the corner of the ONO stack structure formed on the active region after the rounding treatment is circular arc, and the thickness of the tunneling oxide layer on the corner of the active region is basically the same as that of the tunneling oxide layer in other regions, thereby avoiding the problem that the point discharge phenomenon occurs at the corner of the active region when the programming voltage/erasing voltage is applied to the corresponding storage unit, so that the electric field strength at the corner of the active region is close to that of other normal regions, and the tunneling medium layer at the corner of the active region and the tunneling medium layer in other regions of the active region encounter the basically same electron/hole tunneling condition when storing data, and avoiding the problem that the electron/hole stored in the ONO stack structure of the storage unit at the position is easy to lose, thereby improving the reliability of the finally formed semiconductor memory device.
Drawings
FIGS. 1a to 1d are schematic structural views of a semiconductor structure during a fabrication process thereof;
FIG. 2 is a flow chart illustrating a method of forming a semiconductor structure according to an embodiment of the present invention;
fig. 3a to 3f are schematic structural diagrams of a method for forming a semiconductor device in a manufacturing process of the semiconductor device according to an embodiment of the invention.
Detailed Description
As described in the background, as SONOS memory devices are scaled down, the contact area between the ONO stack structure and the active region formed in the semiconductor substrate is reduced, and thus, each memory cell stores fewer and fewer electrons or holes. In order to enlarge or maintain a considerable window, it is an effective method to increase the contact area of the ONO stack structure with the active region. Under the existing process conditions, the tunnel oxide layer at the corner of the active region is thin, so that the damage is large when electron/hole tunneling is performed during data storage, and in addition, the curvature radius at the corner of the active region is small, so that when a programming voltage/an erasing voltage is applied to a corresponding storage unit, a point discharge phenomenon occurs at the corner of the active region, namely an electric field at the position is stronger than that in a normal region, so that electrons/holes stored in an ONO laminated structure of the storage unit are easy to lose, and the reliability problem of the SONOS memory is caused. Referring to fig. 1a to 1d specifically, fig. 1a to 1d are schematic structural diagrams of a SONOS memory structure in a conventional fabrication process thereof, and as shown in fig. 1a to 1d, a method for forming the SONOS memory structure may include the following steps:
in step one, specifically referring to fig. 1a, a substrate 100 is provided, and a pad oxide layer 110 and a hard mask layer 120 (typically, silicon nitride) are sequentially formed on the substrate 100.
Step two, specifically referring to fig. 1b, sequentially etching the hard mask layer 120, the pad oxide layer 110 and the substrate 100 with a partial thickness through photolithography and etching processes, so as to form a shallow trench 101 and an active region M defined by the shallow trench 101 on the substrate 100. A phosphoric acid push-back (pull back) hard mask layer 120 is further used to make the line width of the hard mask layer 120 on the surface of the active region M smaller than that of the active region M, and both sides of the hard mask layer 120 can expose the top surface of the underlying portion of the pad oxide layer 110, so that the top corner of the active region M is in a corner shape.
Step three, specifically referring to fig. 1c, forming a line oxide layer 130 on the inner wall of the shallow trench 101 by a thermal oxidation process or the like, so that the line oxide layer 130 covers the bottom and the sidewall of the shallow trench 101. At this time, the top corners of the active region M are still in the shape of the corners after being oxidized only once.
Step four, referring to fig. 1d specifically, by using a vapor deposition process, filling the shallow trench 101 with the isolation dielectric material layer 140, mechanically grinding the top of the isolation dielectric material layer 140 until the pad oxide layer 120 is exposed, and further performing a wet etching back process on the isolation dielectric material layer 140 to control the top surface of the isolation dielectric material layer 140 in the SONOS storage area to be below the top surface of the active area M, thereby forming the shallow trench isolation structure STI. After the ion implantation related to the active region is completed, the pad oxide layer 120 is removed, and an ONO stack 150 is further formed on the active region M and the shallow trench isolation structure STI, where the ONO stack 150 includes a tunneling oxide layer 151, a nitride layer 152, and a blocking oxide layer 153.
It should be noted that, when data is stored, damage is large during electron/hole tunneling due to the thin thickness of the tunnel oxide layer 151 at the top corner of the active region, and in addition, when a program voltage/an erase voltage is applied to a memory cell formed on the active region M due to the small radius of curvature at the top corner of the active region M, a tip discharge phenomenon occurs at the top corner of the active region M, that is, an electric field is stronger than that in a normal region, so that electrons/holes stored in the ONO stack are easily lost, thereby causing a reliability problem of the SONOS memory.
Therefore, the invention provides a method for forming a semiconductor structure to improve the reliability of a device. For example, referring to fig. 2, the method for forming the semiconductor structure in the present embodiment includes:
step S100, providing a semiconductor substrate, wherein at least one shallow groove and an active area limited by the shallow groove are arranged in the semiconductor substrate, a pad oxide layer and a hard mask layer are formed on the top surface of the active area, and the line width of the hard mask layer is smaller than that of the active area;
step S200, forming a first linear oxidation layer on the inner wall of the shallow trench through a first thermal oxidation process;
step S400, forming a second linear oxide layer on the inner wall of the shallow trench and the top corner of the active region through a second thermal oxidation process, wherein the top corner of the active region is rounded;
step S500, forming a shallow trench isolation structure filled in the shallow trench and removing the hard mask layer, wherein the top surface of the shallow trench isolation structure is lower than the top surface of the active region;
step S600, forming an ONO stack at least covering the active region, and including a tunneling oxide layer, a nitride layer, and a blocking oxide layer stacked in sequence.
That is, in the method for forming a semiconductor structure provided by the present invention, the top corner of the active region in the semiconductor substrate is rounded, so that the corner of the ONO stack structure formed on the active region after the rounding is shaped as an arc, and the thickness of the tunneling oxide layer at the corner of the active region is substantially the same as that of the tunneling oxide layer in other regions, thereby solving the problem that the corner of the active region will generate the tip discharge phenomenon when the programming voltage/erasing voltage is applied to the memory cell formed at the active region, and the electric field at the corner of the active region is close to or the same as that of the normal region, and the tunneling medium at the corner of the active region and the tunneling medium at other regions of the active region will encounter the substantially same electron/hole tunneling condition when storing data, so that the electrons/holes stored in the ONO stack structure of the memory cell formed at the active region are not easily lost, thereby improving the reliability of the finally formed semiconductor memory structure. The method of the invention is not only suitable for improving the reliability of the SONOS memory, but also suitable for improving the reliability of any memory using an ONO laminated structure as a storage medium.
The semiconductor device and the method for forming the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 3a to 3f are schematic structural views illustrating a method for forming a semiconductor structure in a manufacturing process according to an embodiment of the invention.
In step S100, referring to fig. 3b specifically, a semiconductor substrate 300 is provided, where the semiconductor substrate 300 is provided with at least one shallow trench 301 and an active region I defined by the shallow trench 301, a pad oxide layer 310 ' and a hard mask layer 320 ' are formed on a top surface of the active region I, and a line width of the hard mask layer 320 ' is smaller than a line width of the active region I.
In this embodiment, the material of the semiconductor substrate may be silicon, germanium, silicon carbide, or the like, may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be another material, such as a group III or V compound such as gallium arsenide. Illustratively, the semiconductor substrate 300 in the embodiment of the present invention is a silicon substrate. In addition, the semiconductor substrate 300 may also be implanted with certain dopant ions to change electrical parameters according to design requirements.
Further, in the embodiment of the present invention, the step of providing the semiconductor substrate 300 having the active region I, the shallow trench 301 and the hard mask layer 320' may include:
first, referring specifically to fig. 3a, a semiconductor substrate 300 is provided, and a pad oxide layer 310, a hard mask layer 320 and a patterned photoresist layer (not shown) are sequentially formed on the semiconductor substrate 300.
Then, referring to fig. 3b specifically, the hard mask layer 320, the pad oxide layer 310 and the semiconductor substrate 300 with a partial thickness are sequentially etched using the photoresist layer as a mask to form the shallow trench 301. It is understood that, in the embodiment of the present invention, only two shallow trenches 301 and the active region I are exemplarily formed, and in other embodiments, a plurality of shallow trenches and a plurality of active regions defined by the shallow trenches may be formed, that is, a plurality of memory cells may be formed in a storage region of the SONOS memory.
And then, removing the photoresist layer, and performing back etching on the hard mask layer 320 to make the line width of the remaining hard mask layer 320' smaller than the line width of the active region I.
In this embodiment, a hard mask layer 320 ' with a line width smaller than that of the active region I may be formed on the surface of the active region I by using a phosphoric acid back (pull back) method to expose the top surface of a portion of the pad oxide layer 310 ' below the hard mask layer 320 ' on both sides thereof, so as to perform subsequent steps, thereby achieving the purpose of rounding the top corner of the active region I.
Wherein, the top corner of the active region I is in a shape of a corner.
In step S200, referring to fig. 3c in particular, a first linear oxide layer 330 is formed on the inner wall of the shallow trench 301 by a first thermal oxidation process.
Wherein, the process temperature range of the first thermal oxidation process can be 800-1200 ℃; the thickness of the first linear oxide layer may be 2nm to 10 nm.
In step S300, referring to fig. 3d specifically, the first linear oxide layer 330 and the liner oxide layer 310 'exposed by the hard mask layer 320' are removed by a wet method to expose the shallow trench 301 and the top corner a of the active region I. Illustratively, the conditions of the wet process may be that the etching time is 2-10 min, the etching temperature is 20-50 ℃, and the etchant may be 5-20% hydrofluoric acid or a reagent having a similar silicon oxide etching capability, which is not particularly limited in the present invention.
In step S400, referring to fig. 3e specifically, a second thermal oxidation process is performed to form a second linear oxide layer 340 on the inner wall of the shallow trench 301 and the top corner of the active region I, so that the top corner of the active region I is rounded a'.
In this embodiment, since the oxidation speed of the exposed semiconductor substrate at the corner of the top of the active region I is faster than the oxidation speed of the semiconductor substrate on the inner wall of the shallow trench 301 in the process of forming the second linear oxide layer silicon oxide 340, after the second linear oxide layer 340 is formed, the corner of the top of the active region I is changed from a corner to a rounded corner, and the second linear oxide layer 340 formed on the surface of the active region I is also in the shape of an arc, so that the thickness of the tunneling oxide layer 251 formed in the subsequent step S600 in the embodiment of the present invention at the corner of the active region I is thicker, thereby avoiding the problem of great damage during electron/hole tunneling when data is stored.
Wherein, the process temperature range of the second thermal oxidation process can be 800-1200 ℃; the thickness of the second linear oxidation layer is 2 nm-10 nm.
Step S500, referring to fig. 3f specifically, a shallow trench isolation structure 350 filled in the shallow trench 301 is formed and the hard mask layer 320' is removed, where the top surface of the shallow trench isolation structure 350 is lower than the top surface of the active region I.
Optionally, the step of forming the shallow trench isolation structure 350 filled in the shallow trench 301 may include:
firstly, an isolation medium layer is filled in the shallow trench 301 through a vapor deposition process, and the deposited isolation medium layer at least fills the shallow trench. The isolation dielectric layer may be silicon dioxide.
And then, carrying out chemical mechanical planarization on the top of the isolation dielectric layer until the top surface of the pad oxide layer is exposed so as to remove the hard mask layer.
And then, performing back etching on the isolation medium layer to make the top surface of the isolation medium layer lower than the top surface of the active region, so as to form the shallow trench isolation structure 350 filled in the shallow trench 301.
Step S600, with reference to fig. 3f, sequentially depositing an oxide and a nitride, and then depositing an oxide again to form an ONO stack 250, where the ONO stack 250 at least covers the active region I and includes a tunneling oxide layer 251, a nitride layer 252, and a blocking oxide layer 253, which are sequentially stacked. Since the top corner of the active region I is rounded, the thickness of the tunnel oxide layer 251 on the top corner of the active region I is substantially the same as the thickness of the tunnel oxide layer 251 in the remaining region.
In the present embodiment, since the top corner of the active region I has been transformed from a prism shape to a rounded shape when the ONO stack 250 is formed, the ONO stack 250 formed thereon is shaped like a circular arc here, thereby preventing the occurrence of the tip discharge phenomenon at the corners of the active region I when the program voltage/erase voltage is applied to the corresponding memory cell, and since the top corner of the active region I is a rounded corner, the thickness of the tunnel oxide layer 251 on the top corner of the active region I is substantially the same as the thickness of the tunnel oxide layer 251 in the remaining region, when storing data, no more damage than required can be caused during electron/hole tunneling, therefore, the situation that the electron/hole stored in the ONO laminated layer on the active area is not easy to lose can be avoided, and the reliability of the finally formed semiconductor memory structure is improved.
Further, after the shallow trench isolation structure 350 is formed and before the ONO stack 250 is formed, the method for forming the semiconductor structure according to the embodiment of the present invention may further include the following steps:
firstly, channel ion implantation is carried out on the active region I. Including, for example, trap ion implantation, threshold voltage adjustment ion implantation, and the like;
then, the pad oxide layer 310 is removed.
In this embodiment, well ion implantation may be performed on the active region I to form a drain region, a source region, and a channel region, so as to complete programming/erasing operations on a memory cell formed by the ONO stack structure when different voltages are applied to the drain region, the source region, and the communication region; meanwhile, threshold voltage ion implantation can also be performed on the active region I so as to adjust the initial threshold opening voltage of the memory cell formed by the ONO stacked structure.
Optionally, in other embodiments of the present invention, after the shallow trench isolation structure 350 is formed and before the ONO stack 250 is formed, channel ion implantation is performed on the active region I, and the pad oxide layer 310 is retained, and then an ONO stack structure is directly formed on the pad oxide layer 310.
Optionally, after forming the ONO stack 250, the method for forming a semiconductor structure provided in the embodiment of the present invention may further include the following steps:
patterning the ONO stack by photolithography and etching processes; and forming a gate layer on the ONO lamination layer so as to form a memory cell of the SONOS device.
In summary, in the method for forming a semiconductor structure provided by the present invention, the top corner of the active region in the semiconductor substrate is rounded, so that the corner of the ONO stack structure formed on the active region after the rounding is shaped as an arc, thereby solving the problem that when a program voltage/erase voltage is applied to the memory cell of the SONOS memory, a tip discharge phenomenon occurs at the corner of the active region, that is, an electric field at the corner is stronger than that in a normal region, so that electrons/holes stored in the ONO stack structure of the memory cell are easily lost, thereby resulting in reliability of the SONOS memory.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the above embodiments are not intended to limit the present invention. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are within the scope of protection of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein at least one shallow trench and an active area limited by the shallow trench are arranged in the semiconductor substrate, a pad oxide layer and a hard mask layer are formed on the top surface of the active area, and the line width of the hard mask layer is smaller than that of the active area;
forming a first linear oxidation layer on the inner wall of the shallow trench through a first thermal oxidation process;
removing the first linear oxide layer and the liner oxide layer exposed by the hard mask layer by a wet method to expose the shallow trench and the top corner of the active region;
forming a second linear oxide layer on the inner wall of the shallow trench and the top corner of the active region through a second thermal oxidation process, wherein the top corner of the active region is in a round angle;
forming a shallow trench isolation structure filled in the shallow trench and removing the hard mask layer, wherein the top surface of the shallow trench isolation structure is lower than the top surface of the active region;
and forming an ONO lamination layer which at least covers the upper part of the active region and comprises a tunneling oxide layer, a nitride layer and a blocking oxide layer which are sequentially laminated.
2. The method of forming a semiconductor structure of claim 1, wherein providing a semiconductor substrate having the active region, shallow trench and hard mask layer comprises:
providing a semiconductor substrate, and sequentially forming a pad oxide layer, a hard mask layer and a patterned photoresist layer on the semiconductor substrate;
taking the photoresist layer as a mask, and sequentially etching the hard mask layer, the pad oxide layer and the semiconductor substrate with partial thickness to form the shallow trench;
and removing the photoresist layer, and performing back etching on the hard mask layer to enable the line width of the hard mask layer to be smaller than that of the active region.
3. The method of claim 1, wherein the hard mask layer is etched back using a wet etch process, wherein an etchant of the wet etch process comprises phosphoric acid.
4. The method of forming a semiconductor structure of claim 1, wherein the conditions of the first thermal oxidation process comprise: the process temperature range is 800-1200 ℃.
5. The method of claim 1, wherein the first linear oxide layer has a thickness of 2nm to 10 nm.
6. The method of forming a semiconductor structure of claim 1, wherein the conditions of the second thermal oxidation process comprise: the process temperature range is 800-1200 ℃.
7. The method of claim 1, wherein the second linear oxide layer has a thickness of 2nm to 10 nm.
8. The method of claim 1, wherein the step of forming the shallow trench isolation structure filled in the shallow trench comprises:
filling an isolation medium layer in the shallow trench through a vapor deposition process, wherein the deposited isolation medium layer at least fills the shallow trench;
performing chemical mechanical planarization on the top of the isolation dielectric layer until the top surface of the pad oxide layer is exposed so as to remove the hard mask layer;
and carrying out back etching on the isolation medium layer to enable the top surface of the isolation medium layer to be lower than the top surface of the active region, so as to form the shallow trench isolation structure.
9. The method of forming a semiconductor structure of claim 1, further comprising, after forming the shallow trench isolation structure and before forming the ONO stack:
performing channel ion implantation on the active region;
and removing the liner oxide layer.
10. The method of forming a semiconductor structure of claim 1, further comprising, after forming the ONO stack:
patterning the ONO stack by photolithography and etching processes;
and forming a grid layer on the ONO laminated layer so as to form a storage unit of the SONOS device.
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| CN202010719304.9A CN112002634A (en) | 2020-07-23 | 2020-07-23 | Method for forming semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050045963A1 (en) * | 2003-07-23 | 2005-03-03 | Frank Lau | Charge trapping memory cell |
| US20090121276A1 (en) * | 2007-11-08 | 2009-05-14 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices with recessed word lines |
| US20090191688A1 (en) * | 2008-01-28 | 2009-07-30 | Texas Instruments Incorporated | Shallow Trench Isolation Process Using Two Liners |
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- 2020-07-23 CN CN202010719304.9A patent/CN112002634A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050045963A1 (en) * | 2003-07-23 | 2005-03-03 | Frank Lau | Charge trapping memory cell |
| US20090121276A1 (en) * | 2007-11-08 | 2009-05-14 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices with recessed word lines |
| US20090191688A1 (en) * | 2008-01-28 | 2009-07-30 | Texas Instruments Incorporated | Shallow Trench Isolation Process Using Two Liners |
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Application publication date: 20201127 |