CN111988196A - Bandwidth detection method and device, electronic equipment and storage medium - Google Patents
Bandwidth detection method and device, electronic equipment and storage medium Download PDFInfo
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- CN111988196A CN111988196A CN202010703862.6A CN202010703862A CN111988196A CN 111988196 A CN111988196 A CN 111988196A CN 202010703862 A CN202010703862 A CN 202010703862A CN 111988196 A CN111988196 A CN 111988196A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0876—Network utilisation, e.g. volume of load or congestion level
- H04L43/0894—Packet rate
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- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B3/00—Audible signalling systems; Audible personal calling systems
- G08B3/10—Audible signalling systems; Audible personal calling systems using electric transmission; using electromagnetic transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/02—Standardisation; Integration
- H04L41/0246—Exchanging or transporting network management information using the Internet; Embedding network management web servers in network elements; Web-services-based protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0631—Management of faults, events, alarms or notifications using root cause analysis; using analysis of correlation between notifications, alarms or events based on decision criteria, e.g. hierarchy, tree or time analysis
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0677—Localisation of faults
Abstract
The embodiment of the application relates to a bandwidth detection method, a bandwidth detection device, electronic equipment and a storage medium, and the method comprises the following steps: acquiring an actual bandwidth and a first theoretical bandwidth of the external device, and detecting a second theoretical bandwidth of the external device, wherein the actual bandwidth is used for indicating an actual state bandwidth of the external device, the first theoretical bandwidth is used for indicating a due capacity bandwidth of the external device, and the second theoretical bandwidth is used for indicating a real bandwidth of the external device; and whether the bandwidth fails or not is directly determined according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth, so that the time for detecting the bandwidth failure or the normal bandwidth is saved, and the efficiency for detecting the bandwidth failure or the normal bandwidth is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of bandwidth detection, in particular to a bandwidth detection method and device, electronic equipment and a storage medium.
Background
With the rapid development of the internet technology, the service of the data center is continuously increased, artificial intelligence, the internet of things, cloud computing, big data and the like are developed rapidly, the number and the scale of the data center are rapidly increased, and higher requirements are provided for the bandwidth information of the server. The PCIE interface is one of the most common peripheral interfaces of the server, and a large number of external devices including a network card, a Raid card, an FPGA card, a GPU card, an NVME hard disk, and the like are all applied to the server through the PCIE interface, but whether the bandwidth of the server fails after the external device is connected thereto cannot be detected quickly, which results in long detection failure time. How to implement bandwidth failure detection becomes a problem that needs to be continuously improved.
Disclosure of Invention
To solve at least one problem in the prior art, at least one embodiment of the present application provides a bandwidth detection method, apparatus, electronic device, and storage medium.
In a first aspect, an embodiment of the present application provides a bandwidth detection method, including:
acquiring an actual bandwidth and a first theoretical bandwidth of the external device, wherein the actual bandwidth is used for indicating an actual state bandwidth of the external device, and the first theoretical bandwidth is used for indicating a due capacity bandwidth of the external device;
detecting a second theoretical bandwidth of the external equipment, wherein the second theoretical bandwidth is used for indicating the real bandwidth of the external equipment;
and determining whether the bandwidth fails according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth.
In a second aspect, an embodiment of the present application provides a bandwidth detection apparatus, including:
an acquisition module: the method comprises the steps of obtaining an actual bandwidth and a first theoretical bandwidth of the external device, wherein the actual bandwidth is used for indicating an actual state bandwidth of the external device, and the first theoretical bandwidth is used for indicating a due capacity bandwidth of the external device;
a detection module: the second theoretical bandwidth is used for indicating the real bandwidth of the external equipment;
a determination module: and the method is used for determining whether the bandwidth fails according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth.
In a third aspect, an embodiment of the present application provides an electronic device, including: a processor and a memory;
the processor is used to perform the steps of the bandwidth detection method as described above by calling a program or instructions stored by the memory.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing a program or instructions for causing a computer to perform the steps of the bandwidth detection method as described above.
The embodiment of the application has the advantages that: detecting a second theoretical bandwidth of the external device by acquiring an actual bandwidth and a first theoretical bandwidth of the external device, wherein the actual bandwidth is used for indicating an actual state bandwidth of the external device, the first theoretical bandwidth is used for indicating a due capacity bandwidth of the external device, and the second theoretical bandwidth is used for indicating a real bandwidth of the external device; and whether the bandwidth fails or not is directly determined according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth, so that the time for detecting the bandwidth failure or the normal bandwidth is saved, and the efficiency for detecting the bandwidth failure or the normal bandwidth is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
Fig. 1 is a flowchart of a bandwidth detection method provided in an embodiment of the present application;
fig. 2 is an architecture diagram of a bandwidth detection method provided in an embodiment of the present application;
fig. 3 is a schematic diagram of a bandwidth detection apparatus provided in an embodiment of the present application;
fig. 4 is a block diagram of an electronic device provided in an embodiment of the present application.
Detailed Description
In order that the above objects, features and advantages of the present application can be more clearly understood, the present disclosure will be further described in detail with reference to the accompanying drawings and examples. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. The specific embodiments described herein are merely illustrative of the disclosure and are not limiting of the application. All other embodiments that can be derived by one of ordinary skill in the art from the description of the embodiments are intended to be within the scope of the present disclosure.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Aiming at least one problem existing in the prior art, the embodiment of the application provides a bandwidth fault detection method and device.
Fig. 1 is a flowchart of a bandwidth detection method according to an embodiment of the present application.
Fig. 2 is an architecture diagram of a bandwidth detection method according to an embodiment of the present application.
In a first aspect, with reference to fig. 1 and fig. 2, an embodiment of the present application discloses a bandwidth detection method, which specifically includes the following three steps 101, 102, and 103.
101: the method comprises the steps of obtaining an actual bandwidth and a first theoretical bandwidth of the external device, wherein the actual bandwidth is used for indicating an actual state bandwidth of the external device, and the first theoretical bandwidth is used for indicating a due capacity bandwidth of the external device.
Specifically, with reference to fig. 2, in this embodiment of the present application, the external device may be a network card, a Raid card, an FPGA card, a GPU card, an NVME hard disk, and the like, after the external device is accessed to the server, and after the external device is powered on, when the basic input/output system BIOS detects hardware, the bandwidth obtained by detection is sent to the BMC of the substrate management controller through the SPI protocol, where the bandwidth includes: an actual bandwidth and a first theoretical bandwidth. The baseboard management controller BMC sends the actual bandwidth and the first theoretical bandwidth to the programmable logic device CPLD, and the programmable logic device CPLD respectively stores the actual bandwidth and the first theoretical bandwidth into the complex programmable logic device CPLD register II and the complex programmable logic device CPLD register III.
And 102, detecting a second theoretical bandwidth of the external equipment, wherein the second theoretical bandwidth is used for indicating the real bandwidth of the external equipment.
Specifically, in step 102, with reference to fig. 2, a second theoretical bandwidth is obtained through hardware connection line detection, and the second theoretical bandwidth is sent to the complex programmable logic device CPLD, and the complex programmable logic device CPLD stores the second theoretical bandwidth to the first complex programmable logic device CPLD register.
And 103, determining whether the bandwidth fails according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth.
Specifically, in step 103, with reference to fig. 2, the CPLD stores the link rate or the substitute value in the second theoretical bandwidth stored in the first register of the CPLD and the first theoretical bandwidth stored in the third register of the CPLD into the fourth register of the CPLD, and obtains the binary value by comparing the bandwidth information stored in the fourth register and the second register to determine whether the bandwidth fails.
Specifically, in the specific application of the above three steps, fig. 2 is only one embodiment of the present application, and the protection scope of the present application is not limited by this embodiment.
In some embodiments, the determining whether the bandwidth fails according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth in step 103 in the method includes:
determining whether the bandwidth fails according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth, including:
determining whether the link value of the actual bandwidth and the link value of the second theoretical bandwidth are equal; determining whether the link rate of the actual bandwidth and the link rate of the first theoretical bandwidth are equal;
when the link value of the actual bandwidth is equal to the link value of the second theoretical bandwidth, and the link rate (generation value) of the actual bandwidth is equal to the link rate (generation value) of the first theoretical bandwidth, determining that the bandwidth is normal;
when the link value of the actual bandwidth is not equal to the link value of the second theoretical bandwidth, and the link rate (generation value) of the actual bandwidth is equal to the link rate (generation value) of the first theoretical bandwidth; or the like, or, alternatively,
when the link value of the actual bandwidth is equal to the link value of the second theoretical bandwidth and the link rate (generation value) of the actual bandwidth is not equal to the link rate (generation value) of the first theoretical bandwidth; or the like, or, alternatively,
when the link value of the actual bandwidth is not equal to the link value of the second theoretical bandwidth and the link rate (generation value) of the actual bandwidth is not equal to the link rate (generation value) of the first theoretical bandwidth; determining that the bandwidth is faulty.
Specifically, with reference to fig. 2, after comparing the bandwidth information stored in the second register and the fourth register, the binary value obtained by the comparison is stored in the fifth register, and it is determined that the bandwidth is faulty or normal.
Such as: when the link value of the actual bandwidth stored in the register II is equal to the link value of the second theoretical bandwidth stored in the register IV, and the link rate (generation value) of the actual bandwidth stored in the register II is equal to the link rate (generation value) of the first theoretical bandwidth stored in the register IV, determining that the bandwidth is normal;
and when the link value of the actual bandwidth stored in the register II is not equal to the link value of the second theoretical bandwidth stored in the register IV, and the link rate (generation value) of the actual bandwidth stored in the register II is equal to the link rate (generation value) of the first theoretical bandwidth stored in the register, the value of the register V is one, and the bandwidth is determined to be failed.
In some embodiments, the above method further comprises: and when the bandwidth is determined to be in fault, displaying that the bandwidth is in fault, and/or prompting that the bandwidth is in fault through a prompt tone.
Specifically, in the embodiment of the application, when the value of the register five is one, the LED indicator is turned on to determine that the bandwidth of the server accessing the external device is faulty, and when the value of the register five is zero, the LED indicator is turned off to determine that the bandwidth of the server accessing the external device is normal, so that the bandwidth of the server accessing the external device is faulty or normal through visual determination of the display of the LED indicator, and in a specific implementation, the bandwidth is also displayed through the access display, and the bandwidth is also prompted through the access buzzer device.
In some embodiments, the obtaining of the actual bandwidth and the first theoretical bandwidth of the external device in the method is obtained through an IIC line.
Specifically, referring to fig. 2, in the embodiment of the present application, the actual bandwidth and the first theoretical bandwidth may be directly obtained from the BMC through the IIC line.
In some embodiments, the second theoretical bandwidth of the external device is detected by a hardware connection line.
Specifically, with reference to fig. 2, in the embodiment of the present invention, a first pin PRSNT1 (pin a1, not shown in the figure) of a PCIE interface of the high-speed serial computer expansion bus standard is pulled down to be connected to ground, and second pins PRSNT2 (pins B17, B31, B48, and B82) are all pulled up to be connected to a power supply, where the external device itself at the specified second pin in the embodiment of the present invention is to connect a bit detection pin PRSNT1 and a PRSNT2 pin farthest from PRSNT1, for example: when an X4 external card is used, pins A1 and B31 of the external card are connected, and when the external device is accessed to a PCIE interface of the high-speed serial computer expansion bus standard, A1 and B31 are 0, and B17, B48 and B82 are 1, so that the signals can be fed back to the CPLD through high and low levels. Similarly, when the external device is an X1 external card, pins A1 of the external card are connected with pins B17 of the external card, and when the external device is accessed to a PCIE interface of the standard of the expansion bus of the high-speed serial computer, the pins A1 and B17 are 0, and the pins B17, B48 and B82 are 1; when the external device is an X8 external card, pins A1 of the external card are connected with pins B48, when the external device is accessed to a PCIE interface of the high-speed serial computer expansion bus standard, A1 and B48 are 0, and B17, B31 and B82 are 1; when an X16 external card is used, pins A1 and B82 of the external card are connected, when the external device is accessed to a PCIE interface of the high-speed serial computer expansion bus standard, A1 and B48 are 0, and B17, B31 and B48 are 1, so that high and low levels are fed back to a complex programmable logic device CPLD, and a second theoretical bandwidth obtained through hardware connection line detection is a link Lane value.
In some embodiments, the above method further comprises: the actual bandwidth and the first theoretical bandwidth are displayed.
Specifically, with reference to fig. 2, in this embodiment of the present application, through an IPMI protocol, the BMC implements the BMC to display an actual bandwidth and a first theoretical bandwidth at the WEB end of the global wide area network BMC, so that some relevant information of the machine, such as bandwidth, may be displayed on a remote WEB page, and specifically, the relevant information may further include: voltage, fan speed, CPU temperature etc. for example a machine is in the computer lab, and some relevant information such as bandwidth display of machine can be seen on remote webpage to base plate management controller global area network BMC WEB end to whether the condition that descends appears in bandwidth through the webpage is audio-visual, thereby the user can in time take the solution of answering, can also take html5 to show actual bandwidth and first theoretical bandwidth in addition this application embodiment, and does not restrict the protection scope of this application with this.
The actual bandwidth and the first theoretical bandwidth each include: generation (Gen) values and link (Lane) values, Gen values including: gen1, Gen2 and Gen3, Gen1, Gen2 and Gen3 refer to PCIE specifications 1.0, 2.0 and 3.0 single link peak bandwidth, which are 2.5GT/S, 5.0GT/S and 8.0GT/S respectively; and the link values include: x1, X4, X8, X16, X1, X4, X8, and X16 refer to 1lane, 4lane, 8lane, and 16lane, so that the total peak bandwidth is multiplied by Xn (1, 4, 8, and 16), for example, X8 refers to eight lanes of the link, Gen3 refers to the third generation, and each lane8GT/S, so that the total transmission rate is 8 × 8 — 64GT/S, there is a problem in accessing a link on a network card to a PCIE interface, which may be reduced to Gen2, but not to only 4 lanes, and then the total transmission rate is 5GT/S × 4 — 20 GT/S. 64GT/S is the first theoretical bandwidth and 20GT/S in this application is the actual bandwidth.
Fig. 3 is a schematic diagram of a bandwidth detection apparatus according to an embodiment of the present application.
In a second aspect, an embodiment of the present application provides a bandwidth detection apparatus, including: an acquisition module 301, a detection module 302 and a determination module 303;
the acquisition module 301: the method comprises the steps of obtaining an actual bandwidth and a first theoretical bandwidth of the external device, wherein the actual bandwidth is used for indicating an actual state bandwidth of the external device, and the first theoretical bandwidth is used for indicating a due capacity bandwidth of the external device;
specifically, with reference to fig. 2, in this embodiment of the present application, the external device may be a network card, a Raid card, an FPGA card, a GPU card, an NVME hard disk, and the like, after the external device is accessed to the server, and after the external device is powered on, when the basic input/output system BIOS detects hardware, the bandwidth obtained by detection is sent to the BMC of the substrate management controller through the SPI protocol, where the bandwidth includes: an actual bandwidth and a first theoretical bandwidth. The baseboard management controller BMC sends the actual bandwidth and the first theoretical bandwidth to the programmable logic device CPLD, the programmable logic device CPLD respectively stores the first theoretical bandwidth and the actual bandwidth into the complex programmable logic device CPLD register II and the complex programmable logic device CPLD register III, and the acquisition module acquires the actual bandwidth and the first theoretical bandwidth in the embodiment.
The detection module 302: the second theoretical bandwidth is used for indicating the real bandwidth of the external equipment;
specifically, with reference to fig. 2, a second theoretical bandwidth is obtained through detection by the detection module, and is sent to the complex programmable logic device CPLD, and the programmable logic device CPLD stores the second theoretical bandwidth to the first register of the complex programmable logic device CPLD.
The determination module 303: and the method is used for determining whether the bandwidth fails according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth.
Specifically, in step 103, with reference to fig. 2, the CPLD stores the second theoretical bandwidth stored in the CPLD register i and the link rate or the substitute value in the first theoretical bandwidth stored in the CPLD register i into the CPLD register iv of the complex programmable logic device, and the determination module compares the bandwidth information stored in the register iv and the register ii to obtain the binary value to determine whether the bandwidth fails.
Specifically, in the specific application of the above three steps, fig. 2 is only one embodiment of the present application, and the protection scope of the present application is not limited by this embodiment.
In some embodiments, the determining whether the bandwidth fails in the method includes:
determining whether the link value of the actual bandwidth and the link value of the second theoretical bandwidth are equal; determining whether the link rate of the actual bandwidth and the link rate of the first theoretical bandwidth are equal;
when the link value of the actual bandwidth is equal to the link value of the second theoretical bandwidth, and the link rate (generation value) of the actual bandwidth is equal to the link rate (generation value) of the first theoretical bandwidth, determining that the bandwidth is normal;
when the link value of the actual bandwidth is not equal to the link value of the second theoretical bandwidth, and the link rate (generation value) of the actual bandwidth is equal to the link rate (generation value) of the first theoretical bandwidth; or the like, or, alternatively,
when the link value of the actual bandwidth is equal to the link value of the second theoretical bandwidth and the link rate (generation value) of the actual bandwidth is not equal to the link rate (generation value) of the first theoretical bandwidth; or the like, or, alternatively,
when the link value of the actual bandwidth is not equal to the link value of the second theoretical bandwidth and the link rate (generation value) of the actual bandwidth is not equal to the link rate (generation value) of the first theoretical bandwidth; determining that the bandwidth is faulty.
Specifically, with reference to fig. 2, after comparing the bandwidth information stored in the second register and the fourth register, the binary value obtained by the comparison is stored in the fifth register, and it is determined that the bandwidth is faulty or normal.
Such as: when the link value of the actual bandwidth stored in the register II is equal to the link value of the second theoretical bandwidth stored in the register IV, and the link rate (generation value) of the actual bandwidth stored in the register II is equal to the link rate (generation value) of the first theoretical bandwidth stored in the register IV, determining that the bandwidth is normal;
and when the link value of the actual bandwidth stored in the register II is not equal to the link value of the second theoretical bandwidth stored in the register IV, and the link rate (generation value) of the actual bandwidth stored in the register II is equal to the link rate (generation value) of the first theoretical bandwidth stored in the register, the value of the register V is one, and the bandwidth is determined to be failed.
In some embodiments, the obtaining of the actual bandwidth and the first theoretical bandwidth of the external device is obtained via an IIC line.
In some embodiments, detecting the second theoretical bandwidth of the external device is detected via a hardwired connection.
In some embodiments, the above apparatus further comprises: a display module: for displaying the actual bandwidth and a first theoretical bandwidth.
In a third aspect, an embodiment of the present application provides an electronic device, including: a processor and a memory;
the processor is operable to perform the steps of the bandwidth detection method described above by invoking programs or instructions stored by the memory.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing a program or instructions for causing a computer to perform the steps of the bandwidth detection method as described above.
Fig. 4 is a schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. As shown in fig. 4, the electronic apparatus includes: at least one processor 401, at least one memory 402, and at least one communication interface 403. The various components in the electronic device are coupled together by a bus system 404. A communication interface 403 for information transmission with an external device. It is understood that the bus system 404 is used to enable communications among the components. The bus system 404 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, the various buses are labeled as bus system 404 in fig. 4.
It will be appreciated that the memory 402 in this embodiment can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
In some embodiments, memory 402 stores the following elements, executable units or data structures, or a subset thereof, or an expanded set thereof: an operating system and an application program.
The operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, and is used for implementing various basic services and processing hardware-based tasks. The application programs, including various application programs such as a Media Player (Media Player), a Browser (Browser), etc., are used to implement various application services. A program for implementing any one of the bandwidth detection methods provided in the embodiments of the present application may be included in an application program.
In this embodiment of the application, the processor 401 is configured to execute the steps of the embodiments of the bandwidth detection method provided by the embodiment of the application by calling a program or an instruction stored in the memory 402, which may be specifically a program or an instruction stored in an application program.
Any one of the bandwidth detection methods provided in the embodiments of the present application may be applied to the processor 401, or implemented by the processor 401. The processor 401 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 401. The Processor 401 may be a general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The steps of any method of the bandwidth detection method provided by the embodiment of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software units in the decoding processor. The software elements may be located in ram, flash, rom, prom, or eprom, registers, among other storage media that are well known in the art. The storage medium is located in a memory 402, and the processor 401 reads information in the memory 402 and performs the steps of the method in combination with its hardware.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Those skilled in the art will appreciate that although some embodiments described herein include some features included in other embodiments instead of others, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments.
Those skilled in the art will appreciate that the description of each embodiment has a respective emphasis, and reference may be made to the related description of other embodiments for those parts of an embodiment that are not described in detail.
Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations fall within the scope defined by the appended claims.
Claims (14)
1. A method of bandwidth detection, the method comprising:
acquiring an actual bandwidth and a first theoretical bandwidth of the external device, wherein the actual bandwidth is used for indicating an actual state bandwidth of the external device, and the first theoretical bandwidth is used for indicating a due capacity bandwidth of the external device;
detecting a second theoretical bandwidth of the external device, wherein the second theoretical bandwidth is used for indicating the real bandwidth of the external device;
and determining whether the bandwidth fails according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth.
2. The method of claim 1, wherein said determining whether the bandwidth is faulty based on the actual bandwidth, the first theoretical bandwidth, and the second theoretical bandwidth comprises:
determining whether the link value of the actual bandwidth and the link value of the second theoretical bandwidth are equal; determining whether the link rate of the actual bandwidth and the link rate of the first theoretical bandwidth are equal;
when the link value of the actual bandwidth is equal to the link value of the second theoretical bandwidth and the link rate of the actual bandwidth is equal to the link rate of the first theoretical bandwidth, determining that the bandwidth is normal;
when the link value of the actual bandwidth is not equal to the link value of the second theoretical bandwidth, and the link rate of the actual bandwidth is equal to the link rate of the first theoretical bandwidth; or the like, or, alternatively,
when the link value of the actual bandwidth is equal to the link value of the second theoretical bandwidth and the link rate of the actual bandwidth is not equal to the link rate of the first theoretical bandwidth; or the like, or, alternatively,
when the link value of the actual bandwidth is not equal to the link value of the second theoretical bandwidth, and the link rate of the actual bandwidth is not equal to the link rate of the first theoretical bandwidth; determining that the bandwidth is faulty.
3. The method according to claim 1 or 2, characterized in that the method further comprises: and when the bandwidth is determined to be in fault, displaying that the bandwidth is in fault, and/or prompting that the bandwidth is in fault through a prompt tone.
4. The method according to any one of claims 1 to 3, wherein the obtaining of the actual bandwidth and the first theoretical bandwidth of the external device is obtained through an IIC line.
5. The method according to any one of claims 1 to 4, wherein the detecting of the second theoretical bandwidth of the external device is detected via a hardwired connection.
6. The method of claim 1, further comprising:
and displaying the actual bandwidth and the first theoretical bandwidth.
7. A bandwidth detection apparatus, the apparatus comprising:
an acquisition module: the method comprises the steps of obtaining an actual bandwidth and a first theoretical bandwidth of the external device, wherein the actual bandwidth is used for indicating an actual state bandwidth of the external device, and the first theoretical bandwidth is used for indicating a due capacity bandwidth of the external device;
a detection module: the bandwidth detection module is used for detecting a second theoretical bandwidth of the external device, and the second theoretical bandwidth is used for indicating the real bandwidth of the external device;
a determination module: and the bandwidth fault detection module is used for determining whether the bandwidth has a fault according to the actual bandwidth, the first theoretical bandwidth and the second theoretical bandwidth.
8. The apparatus of claim 7, wherein the determining module is further configured to:
determining whether the link value of the actual bandwidth and the link value of the second theoretical bandwidth are equal; determining whether the link rate of the actual bandwidth and the link rate of the first theoretical bandwidth are equal;
when the link value of the actual bandwidth is equal to the link value of the second theoretical bandwidth and the link rate of the actual bandwidth is equal to the link rate of the first theoretical bandwidth, determining that the bandwidth is normal;
when the link value of the actual bandwidth is not equal to the link value of the second theoretical bandwidth, and the link rate of the actual bandwidth is equal to the link rate of the first theoretical bandwidth; or the like, or, alternatively,
when the link value of the actual bandwidth is equal to the link value of the second theoretical bandwidth and the link rate of the actual bandwidth is not equal to the link rate of the first theoretical bandwidth; or the like, or, alternatively,
when the link value of the actual bandwidth is not equal to the link value of the second theoretical bandwidth, and the link rate of the actual bandwidth is not equal to the link rate of the first theoretical bandwidth; determining that the bandwidth is faulty.
9. The apparatus of claim 7 or 8, wherein the determining module is further configured to: and when the bandwidth is determined to be in fault, displaying that the bandwidth is in fault, and/or prompting that the bandwidth is in fault through a prompt tone.
10. The apparatus according to any one of claims 7 to 9, wherein the obtaining of the actual bandwidth and the first theoretical bandwidth of the external device is obtained through an IIC line.
11. The apparatus according to any one of claims 7 to 10, wherein the detection of the second theoretical bandwidth of the external device is detected via a hardwired connection.
12. The apparatus of claim 7, further comprising a display module:
the display module: for displaying the actual bandwidth and a first theoretical bandwidth.
13. An electronic device, comprising: a processor and a memory;
the processor is configured to perform the steps of the bandwidth detection method according to any one of claims 1 to 6 by calling a program or instructions stored in the memory.
14. A computer-readable storage medium, characterized in that it stores a program or instructions for causing a computer to execute the steps of the bandwidth detection method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010703862.6A CN111988196B (en) | 2020-07-21 | 2020-07-21 | Bandwidth detection method and device, electronic equipment and storage medium |
Applications Claiming Priority (1)
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