CN111987108B - Three-dimensional memory device and manufacturing method thereof - Google Patents
Three-dimensional memory device and manufacturing method thereof Download PDFInfo
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention provides a three-dimensional memory device and a manufacturing method thereof, wherein the three-dimensional memory device comprises: the first interconnection layer is positioned on one side of the first substrate, which is away from the first stacking layer, and is provided with a first bonding contact electrically connected with the first channel, and the second interconnection layer is positioned on one side of the second stacking layer, which is away from the second substrate, and is provided with a second bonding contact electrically connected with the second storage string; the first interconnection layer and the second interconnection layer are oppositely arranged and bonded so that the first bonding contact and the second bonding contact are electrically connected, bonding of the first array structure and the second array structure is realized, the number of memory units of the three-dimensional memory device can be effectively increased, and the memory density can be better improved under the condition of low cost.
Description
[ field of technology ]
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory device and a manufacturing method thereof.
[ background Art ]
Three-dimensional memory (3D NAND) is an emerging memory type that addresses the limitations imposed by 2D or planar NAND flash memories by stacking memory particles together. Unlike placing memory chips on a single side, 3D NAND technology vertically stacks multiple layers of data storage units. Based on this technology, a memory device can be created that has a storage capacity up to several times higher than that of the similar NAND technology. The technology can support to accommodate higher storage capacity in a smaller space, thereby bringing great cost saving, energy consumption reduction and great performance improvement, so as to comprehensively meet the demands of numerous consumer mobile devices and most demanding enterprise deployment.
With advances in semiconductor technology, 3D NAND fabrication is bonded to memory cell array chips through complementary metal oxide semiconductor chips (CMOS chips) to form a frame of 3D NAND. How to increase the area of the 3D NAND core area and increase the storage density is a major consideration for the development of 3D NAND at present.
[ invention ]
The invention aims to provide a three-dimensional memory device and a manufacturing method thereof, which can effectively increase the number of memory cells of the three-dimensional memory device and improve the memory density.
In order to solve the above problems, the present invention provides a three-dimensional memory device comprising
A first array structure comprising a first substrate, a first stacked layer on the first substrate, a first memory string extending through the first stacked layer, and a first channel extending through the first stacked layer and the first substrate;
a second array structure including a second substrate, a second stacked layer on the second substrate, and a second memory string penetrating the second stacked layer;
a first interconnect layer on a side of the first substrate facing away from the first stack layer, the first interconnect layer having a first bonding contact electrically connected to the first via; and
the second interconnection layer is positioned on one side, away from the second substrate, of the second stacking layer, the second interconnection layer is provided with a second bonding contact electrically connected with the second storage string, and the first interconnection layer and the second interconnection layer are oppositely arranged and bonded so that the first bonding contact and the second bonding contact are electrically connected.
The first channel comprises a conductive channel penetrating through the first stacking layer and a conductive part embedded in the first substrate and contacted with the conductive channel, and the conductive part is electrically connected with the first interconnection layer; and a dielectric layer is arranged in the first substrate and surrounds the conductive part so as to isolate the conductive part from the first substrate.
Wherein, the critical dimension of the conductive part is larger than the critical dimension of the conductive channel.
Wherein the conductive channel is a virtual memory string.
The first interconnection layer comprises a first connecting line layer and a first bonding layer positioned on one side of the first connecting line layer away from the first substrate, the first connecting line layer comprises a first metal line layer electrically connected with the first channel, and the first bonding contact is positioned on the first bonding layer and electrically connected with the first metal line layer; the second interconnection layer comprises a second connecting line layer and a second bonding layer positioned on one side of the second connecting line layer away from the second stacking layer, the second connecting line layer comprises a second bit line layer electrically connected with the second storage string, and the second bonding contact is positioned on the second bonding layer and electrically connected with the second bit line layer; the first bonding layer and the second bonding layer are bonded.
Wherein the second array structure further comprises a second channel penetrating the second stacked layer and the second substrate, the second channel being electrically connected to the second interconnect layer; the third memory device further includes:
a third interconnect layer on a side of the second substrate facing away from the second stacked layer, the third interconnect layer having a third bond contact electrically connected to the second via;
a third array structure including a third substrate, a third stacked layer on the third substrate, and a third memory string penetrating the third stacked layer;
and the fourth interconnection layer is positioned on one side of the third stacking layer, which is away from the third substrate, and is provided with a fourth bonding contact electrically connected with the third storage string, and the fourth interconnection layer and the third interconnection layer are oppositely arranged and bonded so that the third bonding contact is electrically connected with the fourth bonding contact.
The first array structure further comprises a first bit line layer, the first bit line layer is located on one side, away from the first substrate, of the first stacking layer, and the first memory strings and the first channels are electrically connected with the first bit line layer.
The three-dimensional memory device further comprises a driving structure, wherein the driving structure is located on one side of the first stacking layer, which faces away from the first substrate, and is bonded with the first array structure.
In order to solve the above problems, the present invention further provides a method for manufacturing a three-dimensional memory device, including:
providing a first array structure comprising a first substrate, a first stacked layer on the first substrate, a first memory string extending through the first stacked layer, and a first channel extending through the first stacked layer and the first substrate;
providing a second array structure comprising a second substrate, a second stacked layer on the second substrate, and a second memory string extending through the second stacked layer;
forming a first interconnection layer on one side of the first substrate away from the first stacked layer, wherein the first interconnection layer is provided with a first bonding contact electrically connected with the first channel;
forming a second interconnection layer on one side of the second stack layer away from the second substrate, wherein the second interconnection layer is provided with a second bonding contact electrically connected with the second storage string;
and arranging and bonding the first interconnection layer and the second interconnection layer oppositely so as to electrically connect the first bonding contact and the second bonding contact.
Wherein the first channel comprises a conductive channel and a conductive portion, the providing a first array structure comprising:
providing a first substrate;
forming a conductive portion in the first substrate near one side of the first substrate;
forming a first stacked layer on one side of the first substrate facing away from the conductive part;
forming a conductive channel and a first memory string extending through the first stacked layer and to the conductive portion;
and thinning the surface of one side of the first substrate, which is away from the conductive part, so as to expose the conductive part, thereby obtaining a first array structure.
The beneficial effects of the invention are as follows: according to the three-dimensional memory device and the manufacturing method thereof, the first channel penetrating through the first stacking layer and the first substrate is arranged in the first array structure, the second interconnection layer is formed on the side, away from the second substrate, of the second stacking layer in the second array structure, meanwhile, the first interconnection layer is formed on the side, away from the first stacking layer, of the first substrate, and then the first interconnection layer and the second interconnection layer are oppositely arranged and bonded, so that when the first array structure is connected with an external circuit, the external circuit can control the first memory strings in the first array structure, and can control the second memory strings in the second array structure through the first channel, the first interconnection layer and the second interconnection layer, the number of memory units of the three-dimensional memory device is effectively increased, the memory density is better improved under the condition of low cost, and the practicability is high.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a perspective view of a part of the structure of a conventional array chip;
FIG. 2 is a schematic cross-sectional structure of a three-dimensional memory device provided in an embodiment of the present application;
FIG. 3 is a schematic cross-sectional structural view of a three-dimensional memory device provided in accordance with another embodiment of the present application;
FIG. 4 is a schematic flow chart of a method for fabricating a three-dimensional memory device according to an embodiment of the present disclosure;
FIG. 5a is a schematic cross-sectional view of a first array chip after step 1-1 in the fabrication process according to an embodiment of the present application;
FIG. 5b is a schematic cross-sectional view of a first array chip after step 1-2 in the fabrication process according to an embodiment of the present application;
FIG. 5c is a schematic cross-sectional view of a first array chip after steps 1-3 in the fabrication process provided in the embodiments of the present application;
FIG. 5d is a schematic cross-sectional view of the first array chip after step S1013 in the fabrication process according to an embodiment of the present application;
FIG. 5e is a schematic cross-sectional view of the first array chip after step S1014 in the fabrication process according to the embodiment of the present application;
FIG. 5f is a schematic cross-sectional view of the first array chip after step S1015 in the fabrication process according to the embodiment of the present application;
FIG. 5g is a schematic cross-sectional view of the first array chip after step S102 in the fabrication process according to the embodiment of the present application;
fig. 6 is a flow chart of a method for manufacturing a three-dimensional memory device according to another embodiment of the present application.
[ detailed description ] of the invention
The invention is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustrating the present invention, but do not limit the scope of the present invention. Likewise, the following examples are only some, but not all, of the examples of the present invention, and all other examples, which a person of ordinary skill in the art would obtain without making any inventive effort, are within the scope of the present invention.
It should be readily understood that directional terms, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], etc., as referred to herein are merely referring to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the invention and is not limiting of the invention. In the drawings, elements of similar structure are denoted by the same reference numerals. The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly.
It should be readily understood that the references to "on … …", "over … …" and "over … …" in the present invention should be interpreted in the broadest sense such that "on … … means not only" directly on something "but also includes the meaning of" on something "with intermediate features or layers therebetween.
The prior art three-dimensional memory device is formed by bonding a single memory cell array chip to a CMOS chip, and fig. 1 is a perspective view showing a partial structure of a prior art array chip 100. The array chip 100 includes a substrate 110, an insulating film 120 over the substrate 110, a lower select gate (low selection gate, LSG) 130 over the insulating film 120, a plurality of rows of control gates 140, also referred to as "Word Lines (WL)", over the lower select gate 130, and an upper select gate (top selection gate, TSG) 191 over the control gates 140. Dielectric layers (not shown) are also provided between the control gate 140, the lower select gate 130 and the upper select gate 191 to form a film stack 150 comprised of alternating conductive layers and dielectric layers.
The region of the array chip 100 may include a stepped region B and a channel structure region a divided in a vertical direction. The vertical direction is the stacking direction of the film stack. The channel structure region a may include an array of memory strings 160, each memory string 160 including a plurality of stacked memory cells. The stepped region B may include a stepped structure and an array of contact structures 170 formed on the stepped structure. A plurality of slit structures 180 extend in the WL direction, and at least some of the slit structures 180 may serve as a common source contact (e.g., an array common source) for the array of memory strings 160 in the channel structure region a.
The control gates of each row are divided into multiple individual control gates by slit structures 180-1 and 180-2 through film stack 150. The stack of TSG 191, control gate 140, and LSG 130 is also referred to as a "gate electrode". The array chip 100 further includes a memory string 160 and a doped source line region 192. Each memory string 160 includes a channel hole 161 through the insulating film 120 and the film stack 150. The memory string 160 further includes a memory film 162 on a sidewall of the channel hole 161, a channel layer 163 over the memory film 162, and a core fill film 164 surrounded by the channel layer 163. Memory cells (160-1, 160-2, and 160-3) may be formed at intersections of the control gates (140-1, 140-2, and 140-3) and the memory string 160. The array chip 100 further includes a plurality of Bit Lines (BL) m1 connected to the memory strings 160 over the TSG 191. The array chip 100 further includes a plurality of metal interconnection lines m2 connected to the gate electrodes through a plurality of contact structures 170. The edges of the film stack 150 are configured in a step shape to allow electrical connection to each row of gate electrodes. In addition, the array chip 100 may include other structures such as TSG cuts, common source contacts (i.e., array common sources) and dummy memory strings. For simplicity, these structures are not shown in fig. 1.
In the conventional three-dimensional memory device, the memory cells that can be provided are limited due to the limitation of the space size of the single array chip 100, and the memory density is hardly improved, but in order to improve the memory capacity, only a plurality of three-dimensional memory devices can be used, so that the use cost is high.
Referring to fig. 2, fig. 2 is a schematic cross-sectional structure of a three-dimensional memory device according to an embodiment of the present application.
The three-dimensional memory device 200 in the embodiment of the present application includes a first array structure 210, a second array structure 220, a first interconnection layer 230, and a second interconnection layer 240, where the first array structure 210 includes a first substrate 211, a first stacked layer 212 located on the first substrate 211, and a first channel 213 penetrating the first stacked layer 212 and the first substrate 211. The second array structure 220 includes a second substrate 221, a second stack layer 222 on the second substrate 221, and a second memory string 224 penetrating the second stack layer 222. The first interconnection layer 230 is located on a side of the first substrate 211 facing away from the first stack layer 212, the first interconnection layer 230 having a first bonding contact h1 electrically connected to the first via 213. The second interconnection layer 240 is located at a side of the second stack layer 222 facing away from the second substrate 221, the second interconnection layer 240 has a second bonding contact h2 electrically connected with the second memory string 224, and the first interconnection layer 230 and the second interconnection layer 240 are disposed opposite and bonded such that the first bonding contact h1 and the second bonding contact h2 are electrically connected.
Specifically, the materials of the first substrate 211 and the second substrate 221 may be Silicon, germanium, silicon-On-Insulator (SOI), or the like. The first stacked layer 212 may include an upper select gate, a plurality of control gates, which may be referred to as "word lines", a lower select gate, and a gate insulating layer (not shown) between adjacent gates, and the second stacked layer 222 is similar to the first stacked layer 212 and will not be described again.
The first interconnection layer 230 includes a first connection layer 231 and a first bonding layer 232 located on a side of the first connection layer 231 facing away from the first substrate 211, the first connection layer 231 includes a first metal line layer 2311 electrically connected to the first channel 213, and the first bonding contact h1 is located on the first bonding layer 232 and electrically connected to the first metal line layer 2311. The second interconnection layer 240 includes a second connection layer 241 and a second bonding layer 242 located on a side of the second connection layer 241 facing away from the second stack layer 222, the second connection layer 241 includes a second bit line layer 2411 electrically connected to the second memory string 224, and a second bonding contact h2 is located on the second bonding layer 242 and electrically connected to the second bit line layer 2411, and the first bonding layer 232 and the second bonding layer 242 are bonded. Wherein, the first metal line layer 2311 and the first channel 213, the first metal line layer 2311 and the first bonding contact h1, the second bit line layer 2411 and the second memory string 224, and the second bit line layer 2411 and the second bonding contact h2 are electrically connected through connection contacts (not shown).
It should be noted that, the first metal line layer 2311 includes a plurality of first metal lines arranged in parallel, the second bit line layer 2411 includes a plurality of second bit lines arranged in parallel, and the first channels 213 are plural, and each of the first channels 213 is electrically connected to one of the first metal lines and one of the second bit lines.
In addition, the first array structure 210 further includes a first bit line layer (not shown) on a side of the first stack layer 212 facing away from the first substrate 211, and the first array structure 210 should further include a first memory string 214 penetrating the first stack layer 212 in a direction perpendicular to the first substrate 211, and the first memory string 214 and the first channel 213 are electrically connected to the first bit line layer, through which a control signal is accessed. The structure of the first storage string 214 and the second storage string 224 may be referred to as the structure of the storage string 160 in fig. 1, and will not be described herein.
The three-dimensional memory device 200 may further include a driving structure 250, the driving structure 250 being located on a side of the first stacked layer 212 facing away from the first substrate 211 and bonded to the first array structure 210, thereby providing a control circuit for the three-dimensional memory device 200. The driving structure 250 may be a CMOS chip. It is easy to understand that in the actual working process, the electrical connection relationship between the driving structure 250 and the first channel 213 and the first storage string 214 may be flexibly set, for example, the same control signal may be sent to the first channel 213 and the first storage string 214, and the first storage string 214 and the second storage string 224 belong to a serial connection relationship. In this embodiment, the control of the first memory string 214 and the second memory string 224 by the driving structure 250 is independent, and the driving structure 250 may transmit the voltage signal to the first memory string 214 through the first bit line layer alone, thereby controlling the first memory string 214, and may transmit the voltage signal to the first interconnection layer 230 through the first bit line layer and to the second memory string 224 through the second interconnection layer 230, thereby controlling the second memory string 224.
Further, the first channel 213 may include a conductive channel 2131 penetrating the first stacked layer 212 and penetrating part of the first substrate 211, and a conductive portion 2132 embedded in the first substrate 211 and contacting the conductive channel 2131, the conductive portion 2132 being electrically connected with the first bonding contact h1. In general, the conductive channel 2131 may be a dummy memory string (i.e., a memory string that does not have substantial memory functionality), or an additionally fabricated TAC (Through Array Contact, through the array contacts). The conductive portion 2132 is made mainly of a metal material such as tungsten, copper, or aluminum. Preferably, the conductive portion 2132 has a trapezoidal cross section in a direction through the first stacked layer 212, the conductive channel 2131 has a rectangular cross section in a direction through the first stacked layer 212, and a critical dimension of the conductive portion 2132 is larger than a critical dimension of the conductive channel 2131, i.e., the conductive channel 2131 is located within a projection area of the conductive portion 2132. In the present application, the first channel 213 is formed by using a virtual memory string or an additional TAC, so that stacking of a plurality of array structures can be achieved without adding additional process or area and the memory string of the stacked array can be extracted, thereby increasing the memory density.
It should be noted that, in order to prevent the metal material of the conductive portion 2132 from leaking, and to pollute the metal for other processes, a dielectric layer 215 is further disposed in the first substrate 211, and the dielectric layer 215 is disposed around the conductive portion 2132 to isolate the conductive portion 2132 from the first substrate 211. The dielectric layer 215 is made of an insulating material such as a doped material including silicon nitride, silicon oxide, and silicon nitride or a doped material of silicon oxide.
In addition, the three-dimensional memory device 200 may include more array structures in addition to the driving structure 250, the first array structure 210, and the second array structure 220, so long as bonding between adjacent array structures is ensured. Referring to fig. 3, a simplified description of the structure of the three-dimensional memory device 200 will be given below by taking the addition of the third array structure 260 as an example.
Specifically, the second array structure 220 may further include a second via 223 penetrating the second stack layer 222 and the second substrate 221 in a direction perpendicular to the second substrate 221, the second via 223 being electrically connected with the second interconnection layer 230. The three-dimensional memory device 200 further includes a third array structure 260, a third interconnect layer 270, and a fourth interconnect layer 280.
The third array structure 260 includes a third substrate 261, a third stacked layer 262 on the third substrate 261, and a third memory string 264 penetrating the third stacked layer 262 in a direction perpendicular to the third substrate 261. The third interconnect layer 270 is located on a side of the second substrate 221 facing away from the second stack layer 222, the third interconnect layer 270 having a third bonding contact h3 electrically connected to the second via 223. The fourth interconnect layer 280 is located on a side of the third stack layer 262 facing away from the third substrate 261, the fourth interconnect layer 280 having a fourth bonding contact h4 electrically connected with the third storage string 264, the fourth interconnect layer 280 and the third interconnect layer 270 being oppositely disposed and bonded such that the third bonding contact h3 and the fourth bonding contact h4 are electrically connected.
It is to be understood that the second channel 223 is similar to the first channel 213, the third interconnect layer 270 is similar to the first interconnect layer 230, the fourth interconnect layer 280 is similar to the second interconnect layer 240, and the third substrate 261 is made of similar material to the first substrate 211, which is not repeated here. The fourth interconnect layer 280 is similar to the second interconnect layer 240 in structure and also has a fourth bit line layer (not shown), and the third memory string 264 is electrically connected to the fourth bit line layer.
When three array structures are stacked, signals of the driving structure 250 are transferred to the second memory string 224 through the first channel 213 and transferred to the third memory string 264 through the first channel 213 and the second channel 223, thereby realizing parallel connection of the second memory string 224 and the third memory string 264 and improving the memory density. In the above embodiment, only three array structures are shown to be stacked, it will be appreciated that more array structures may be stacked on the third array structure in the manner described above.
It should be noted that, for the existing three-dimensional memory device 200 structure only including the bonded driving structure 250 and the single array structure, in this embodiment of the present application, by stacking a plurality of array structures and transmitting signals to the memory strings in the stacked array structure through the design channel, so that a plurality of array structures may share one driving structure 250, in the actual working process, the voltage signal of the driving structure 250 may be separately transmitted to the first memory string 214 through the first bit line layer, and may also be separately transmitted to the memory strings in other array structures through the first bit line layer and the interconnection layer, so that control operations such as data writing and reading of the memory cells (memory strings) in the plurality of array structures are separately implemented, and compared with the existing structure capable of controlling only the memory cells in the single array structure, the number of the whole memory cells of the three-dimensional memory device 200 is greatly increased, and the memory density is improved.
On the basis of the above-described embodiments, the present embodiment will be further described from the viewpoint of the manufacturing method of the three-dimensional memory device 200.
Referring to fig. 4, and fig. 2 to 3, a method for manufacturing a three-dimensional memory device 200 includes the following steps:
in step S101, a first array structure 210 is provided, the first array structure 210 including a first substrate 211, a first stack layer 212 on the first substrate 211, a first memory string 214 extending through the first stack layer 212, and a first channel 213 extending through the first stack layer 212 and the first substrate 211 in a direction perpendicular to the first substrate 211.
Specifically, the material of the first substrate 211 may be Silicon, germanium, or Silicon-On-Insulator (SOI), etc. The first stacked layer 212 may include an upper select gate, a plurality of rows of control gates, which may be referred to as "word lines," a lower select gate, and a gate insulation layer between adjacent gates.
Referring to fig. 5a-5g and fig. 6, fig. 5a-5g are schematic cross-sectional views of the first array structure 210 after different process flows, wherein the first channel 213 includes a conductive channel 2131 and a conductive portion 2132, and the step S101 may specifically include steps S1011 to S1014, wherein:
step S1011 provides the first substrate 211.
Step S1012, forming a conductive portion 2132 on a side close to the first substrate 211 in the first substrate 211, see fig. 5c.
The conductive portion 2132 is made of a metal material such as tungsten, copper, or aluminum. In order to prevent the metal material of the conductive portion 2132 from leaking and polluting other materials, the first substrate 211 is further provided with a dielectric layer 215, and in this case, referring to fig. 5a to 5c, the step S1012 may specifically include:
1-1, forming a first groove C on a surface of one side of the first substrate 211, see fig. 5a;
1-2, forming a dielectric layer 215 in the first recess C, the dielectric layer 215 filling the first recess C, see fig. 5b;
1-3, a conductive portion 2132 is formed within the dielectric layer 215, see fig. 5c.
Specifically, the dielectric layer 215 is made of an insulating material, such as a doped material including silicon nitride, silicon oxide, and silicon nitride, or a doped material of silicon oxide. The recess may be formed in a channel structure region of the three-dimensional memory device 200, typically using a plasma dry etching process.
In step S1013, a first stacked layer 212 is formed on a side of the first substrate 211 facing away from the conductive portion 2132, see fig. 5d.
Step S1014, forming a conductive channel 2131 and a first memory string 214 extending through the first stacked layer 212 and to the conductive portion 2132, see fig. 5e.
In particular, the conductive channel 2131 may be a dummy memory string, or an additionally fabricated TAC.
In step S1015, a surface of the first substrate 211 facing away from the conductive portions 2132 is thinned to expose the conductive portions 2132, resulting in a first array structure 210, see fig. 5f.
In step S102, a first interconnection layer 230 is formed on a side of the first substrate 211 away from the first stacked layer 212, and the first interconnection layer 230 has a first bonding contact h1 electrically connected to the first via 213, see fig. 5g.
The first interconnection layer 230 includes a first wiring layer 231 and a first bonding layer 232 located on a side of the first wiring layer 231 facing away from the first substrate 211, the first wiring layer 231 includes a first metal line layer 2311 electrically connected to the first channel 213, and the first bonding contact h1 is located on the first bonding layer 232 and electrically connected to the first metal line layer 2311.
In step S103, a second array structure 220 is provided, where the second array structure 220 includes a second substrate 221, a second stacked layer 222 on the second substrate 221, and a second memory string 224 penetrating the second stacked layer 222 along a direction perpendicular to the second substrate 221.
The second stacked layer 222 is similar to the first stacked structure layer 212, and the second substrate 221 is similar to the first substrate 211, which are not described herein.
In step S104, a second interconnection layer 240 is formed on a side of the second stacked layer 222 facing away from the second substrate 221, where the second interconnection layer 240 has a second bonding contact h2 electrically connected to the second memory string 224.
It should be noted that the steps S101-S102 and S103-S104 may be performed synchronously or sequentially, and the execution sequence is not limited herein.
In step S105, the first interconnection layer 230 and the second interconnection layer 240 are disposed opposite to each other and bonded, so that the first bonding contact h1 and the second bonding contact h2 are electrically connected.
Wherein the three-dimensional memory device 200 further includes a first bit line layer (not shown), the first bit line layer is located on a side of the first stacked layer 212 facing away from the first substrate 211, the first memory string 214 and the first channel 213 are electrically connected to the first bit line layer, and before the first interconnection layer 230 and the second interconnection layer 240 are disposed opposite to each other and bonded, the method for fabricating the three-dimensional memory device 200 may further include:
providing a drive structure 250;
the first array structure 210 is bonded to the drive structure 250.
Wherein the control circuit may be provided for the three-dimensional memory device 200 by bonding the first array structure 210 with the driving structure 250. The driving structure 250 may be a CMOS chip.
It should be noted that, the steps S1011 to S1014 described above describe that the first channel 213 is formed before the bonding of the driving structure 250, in fact, the first channel 213 may be formed after the bonding of the driving structure 250, that is, the first stacked layer 212 is formed on the first substrate 211, then bonded with the driving structure 250, and then the first channel 213 penetrates through the first stacked layer 212 and the first substrate 211 along the direction perpendicular to the first substrate 211.
In addition, in addition to the driving structure 250, the first array structure 210 and the second array structure 220, more array structures may be stacked on the second array structure 220, such as stacking the third array structure 260, where a second channel 223 penetrating the second stacked layer 222 and the second substrate 221 along a direction perpendicular to the second substrate 221 needs to be disposed in the second array structure 220, and a third interconnect layer 270 and a fourth interconnect layer 280 need to be disposed in the third memory device 200, so as to implement bonding of the second array structure 220 and the third array structure 250, and the specific structure and manufacturing method are similar to those of the first channel 213, the first interconnect layer 230 and the second interconnect layer 240 described above, which are not repeated herein.
Unlike the prior art, the three-dimensional memory device 200 and the manufacturing method thereof provided in this embodiment are different from the prior art in that the first channel 213 penetrating the first stacked layer 212 and the first substrate 211, the first interconnection layer 230 located on the side of the first substrate 211 away from the first stacked layer 212 and having the first bonding contact h1, and the second interconnection layer 240 located on the side of the second stacked layer 222 away from the second substrate 221 and having the second bonding contact h2 are provided, and the first interconnection layer 230 and the second interconnection layer 240 are oppositely provided and bonded so that the first bonding contact h1 and the second bonding contact h2 are electrically connected, so that the bonding of the first array structure 210 and the second array structure 220 is realized, the number of memory cells of the three-dimensional memory device 200 can be effectively increased, the memory density can be better improved under the condition of low cost, and the practicality is high.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A three-dimensional memory device, comprising:
a first array structure comprising a first substrate, a first stacked layer on the first substrate, a first memory string extending through the first stacked layer, and a first channel extending through the first stacked layer and the first substrate;
a second array structure including a second substrate, a second stacked layer on the second substrate, and a second memory string penetrating the second stacked layer;
a first interconnect layer on a side of the first substrate facing away from the first stack layer, the first interconnect layer having a first bonding contact electrically connected to the first via; and
the second interconnection layer is positioned on one side of the second stacking layer, which is away from the second substrate, and is provided with a second bonding contact electrically connected with the second storage string, and the first interconnection layer and the second interconnection layer are oppositely arranged and bonded so that the first bonding contact and the second bonding contact are electrically connected;
the second interconnection layer comprises a second connecting line layer and a second bonding layer which is positioned on one side of the second connecting line layer away from the second stacking layer, the second connecting line layer comprises a second bit line layer electrically connected with the second storage string, and the second bonding contact is positioned on the second bonding layer and electrically connected with the second bit line layer.
2. The three-dimensional memory device of claim 1, wherein the first channel comprises a conductive channel extending through the first stacked layer, and a conductive portion embedded in the first substrate and in contact with the conductive channel, the conductive portion being electrically connected to the first interconnect layer; and a dielectric layer is arranged in the first substrate and surrounds the conductive part so as to isolate the conductive part from the first substrate.
3. The three-dimensional memory device of claim 2, wherein a critical dimension of the conductive portion is greater than a critical dimension of the conductive channel.
4. The three-dimensional memory device of claim 2, wherein the conductive channel is a virtual memory string.
5. The three-dimensional memory device of claim 1, wherein the first interconnect layer comprises a first wiring layer and a first bonding layer on a side of the first wiring layer facing away from the first substrate, the first wiring layer comprising a first metal line layer electrically connected to the first via, the first bonding contact being located on the first bonding layer and electrically connected to the first metal line layer; the first bonding layer and the second bonding layer are bonded.
6. The three-dimensional memory device of claim 1, wherein the second array structure further comprises a second via extending through the second stacked layer and the second substrate, the second via being electrically connected to the second interconnect layer; the three-dimensional memory device further includes:
a third interconnect layer on a side of the second substrate facing away from the second stacked layer, the third interconnect layer having a third bond contact electrically connected to the second via;
a third array structure including a third substrate, a third stacked layer on the third substrate, and a third memory string penetrating the third stacked layer;
and the fourth interconnection layer is positioned on one side of the third stacking layer, which is away from the third substrate, and is provided with a fourth bonding contact electrically connected with the third storage string, and the fourth interconnection layer and the third interconnection layer are oppositely arranged and bonded so that the third bonding contact is electrically connected with the fourth bonding contact.
7. The three-dimensional memory device of claim 1, wherein the first array structure further comprises a first bit line layer on a side of the first stack layer facing away from the first substrate, the first memory string and the first channel each being electrically connected to the first bit line layer.
8. The three-dimensional memory device of claim 1, further comprising a drive structure located on a side of the first stack layer facing away from the first substrate and bonded to the first array structure.
9. A method of fabricating a three-dimensional memory device, comprising:
providing a first array structure comprising a first substrate, a first stacked layer on the first substrate, a first memory string extending through the first stacked layer, and a first channel extending through the first stacked layer and the first substrate;
providing a second array structure comprising a second substrate, a second stacked layer on the second substrate, and a second memory string extending through the second stacked layer;
forming a first interconnection layer on one side of the first substrate away from the first stacked layer, wherein the first interconnection layer is provided with a first bonding contact electrically connected with the first channel;
forming a second interconnection layer on one side of the second stack layer away from the second substrate, wherein the second interconnection layer is provided with a second bonding contact electrically connected with the second storage string; the second interconnection layer comprises a second connecting line layer and a second bonding layer positioned on one side of the second connecting line layer away from the second stacking layer, the second connecting line layer comprises a second bit line layer electrically connected with the second storage string, and the second bonding contact is positioned on the second bonding layer and electrically connected with the second bit line layer;
and arranging and bonding the first interconnection layer and the second interconnection layer oppositely so as to electrically connect the first bonding contact and the second bonding contact.
10. The method of claim 9, wherein the first channel comprises a conductive channel and a conductive portion, and wherein the providing the first array structure comprises:
providing a first substrate;
forming a conductive portion in the first substrate near one side of the first substrate;
forming a first stacked layer on one side of the first substrate facing away from the conductive part;
forming a conductive channel and a first memory string extending through the first stacked layer and to the conductive portion;
and thinning the surface of one side of the first substrate, which is away from the conductive part, so as to expose the conductive part, thereby obtaining a first array structure.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103199A (en) * | 2018-08-07 | 2018-12-28 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN109417075A (en) * | 2018-09-20 | 2019-03-01 | 长江存储科技有限责任公司 | Multiple pileup layer three-dimensional storage part |
| CN109923668A (en) * | 2019-01-30 | 2019-06-21 | 长江存储科技有限责任公司 | Use the hybrid bonded of illusory bonding contacts |
| CN110914987A (en) * | 2019-10-17 | 2020-03-24 | 长江存储科技有限责任公司 | Three-dimensional memory device with backside isolation structure |
| CN110998844A (en) * | 2019-11-05 | 2020-04-10 | 长江存储科技有限责任公司 | Bonded three-dimensional memory device and method of forming the same |
| CN111033739A (en) * | 2019-11-05 | 2020-04-17 | 长江存储科技有限责任公司 | Bonded three-dimensional memory device and method of forming the same |
| US10741535B1 (en) * | 2019-02-14 | 2020-08-11 | Sandisk Technologies Llc | Bonded assembly containing multiple memory dies sharing peripheral circuitry on a support die and methods for making the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113161366B (en) * | 2018-06-29 | 2023-08-18 | 长江存储科技有限责任公司 | Three-dimensional memory device having stacked device chips using interposer |
| WO2020034152A1 (en) * | 2018-08-16 | 2020-02-20 | Yangtze Memory Technologies Co., Ltd. | Embedded pad structures of three-dimensional memory devices and fabrication methods thereof |
| CN110896669B (en) * | 2018-12-18 | 2021-01-26 | 长江存储科技有限责任公司 | Multi-stack three-dimensional memory device and method of forming the same |
-
2020
- 2020-09-21 CN CN202010996327.4A patent/CN111987108B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103199A (en) * | 2018-08-07 | 2018-12-28 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN109417075A (en) * | 2018-09-20 | 2019-03-01 | 长江存储科技有限责任公司 | Multiple pileup layer three-dimensional storage part |
| CN109923668A (en) * | 2019-01-30 | 2019-06-21 | 长江存储科技有限责任公司 | Use the hybrid bonded of illusory bonding contacts |
| US10741535B1 (en) * | 2019-02-14 | 2020-08-11 | Sandisk Technologies Llc | Bonded assembly containing multiple memory dies sharing peripheral circuitry on a support die and methods for making the same |
| CN110914987A (en) * | 2019-10-17 | 2020-03-24 | 长江存储科技有限责任公司 | Three-dimensional memory device with backside isolation structure |
| CN110998844A (en) * | 2019-11-05 | 2020-04-10 | 长江存储科技有限责任公司 | Bonded three-dimensional memory device and method of forming the same |
| CN111033739A (en) * | 2019-11-05 | 2020-04-17 | 长江存储科技有限责任公司 | Bonded three-dimensional memory device and method of forming the same |
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