CN111984335A - Low-power-consumption chip awakening method, circuit, chip, system and medium - Google Patents
Low-power-consumption chip awakening method, circuit, chip, system and medium Download PDFInfo
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- CN111984335A CN111984335A CN202010846584.XA CN202010846584A CN111984335A CN 111984335 A CN111984335 A CN 111984335A CN 202010846584 A CN202010846584 A CN 202010846584A CN 111984335 A CN111984335 A CN 111984335A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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Abstract
The invention provides a chip awakening method, a circuit, a chip, a system and a medium with low power consumption, which reduce the power consumption of the chip on the premise of not influencing functions, and consider the image of the preparation time of an external environment on an awakening system to ensure that the power consumption of the chip is the lowest, wherein the method comprises the following steps: setting awakening interval time and awakening adjustment time, after the time length of the awakening adjustment time is subtracted from the awakening interval time in the dormancy of the chip system, the analog module prepares to awaken the chip system, timing is carried out when the analog module prepares to awaken the chip system every time, the time spent when the analog module prepares to awaken the chip system is counted, the time spent superposition margin time of the analog module for preparing to awaken the chip system last time is used as the next awakening adjustment time, and the awakening adjustment time is continuously updated so as to reduce the awakening power consumption of the chip.
Description
Technical Field
The invention relates to the technical field of power consumption control of a control chip, in particular to a low-power chip awakening method, a low-power chip awakening circuit, a low-power chip system and a low-power chip medium.
Background
The power consumption is a very important parameter for measuring the chip, different chips with the same function are realized, the temperature of the chip is increased due to higher power consumption density, the reliability of a circuit is influenced, the service life of a device is reduced, meanwhile, higher power consumption means more battery consumption and higher use cost.
The power consumption of the low-power chip during normal operation is usually between 10 milliwatts and 100 milliwatts, the power consumption is reduced to be below 100 microwatts when the low-power chip enters the idle mode, and the power consumption is reduced to be below 1 microwatt when the low-power chip enters the power-down mode. Under the condition of meeting the application requirement, the chip is set to be in a power-down mode as much as possible, so that a large amount of power consumption can be saved, and the method has very important significance for a battery power supply system. In the power-down mode, the external voltage modulator enters a low power consumption mode, the crystal oscillator stops oscillating, and modules such as a CPU, a timer, a serial port and the like all stop working, and only external interruption continues working. Many applications require waking up the chip from a power down mode according to an accurate fixed beat, such as a timing detection circuit, bluetooth scanning, etc. The time for the chip to initiate detection or bluetooth scan from the low power mode back to the normal operating mode must be strictly accurate.
For example, chinese patent publication No. 105653279a discloses a clock system and a wake-up method for a mobile terminal, which discloses that when the main control chip is in a sleep mode, the functional chip performs timing; and when the current time reaches the preset time, the functional chip awakens the main control chip through the first control end.
However, referring to fig. 1, which shows a schematic diagram of the power consumption of the chip for detecting the precise time interval, wherein the X axis is time and the Y axis is power consumption, it can be seen that the chip is awakened once every second. Active is the normal working mode of the chip. Deep sleep is in power down mode.
In the power down mode, power consumption is very low. The slope before the Active normal operation mode indicates that a voltage modulator, a crystal oscillator and the like which stop working in the power-down mode are started in advance, and the modules must be prepared before a fixed interval to prepare for the chip to start working at a fixed time. It is clear that early activation of these modules wastes energy. Activating these modules too late may also affect the chip entering normal operation at precisely fixed intervals. Most importantly, the preparation time for starting the modules by the analog modules is influenced by external conditions such as temperature, working voltage and the like, and has large uncertainty, so that the problems existing at present are overcome, and a chip wake-up method with low power consumption is necessary.
Disclosure of Invention
In view of the above problems, the present invention provides a chip wake-up method, circuit, chip, system and medium with low power consumption, which reduces the power consumption of the chip without affecting the functions, and minimizes the power consumption of the chip by considering the image of the preparation time of the wake-up system from the external environment.
The technical scheme is as follows: a chip wake-up method with low power consumption is characterized by comprising the following steps:
setting awakening interval time and awakening adjustment time, after the time length of the awakening adjustment time is subtracted from the awakening interval time in the dormancy of the chip system, the analog module prepares to awaken the chip system, timing is carried out when the analog module prepares to awaken the chip system every time, the time spent when the analog module prepares to awaken the chip system is counted, the time spent superposition margin time of the analog module for preparing to awaken the chip system last time is used as the next awakening adjustment time, and the awakening adjustment time is continuously updated so as to reduce the awakening power consumption of the chip.
Further, the chip wake-up method with low power consumption specifically comprises the following steps:
step 1: setting a wakeup interval time T1 and a wakeup adjustment time T2;
step 2: sending the set wakeup interval time T1 and the wakeup adjustment time T2 to a first counter, wherein the first counter starts counting, and when the first counter counts to T1-T2, the analog module prepares to wake up the chip system, and meanwhile, a second counter starts counting;
and step 3: when the analog module is ready to wake up the chip system, a preparation completion signal is sent to the second counter, the time count of the second counter when the preparation completion signal is received is saved, the time is used as new wake-up adjustment time T2 after the margin time is superposed for the next counting, and the first counter continues to count until the wake-up interval time T1 is finished;
and 4, step 4: after the counting of the T1 counter is finished, waking up the chip system to enter a normal working state, and after the active time of the chip system is finished, entering a dormant state again;
and 5: and (4) repeatedly executing the step 2 to the step 4, and continuously updating the wakeup adjustment time T2 to reduce the chip wakeup power consumption.
Further, in step 1, the duration of the initial wake-up adjustment time T2 is set to be longer than the maximum time for the analog module to wake up the chipset system.
A chip wake-up circuit with low power consumption is characterized in that: the method comprises a first counter count 1 and a second counter count 2, wherein an input end of the first counter count 1 can input a wakeup interval time T1 as a counting trigger signal, an output end of the first counter is connected to an input end of an enabling module EN, an input end of the enabling module EN can also input a wakeup adjustment time T2, an output end of the enabling module EN is connected to an input end of a second counter count 2, an output end of the second counter count T2 is connected with a Latch Latch, when the first counter count 1 counts a difference value between the input wakeup interval time T1 and the wakeup adjustment time T2, the second counter count 2 starts counting, and when the Latch Latch receives a ready signal of the analog module wakeup chip system, the second counter count 2 latches a current time count to the Latch Latch, and after the margin time is added, the current time serves as a new wakeup adjustment time T2 for counting next time.
Further, the wake-up interval T1 is input to the first counter T1 through an and gate, and the other input terminal of the and gate is at a high level; the wakeup adjust time T2 is input to the enable module EN through an and gate, and the other input terminal of the and gate is at a high level.
A chip is characterized by comprising the chip wake-up circuit with low power consumption.
A chip wake-up power consumption adjustment system, comprising:
a setting module, configured to set a wake-up interval time T1 and a wake-up adjustment time T2;
the wake-up counting module is used for sending the set wake-up interval time T1 and the wake-up adjustment time T2 to the first counter, the first counter starts counting, when the first counter counts to T1-T2, the simulation module prepares to wake up the chip system, and meanwhile, the second counter starts counting;
the wake-up adjusting module is used for sending a preparation completion signal to the second counter after the analog module is ready to wake up the chip system, the time count of the second counter when the preparation completion signal is received is saved, the new wake-up adjusting time T2 is used for counting next time after margin time is superposed, and the first counter continues to count until the wake-up interval time T1 is finished;
the awakening module is used for awakening the chip system to enter a normal working state after the counting of the T1 counter is finished, and entering a dormant state again after the active time of the chip system is finished;
and the repeated execution module is used for controlling the awakening counting module, the awakening adjusting module and the awakening module and constantly updating the awakening adjusting time T2 so as to reduce the awakening power consumption of the chip.
A computer-readable storage medium characterized by: the computer-readable storage medium is configured to store a program configured to perform the above-described low-power chip wake-up method.
The chip system will enter into normal working state after wake-up interval time, therefore the low power consumption chip wake-up method of the invention, through setting wake-up interval time and wake-up adjustment time, when the chip system in sleep is after the wake-up interval time minus the duration of the wake-up adjustment time, the analog module prepares to wake-up the chip system, and the timing is carried out when the analog module prepares to wake-up the chip system every time, the time of the analog module preparing to wake-up the chip system last time is added with the margin time to obtain the next wake-up adjustment time, the wake-up adjustment time is updated continuously, the energy waste caused by the early start of the modules is avoided, so as to reduce the wake-up power consumption of the chip, in the invention, the time of the analog module preparing to wake-up the chip system last time is added with the margin time as the next wake-up adjustment, the reason for doing so is that the operating environment such as temperature can not take place the sudden change in short time to can ensure that each module of chip system is prepared to awaken to comparatively accurate control analog module at every turn, avoid starting these modules in advance and can waste the energy, also avoid starting these modules too late, cause the unable normal realization of function of chip, the preparation time's of awakening chip system influence is taken into account to the external environment comprehensively, makes the chip consumption reach minimum.
Drawings
FIG. 1 shows a schematic diagram of the power consumption of a precision time interval detection chip;
FIG. 2 is a schematic flow chart of a chip wake-up method with low power consumption according to an embodiment;
fig. 3 is a schematic diagram of a chip wake-up circuit with low power consumption in an embodiment.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the prior art, when a main control chip is in a sleep mode, a functional chip times; when the current time reaches the preset time, the functional chip wakes up the main control chip through the first control end, however, many influence factors are ignored, firstly, the chip returns to the working state from the sleep mode, a voltage modulator, a crystal oscillator and the like which stop working in the power-down mode need to be started, and the modules need to be prepared before a fixed interval so as to be ready for the chip to start working at the fixed time. It is clear that early activation of these modules wastes energy. Activating these modules too late may also affect the chip entering normal operation at precisely fixed intervals. In the prior art, the detailed consideration of saving power consumption is not provided, or energy is wasted due to the fact that the modules are started in advance, so that the power consumption of a chip is greatly increased, or the modules are started too late, so that certain functions of the chip cannot be started normally in the starting time;
secondly, the preparation time for starting the modules by the analog modules of the chip is influenced by external conditions such as temperature, working voltage and the like, and has large uncertainty, the chip system can work in a wide temperature range from-40 ℃ to 125 ℃, and in the wide working range, the preparation time for starting the modules by the analog modules of the chip can be floated and excessively conservative estimation of the temperature and voltage influence can be caused, so that energy waste can be caused, the influence can be ignored, and certain functions of the chip can not be normally started in the starting time.
In order to overcome the existing problems, the invention provides a chip awakening method with low power consumption, which mainly comprises the following steps:
setting awakening interval time and awakening adjustment time, enabling the chip system to be in dormancy in the awakening interval time and to be active after each awakening interval time, enabling the chip system to be in dormancy after the time length of the awakening adjustment time is subtracted from the awakening interval time, enabling the simulation module to prepare to awaken the chip system, timing when the simulation module prepares to awaken the chip system every time, counting the time used for the simulation module to prepare to awaken the chip system, enabling the time used for the simulation module to prepare to awaken the chip system for the last time to be used as the next awakening adjustment time, and constantly updating the awakening adjustment time to reduce the awakening power consumption of the chip.
In order to make the chip wake-up method with low power consumption of the present invention easier to implement, as shown in fig. 2, in an embodiment of the present invention, two counters, namely a first counter and a second counter, are introduced to count the set wake-up interval time T1 and the wake-up adjustment time T2, and the method specifically includes the following steps:
step 1: setting a wakeup interval time T1 and a wakeup adjustment time T2;
step 2: sending the set wakeup interval time T1 and the wakeup adjustment time T2 to a first counter, wherein the first counter starts counting, and when the first counter counts to T1-T2, the analog module prepares to wake up the chip system, and meanwhile, a second counter starts counting;
and step 3: when the analog module is ready to wake up the chip system, a preparation completion signal is sent to the second counter, the time count of the second counter when the preparation completion signal is received is saved, the time is used as new wake-up adjustment time T2 after the margin time is superposed for the next counting, and the first counter continues to count until the wake-up interval time T1 is finished;
and 4, step 4: after the counting of the T1 counter is finished, waking up the chip system to enter a normal working state, and after the active time of the chip system is finished, entering a dormant state again;
and 5: and (4) repeatedly executing the step 2 to the step 4, and continuously updating the wakeup adjustment time T2 to reduce the chip wakeup power consumption.
Because the chipset will operate in a wide temperature range from-40 degrees to 125 degrees, and to ensure that the analog modules are ready before the wake-up interval T1 counts are complete, a relatively conservative wake-up adjustment time T2 must be set to satisfy the worst case condition that the analog modules are ready before the wake-up interval T1 counts are complete, so in this embodiment, the initial wake-up adjustment time T2 is set to be longer than the maximum time the analog modules are ready to wake up the chipset.
The chip wake-up method with low power consumption in this embodiment is further described below with reference to a time axis: the first counter starts at the time count of the wakeup interval time T1 → the first counter counts to T1-T2 → the analog module prepares to wake up the system, meanwhile, the second counter starts counting → sends a ready signal to the second counter after the analog module is ready to wake up the chip system, the second counter saves the time count when the ready signal is received, the time is used as a new wake-up adjustment time T2 after the margin time is superposed → waits for the T1 counter to finish counting → the chip system enters a normal working state → the chip system enters a sleep state again → the first counter starts counting for a time of a wake-up interval T1 → the first counter counts to T1-T2 (T2 is an updated wake-up adjustment time T2) → … … and then is a continuously repeated process, and the wake-up adjustment time T2 is continuously updated to reduce the power consumption of the chip wake-up.
The low-power chip wake-up method can accelerate the start of a chip system, accelerate the operation of corresponding modules and reduce the power consumption of the chip, and the low-power chip wake-up method of the invention can accelerate the start of the chip system, accelerate the operation of the corresponding modules and reduce the power consumption of the chip by setting the wake-up interval time and the wake-up adjustment time, when the chip system is in dormancy and the wake-up interval time subtracts the duration of the wake-up adjustment time, the analog module prepares to wake up the chip system, thereby avoiding that some functions of the chip can not be normally started in the starting time, the time is counted when the analog module prepares to wake up the chip system each time, the time when the analog module prepares to wake up the chip system is counted, the time when the analog module prepares to wake up the chip system last time is superposed with the margin time to obtain the next wake-up adjustment time, the, in the invention, the time of the analog module for waking up the chip system for the last time is superposed with the margin time as the next wake-up adjustment time, the reason for doing so is that the working environment such as temperature cannot suddenly change in a short time, the time of the analog module for waking up the chip system for the last time is the next wake-up adjustment time, each time the analog module is controlled to be accurately controlled to wake up each module of the chip system for the next time, energy waste caused by starting the modules in advance is avoided, the modules are prevented from being started too late, the function of the chip cannot be normally realized, the influence of the external environment on the preparation time for waking up the chip system is comprehensively considered, and the power consumption of the chip is minimized.
In this embodiment, when the chip system is prepared to be woken up by the last analog module, the margin time overlapped together is an empirical value, and the margin time can be reasonably set according to application requirements, so that the time spent failure of the chip system prepared to be woken up by the analog module obtained last time due to too large change of temperature or voltage data is avoided, and the stability and reliability of the control wake-up process are further ensured.
As shown in fig. 3, a chip wake-up circuit with low power consumption includes a first counter count 1 and a second counter count 2, an input terminal of the first counter count 1 can input a wake-up interval time T1 as a count trigger signal, an output terminal of the first counter is connected to an input terminal of an enable module EN, the input terminal of the enable module EN can also input a wake-up adjustment time T2, an output terminal of the enable module EN is connected to an input terminal of the second counter count 2, an output terminal of the second counter count 2 is connected to a Latch, when the first counter count 1 counts a difference between the input wake-up interval time T1 and the wake-up adjustment time T2, the second counter count 2 starts counting, and when the Latch receives a ready signal analog ready for the analog module to wake-up the chip system, the second counter count 2 latches a current time to the Latch, and superposes the wake-up time T2 as a new wake-up time margin, for the next counting.
Specifically, in this embodiment, the wake-up interval T1 is input to the first counter T1 through the and gate, and the other input terminal of the and gate is at a high level; the wakeup adjust time T2 is input to the enable module EN through an and gate, and the other input terminal of the and gate is at a high level.
In an embodiment of the present invention, a chip is further provided, which includes the chip wake-up circuit with low power consumption.
Based on the same inventive concept, in an embodiment of the present invention, there is also provided a chip wake-up power consumption adjusting system, including:
a setting module, configured to set a wake-up interval time T1 and a wake-up adjustment time T2;
the wake-up counting module is used for sending the set wake-up interval time T1 and the wake-up adjustment time T2 to the first counter, the first counter starts counting, when the first counter counts to T1-T2, the simulation module prepares to wake up the chip system, and meanwhile, the second counter starts counting;
the wake-up adjusting module is used for sending a preparation completion signal to the second counter after the analog module is ready to wake up the chip system, the time count of the second counter when the preparation completion signal is received is saved, the new wake-up adjusting time T2 is used for counting next time after margin time is superposed, and the first counter continues to count until the wake-up interval time T1 is finished;
the awakening module is used for awakening the chip system to enter a normal working state after the counting of the T1 counter is finished, and entering a dormant state again after the active time of the chip system is finished;
and the repeated execution module is used for controlling the awakening counting module, the awakening adjusting module and the awakening module and constantly updating the awakening adjusting time T2 so as to reduce the awakening power consumption of the chip.
Based on the same inventive concept, embodiments of the present invention provide a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the chip wake-up method with low power consumption as described in the above embodiments.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A chip wake-up method with low power consumption is characterized by comprising the following steps:
setting awakening interval time and awakening adjustment time, after the time length of the awakening adjustment time is subtracted from the awakening interval time in the dormancy of the chip system, the analog module prepares to awaken the chip system, timing is carried out when the analog module prepares to awaken the chip system every time, the time spent when the analog module prepares to awaken the chip system is counted, the time spent superposition margin time of the analog module for preparing to awaken the chip system last time is used as the next awakening adjustment time, and the awakening adjustment time is continuously updated so as to reduce the awakening power consumption of the chip.
2. The chip wake-up method with low power consumption according to claim 1, wherein the chip wake-up method with low power consumption specifically comprises the following steps:
step 1: setting a wakeup interval time T1 and a wakeup adjustment time T2;
step 2: sending the set wakeup interval time T1 and the wakeup adjustment time T2 to a first counter, wherein the first counter starts counting, and when the first counter counts to T1-T2, the analog module prepares to wake up the chip system, and meanwhile, a second counter starts counting;
and step 3: when the analog module is ready to wake up the chip system, a preparation completion signal is sent to the second counter, the time count of the second counter when the preparation completion signal is received is saved, the time is used as new wake-up adjustment time T2 after the margin time is superposed for the next counting, and the first counter continues to count until the wake-up interval time T1 is finished;
and 4, step 4: after the counting of the T1 counter is finished, waking up the chip system to enter a normal working state, and after the active time of the chip system is finished, entering a dormant state again;
and 5: and (4) repeatedly executing the step 2 to the step 4, and continuously updating the wakeup adjustment time T2 to reduce the chip wakeup power consumption.
3. The chip wake-up method with low power consumption according to claim 2, characterized in that: in step 1, the duration of the initial wake-up adjustment time T2 is set to be longer than the maximum time for the analog module to wake up the chipset system.
4. A chip wake-up circuit with low power consumption is characterized in that: the method comprises a first counter count 1 and a second counter count 2, wherein an input end of the first counter count 1 can input a wakeup interval time T1 as a counting trigger signal, an output end of the first counter is connected to an input end of an enabling module EN, an input end of the enabling module EN can also input a wakeup adjustment time T2, an output end of the enabling module EN is connected to an input end of a second counter count 2, an output end of the second counter count T2 is connected with a Latch Latch, when the first counter count 1 counts a difference value between the input wakeup interval time T1 and the wakeup adjustment time T2, the second counter count 2 starts counting, and when the Latch Latch receives a ready signal of the analog module wakeup chip system, the second counter count 2 latches a current time count to the Latch Latch, and after the margin time is added, the current time serves as a new wakeup adjustment time T2 for counting next time.
5. The chip wake-up circuit with low power consumption according to claim 4, wherein: a counting trigger signal of the loading wake-up interval time T1 is input into a first counter T1 through an AND gate, and the other input end of the AND gate is at a high level; the wakeup adjust time T2 is input to the enable module EN through an and gate, and the other input terminal of the and gate is at a high level.
6. A chip, characterized by: comprising the low power consumption chip wake-up circuit of claim 4.
7. A chip wake-up power consumption adjustment system, comprising:
a setting module, configured to set a wake-up interval time T1 and a wake-up adjustment time T2;
the wake-up counting module is used for sending the set wake-up interval time T1 and the wake-up adjustment time T2 to the first counter, the first counter starts counting, when the first counter counts to T1-T2, the simulation module prepares to wake up the chip system, and meanwhile, the second counter starts counting;
the wake-up adjusting module is used for sending a preparation completion signal to the second counter after the analog module is ready to wake up the chip system, the time count of the second counter when the preparation completion signal is received is saved, the new wake-up adjusting time T2 is used for counting next time after margin time is superposed, and the first counter continues to count until the wake-up interval time T1 is finished;
the awakening module is used for awakening the chip system to enter a normal working state after the counting of the T1 counter is finished, and entering a dormant state again after the active time of the chip system is finished;
and the repeated execution module is used for controlling the awakening counting module, the awakening adjusting module and the awakening module and constantly updating the awakening adjusting time T2 so as to reduce the awakening power consumption of the chip.
8. A computer-readable storage medium characterized by: the computer-readable storage medium is configured to store a program configured to perform the low power chip wake-up method of claim 1.
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| CN114422881A (en) * | 2022-01-18 | 2022-04-29 | 宁波东海集团有限公司 | Low-power communication method, system, storage medium and intelligent terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114422881A (en) * | 2022-01-18 | 2022-04-29 | 宁波东海集团有限公司 | Low-power communication method, system, storage medium and intelligent terminal |
| CN114422881B (en) * | 2022-01-18 | 2023-08-25 | 宁波东海集团有限公司 | Low-power communication method, system, storage medium and intelligent terminal |
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