CN111969066A - Thin film transistor, array substrate, display panel and display device - Google Patents

Thin film transistor, array substrate, display panel and display device Download PDF

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CN111969066A
CN111969066A CN202010610483.2A CN202010610483A CN111969066A CN 111969066 A CN111969066 A CN 111969066A CN 202010610483 A CN202010610483 A CN 202010610483A CN 111969066 A CN111969066 A CN 111969066A
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electrode
thin film
film transistor
electrically connected
substrate
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CN111969066B (en
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南洋
陈宇
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Wuhu Tianma Automotive Electronics Co ltd
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Shanghai Tianma Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions

Abstract

The embodiment of the invention discloses a thin film transistor, an array substrate, a display panel and a display device. The thin film transistor comprises a substrate, a first conductive layer, a semiconductor layer and a second conductive layer, wherein the first conductive layer, the semiconductor layer and the second conductive layer are arranged on the substrate; the first conductive layer comprises a grid electrode, the second conductive layer comprises a source electrode and a drain electrode, and the first conductive layer and the second conductive layer are different layers; the grid electrode, the source electrode and the drain electrode comprise two common electrodes and a split electrode, the split electrode comprises at least two sub-electrodes which are insulated from each other, and the vertical projection of each common electrode and each sub-electrode on the substrate is overlapped with the vertical projection of the active region on the substrate. The embodiment of the invention solves the problem of power consumption waste caused by the fact that the driving capability of the existing thin film transistor cannot be changed, and can change the driving capability of the thin film transistor by realizing the switching of the width-to-length ratio, correspondingly realize the brightness control of the pixel unit and reduce the power consumption.

Description

Thin film transistor, array substrate, display panel and display device
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a thin film transistor, an array substrate, a display panel and a display device.
Background
In the conventional display device technology, the display panel is mainly divided into two mainstream technologies, namely a liquid crystal display panel and an organic light emitting display panel. The liquid crystal display panel forms an electric field capable of controlling the deflection of liquid crystal molecules by applying voltage on the pixel electrode and the common electrode, and further controls the transmission of light rays to realize the display function of the liquid crystal display panel; the organic self-luminous display panel adopts an organic electroluminescent material, and when current passes through the organic electroluminescent material, the luminescent material can emit light, so that the display function of the organic electroluminescent display panel is realized.
In the existing liquid crystal display panel or organic light emitting display panel, the pixel units are all turned on by inputting driving signals into a driving circuit, and the display brightness is controlled by the driving signals. The main composition structure of the driving circuit comprises various thin film transistors, and corresponding driving signals and output signals can be determined according to output characteristic curves of the thin film transistors, so that the brightness control of the pixel units is realized. Further, the driving capability of the thin film transistor is determined by a dimension parameter of the thin film transistor, such as a width-to-length ratio. In the driving process of the display panel, for the pixel unit with brighter brightness, the driving capability of the thin film transistor is enhanced to reduce the driving voltage, so that the power consumption of the panel is reduced. However, in the manufacturing process of the array substrate of the conventional display panel, the width-to-length ratio of the thin film transistor is fixed, and the driving capacities of the thin film transistors corresponding to different pixel units are the same, so that the driving capacity of the thin film transistor cannot be adjusted according to the brightness of the pixel of the display panel, and the waste of power consumption is caused.
Disclosure of Invention
The invention provides a thin film transistor, an array substrate, a display panel and a display device, which are used for changing the width-length ratio of the thin film transistor, realizing the switching of the driving capability of the thin film transistor, correspondingly realizing the brightness control of a pixel unit and reducing the power consumption.
In a first aspect, an embodiment of the present invention provides a thin film transistor, including a substrate, and a first conductive layer, a semiconductor layer, and a second conductive layer disposed on the substrate, where the semiconductor layer includes an active region;
the first conducting layer comprises a grid electrode, the second conducting layer comprises a source electrode and a drain electrode, and the first conducting layer and the second conducting layer are different in layer;
the grid electrode, the source electrode and the drain electrode comprise two common electrodes and one split electrode, the split electrode comprises at least two sub-electrodes which are insulated from each other, and the vertical projection of each common electrode and each sub-electrode on the substrate is overlapped with the vertical projection of the active region on the substrate.
In a second aspect, an embodiment of the present invention further provides an array substrate, including the thin film transistor according to the first aspect.
In a third aspect, an embodiment of the present invention further provides a display panel, including the array substrate according to the second aspect.
In a fourth aspect, embodiments of the present invention further provide a display device, including the display panel according to the third aspect.
According to the thin film transistor, the array substrate, the display panel and the display device provided by the embodiment of the invention, the substrate, the first conducting layer, the semiconductor layer and the second conducting layer are arranged on the substrate in the thin film transistor, the semiconductor layer comprises the active region, the first conducting layer comprises the grid electrode, the second conducting layer comprises the source electrode and the drain electrode, and the first conducting layer and the second conducting layer are arranged on different layers; the split electrode comprises at least two sub-electrodes which are insulated with each other, the vertical projection of each common electrode and each sub-electrode on the substrate is overlapped with the vertical projection of the active area on the substrate, at least two sub-thin film transistors can be correspondingly formed by utilizing the at least two sub-electrodes, and the width-length ratio of the thin film transistor formed by the at least two sub-thin film transistors is different from that of the sub-thin film transistors, so that the switching of the width-length ratio of the thin film transistor is realized, and the thin film transistor has the function of changing the driving capability. The embodiment of the invention not only can reduce the power consumption of the display panel when driving the display, but also can improve the brightness compensation precision of the display panel, improve the driving efficiency of the display panel, solve the problem of uneven brightness of the display panel and ensure the display quality.
Drawings
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view AA' of the thin film transistor of FIG. 1;
fig. 3 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present invention;
FIG. 5 is a graph of performance of thin film transistors of different aspect ratios;
FIG. 6 is a schematic cross-sectional view of a different type of TFT;
fig. 7 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of the thin film transistor of FIG. 7 taken along line BB';
fig. 9 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view of the thin film transistor of FIG. 9 taken along line CC';
fig. 11 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;
FIG. 12 is a schematic cross-sectional view DD' of the TFT of FIG. 11;
fig. 13 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 14 is a partially enlarged view of the array substrate of fig. 13;
fig. 15 is a partially enlarged view of another array substrate according to an embodiment of the present invention;
fig. 16 is a partially enlarged view of still another array substrate according to an embodiment of the present invention;
fig. 17 is a structural diagram of a pixel driving circuit of another array substrate according to an embodiment of the invention;
fig. 18 is a structural view of a pixel driving circuit of another array substrate according to an embodiment of the invention;
fig. 19 is a structural diagram of a pixel driving circuit of another array substrate according to an embodiment of the invention;
fig. 20 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention;
fig. 21 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It is to be further noted that, for the convenience of description, only a part of the structure relating to the present invention is shown in the drawings, not the whole structure.
Fig. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a cross-section of the thin film transistor shown in fig. 1 along AA', referring to fig. 1 and 2, the thin film transistor includes a substrate 10, and a first conductive layer 11, a semiconductor layer 13 and a second conductive layer 12 disposed on the substrate 10, the semiconductor layer 13 includes an active region 130; the first conductive layer 11 includes a gate electrode 21, the second conductive layer 12 includes a source electrode 22 and a drain electrode 23, the first conductive layer 11 and the second conductive layer 12 are different layers; the gate 21, the source 22 and the drain 23 include two common electrodes 31 and one split electrode 32 therein, the split electrode 32 includes at least two sub-electrodes 321 insulated from each other, and a vertical projection of each common electrode 31 and each sub-electrode 321 on the substrate 10 overlaps a vertical projection of the active region 130 on the substrate 10.
The thin film transistor is essentially an insulated gate field effect transistor and mainly comprises a conductive layer and a semiconductor layer, wherein the semiconductor forms an active region through ion doping, and a voltage is applied to an electrode in the conductive layer, so that a channel for carrier migration can be formed in the active region. Specifically, the conductive layer has a gate electrode 21, a source electrode 22 and a drain electrode 23. When a voltage is applied to the gate electrode 21, the gate voltage generates an electric field in the gate insulating layer, lines of electric force are directed from the gate electrode to the semiconductor surface, and induced charges are generated at the surface. As the gate voltage increases, carriers are formed in the semiconductor, and when a voltage is applied between the source and drain electrodes, carrier migration occursThereby achieving conduction. The characteristic curve of the thin film transistor comprises a linear region and a saturation region, and the slope of the relation curve of the conduction current and the source-drain voltage of the thin film transistor is different in different regions. As shown in fig. 1, the gate electrode 21 and the source electrode 22 are alternatively a common electrode 31, the drain electrode 23 is a split electrode 32, and the drain electrode 23 includes at least two sub-drain electrodes 231 insulated from each other. It is understood that, in the thin film transistor shown in fig. 1, the vertical projection of each common electrode 31 and each sub-electrode 321 on the substrate 10 overlaps the vertical projection of the active region 130 on the substrate 10, which essentially means that the two sub-drain electrodes 231 can form a large thin film transistor together with the source electrode 22 and the gate electrode 21; meanwhile, each of the sub-drain 231 and the source 22 and the gate 21 may form a small thin film transistor. In other words, when a voltage is applied to the gate electrode 21 and a source-drain voltage difference is applied to the source electrode 22 and any one of the sub-drain electrodes 231 at the same time, any one of the small tfts can be turned on correspondingly. When both small thin film transistors are turned on, a large thin film transistor can be formed. The width-to-length ratio of the large thin film transistor is equal to the sum of the width-to-length ratios of the two small thin film transistors, i.e., W/L ═ W1/L+W2/L。
Fig. 3 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention, and referring to fig. 3, different from the thin film transistor shown in fig. 2, in the thin film transistor shown in fig. 3, the gate electrode 21 and the drain electrode 23 are a common electrode 31, the source electrode 22 is a split electrode 32, and the source electrode 22 includes at least two sub-source electrodes 221 insulated from each other.
Similarly, in the thin film transistor shown in fig. 3, the two sub-sources 221 can form a large thin film transistor together with the gate electrode 21 and the drain electrode 23, and at the same time, each of the sub-sources 221, the drain electrode 23 and the gate electrode 21 can form a small thin film transistor. The width-to-length ratio W/L of the large thin film transistor is equal to the sum W of the width-to-length ratios of the two small thin film transistors1/L+W2/L。
Fig. 4 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention, and referring to fig. 4, unlike the thin film transistors shown in fig. 2 and fig. 3, in the thin film transistor shown in fig. 4, the source 22 and the drain 23 are the common electrode 31, the gate is a split electrode, and the gate 21 includes at least two sub-gates 211 insulated from each other.
Similarly, in the thin film transistor shown in fig. 4, two sub-gates 211 can form a large thin film transistor together with the source electrode 22 and the drain electrode 23, and at the same time, each sub-gate 211 and the source electrode 22 and the drain electrode 23 can form a small thin film transistor. The width-to-length ratio W/L of the large thin film transistor is equal to the sum W of the width-to-length ratios of the two small thin film transistors1/L+W2/L。
As can be seen from fig. 1, 3, and 4, when one of the gate, the source, or the drain is a split electrode 32 including two sub-electrodes 321, and the other two electrodes are the common electrode 31, one tft can be split into two small tfts, and a voltage can be applied to any one of the sub-electrodes to control the on or off of any one of the small tfts. Obviously, the width-length ratio of the two thin film transistors is obviously different, so that the width-length ratio of the thin film transistor can be changed.
Fig. 5 is a performance curve of thin film transistors with different aspect ratios, and referring to fig. 5, under the same gate-source driving voltage, there is a difference in output current of the thin film transistors, and the higher the aspect ratio, the larger the corresponding output current. It is understood that, when the width and length of the thin film transistor are large, the output capability thereof is stronger. The thin film transistor provided by the embodiment can realize the conversion of the width-to-length ratio, namely, the switching of different driving capacities can be correspondingly realized. Therefore, on the basis of the thin film transistor provided in this embodiment, when a display panel is manufactured and formed, for a pixel unit with higher luminance, the thin film transistor can be controlled to be switched to have stronger driving capability, that is, the driving voltage with lower power consumption is used for driving while the requirement of luminance is ensured, so that the reduction of power consumption can be realized. For the pixel unit with lower brightness, the thin film transistor can be controlled to be switched to have lower driving capability, the output requirement of the thin film transistor is low, and the influence of output change on the power consumption of the thin film transistor is small; meanwhile, the lower driving capability can properly reduce the attenuation of the active layer of the thin film transistor, reduce the performance degradation of the thin film transistor and contribute to prolonging the service life of the thin film transistor.
In addition, it should be noted that, as the thin film transistors shown in fig. 1, fig. 3 and fig. 4, the drain is only exemplarily shown to be split into two sub-drains, or the source is split into two sub-sources, or the gate is split into two sub-gates, and in actual design and arrangement, a person skilled in the art can fully increase the number of sub-electrodes to realize the on control of the small thin film transistors with the number greater than two. Based on this, it can be understood by those skilled in the art that the conventional liquid crystal display panel and organic light emitting display panel usually have the problem of uneven brightness or display standard of the pixel units due to the problems of uneven signal transmission or different attenuation of the light emitting material. For example, the moire phenomenon occurring in the display process of the conventional liquid crystal display panel is caused by the display unevenness. The existing method usually implements brightness compensation by correspondingly changing the value of the input driving signal, thereby ensuring that the brightness standard of each pixel unit is consistent. However. Because the brightness difference between the pixel units is different, the compensation driving signal value required by some pixel units is a small value. In the process of brightness compensation, the actual compensation driving signal value can only provide an integer compensation driving signal value, and the compensation precision is insufficient, so that even if brightness compensation is performed, the problem of uneven brightness is still obvious, and the display effect is poor. The thin film transistor provided by the embodiment of the invention can realize the conduction control of a plurality of small thin film transistors, so that the adjustment of the output signal value can be carried out by providing different input signals for different small thin film transistors, and the more free and accurate adjustment can be realized. Therefore, on the basis of the thin film transistor provided by the embodiment, when the display panel is prepared and formed, the brightness of the display pixels can be accurately compensated, the brightness uniformity of the display panel is ensured, and the problem of water ripple in the display process of the panel is solved.
Specifically, referring to the thin film transistor shown in fig. 3, the embodiment of the present invention performs analog verification on the input signal adjustment of the thin film transistor. Wherein, the input signals V1 and V2 are respectively provided to the two sub-sources 221 of the two small thin film transistors of the thin film transistor, and the output signal value Vs of the thin film transistor is read. When V1 is 3V and V2 is 0V, Vs is 1.3V; when V1 is 3V and V2 is 1.5V, Vs is 2.2V; when V1 is 3V and V2 is 3V, Vs is 3V. Obviously, different input signals are provided for the two sub-source electrodes of the thin film transistor, so that different output signal values can be adjusted in a matching manner, the brightness of the pixel can be adjusted accordingly, and the uniformity of the brightness of the display panel is ensured.
It should be noted that, in addition to providing different input signals to the two sub-sources for the thin film transistor shown in fig. 3, so as to modulate and accurately compensate the output signal value, the thin film transistor provided in the embodiment of the present invention may select to turn on some of the small thin film transistors and the number of the small thin film transistors, so as to adjust the aspect ratio of the thin film transistors, thereby changing the output capability of the thin film transistors, and adjust the output value by using the thin film transistors with different output capabilities, so as to compensate the luminance unevenness of the display panel.
According to the thin film transistor provided by the embodiment of the invention, the substrate, the first conducting layer, the semiconductor layer and the second conducting layer are arranged on the substrate, the semiconductor layer comprises the active region, the first conducting layer comprises the grid electrode, the second conducting layer comprises the source electrode and the drain electrode, and the first conducting layer and the second conducting layer are arranged on different layers; the split electrode comprises at least two sub-electrodes which are insulated with each other, the vertical projection of each common electrode and each sub-electrode on the substrate is overlapped with the vertical projection of the active area on the substrate, at least two sub-thin film transistors can be formed by utilizing at least two sub-electrodes correspondingly, and the width-length ratio of the thin film transistor formed by at least two sub-thin film transistors is different from that of the sub-thin film transistors, so that the switching of the width-length ratio of the thin film transistor is realized, and the thin film transistor has the function of changing the driving capability. The embodiment of the invention not only can reduce the power consumption of the display panel when driving the display, but also can improve the brightness compensation precision of the display panel, improve the driving efficiency of the display panel, solve the problem of uneven brightness of the display panel and ensure the display quality.
The thin film transistor according to the above embodiment further includes an insulating layer 14; a first conductive layer 11, an insulating layer 14, a semiconductor layer 13, and a second conductive layer 12 are sequentially provided on the substrate 10. The thin film transistor is substantially of a bottom-gate top-contact type, but of course, is only one embodiment of the present invention. It will be understood by those skilled in the art that the types of thin film transistors may be designed as bottom gate bottom contact, top gate bottom contact, and top gate top contact types in addition to the bottom gate top contact type thin film transistor. Fig. 6 is a schematic cross-sectional structure of a different type of thin film transistor, and referring to fig. 6, in particular, in a bottom gate bottom contact thin film transistor, a first conductive layer 11, an insulating layer 14, a second conductive layer 12, and a semiconductor layer 13 are sequentially disposed on a substrate 10; in the top-gate bottom-contact thin film transistor, a second conductive layer 12, a semiconductor layer 13, an insulating layer 14, and a first conductive layer 11 are sequentially disposed on a substrate 10; in the top-gate top-contact thin film transistor, a semiconductor layer 13, a second conductive layer 12, an insulating layer 14, and a first conductive layer 11 are provided in this order over a substrate 10.
In addition, in the thin film transistor provided in the embodiment of the present invention, optionally, the thin film transistor is any one of an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, a metal oxide thin film transistor, and an organic thin film transistor, and a person skilled in the art may select the thin film transistor according to actual process conditions to design and prepare a corresponding type of thin film transistor, which is not limited herein.
With continued reference to fig. 1, 3 and 4, optionally, the common electrode 31 and the split electrode 32 are projected perpendicularly on the substrate 10 in an open-loop pattern. And, optionally, the common electrode 31 and the split electrode 32 are in the form of a stripe in vertical projection on the substrate 10. Obviously, the common electrode 31 and the split electrode 32 in the open-loop pattern structure can ensure that the thin film transistor has a regular shape, or ensure that the shape of the small thin film transistor formed by splitting is more regular. Meanwhile, when the thin film transistor with the switch pattern structure is provided with the grid electrode, the source electrode and the drain electrode, the electrode signal wire is conveniently and electrically connected with the grid electrode, the source electrode and the drain electrode, and wiring is conveniently arranged.
Of course, the shape of the thin film transistor can be designed as appropriate by those skilled in the art. In particular, the perpendicular projection of the common electrode and the split electrode on the substrate can be designed as a closed-loop pattern. Wherein, optionally, the vertical projection of the common electrode and the split electrode on the substrate is in a circular ring shape or a polygonal ring shape. Another structure of the thin film transistor provided in the embodiment of the present invention is described below by taking a circular ring type as an example.
Fig. 7 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention, fig. 8 is a schematic structural diagram of a cross section of the thin film transistor shown in fig. 7 along BB', and referring to fig. 7 and 8, a vertical projection of the common electrode 31 and the split electrode on the substrate 10 is a circular ring. In the thin film transistor, the source electrode 22 and the drain electrode 23 are the common electrode 31, the gate electrode is a split electrode, and the gate electrode includes three sub-gate electrodes 211 insulated from each other.
Similarly, in the thin film transistor shown in fig. 7, three sub-gates 211 may form a large thin film transistor together with the source 22 and the drain 23, and at the same time, each sub-gate 211 and the source 22 and the drain 23 may form a small thin film transistor, and the width-to-length ratio W/L of the large thin film transistor is equal to the sum W of the width-to-length ratios of the three small thin film transistors1/L+W2/L+W3/L。
As can be seen from comparing the thin film transistors shown in fig. 1 and 7, when the splitting electrode includes a plurality of sub-electrodes in the thin film transistor, that is, when the thin film transistor is split into a plurality of small thin film transistors, the entire thin film transistor has a certain occupied area, and the overall shape of the thin film transistor has a certain influence on the occupied area. Considering the preparation and layout design of the thin film transistor, a person skilled in the art can set the thin film transistor to be in a closed loop structure such as a circular ring type, and the like, and the layout structure of the thin film transistor is compact, so that the layout and the positioning are convenient.
Fig. 9 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention, and fig. 10 is a schematic structural diagram of a cross-section of the thin film transistor along CC' shown in fig. 9, referring to fig. 9 and 10, in the thin film transistor, a vertical projection of the common electrode 31 and the split electrode on the substrate 10 is a circular ring. The gate 21 and the source 22 are a common electrode 31, the drain is a split electrode, and the drain includes three mutually insulated sub-drains 231.
Similarly, in the thin film transistor shown in fig. 9 and 10, the three sub-drains 231 may form one large thin film transistor together with the source electrode 22 and the gate electrode 21; meanwhile, each of the sub-drain 231 and the source 22 and the gate 21 may form a small thin film transistor. The width-length ratio W/L of the large thin film transistor is equal to the sum W of the width-length ratios of the three small thin film transistors1/L+W2/L+W3/L。
With continued reference to fig. 9 and 10, since the common electrode source 22 is located inside the split electrode drain, when the source 22 is led out, one end of the electrode lead-out wire 24 may be arranged to connect the source 22, so that the source 22 is led out from the break of the two adjacent sub-drains 231.
Fig. 11 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention, and fig. 12 is a schematic structural diagram of a cross-section of the thin film transistor shown in fig. 10 along line DD', and referring to fig. 11 and 12, two common electrodes 31 are disposed in the same layer, and the two common electrodes 31 include a first common electrode 311 and a second common electrode 312; the vertical projection of the first common electrode 311 on the substrate 10 surrounds the vertical projection of the second common electrode 312 on the substrate 10; the thin film transistor further includes an electrode lead-out line 24, and one end of the electrode lead-out line 24 is electrically connected to the second common electrode 312.
When the first common electrode 311 is the drain 23, the second common electrode 312 is the source 22, and the source 22 and the drain 23 are disposed in the same layer, the source 22 is surrounded by the drain 23 because the vertical projections of the source 22 and the drain 23 on the substrate 10 are circular. On the basis of the above, one skilled in the art can understand that an electrode lead-out wire can be disposed on another film layer, and one end of the electrode lead-out wire is connected with the source electrode 22, so as to lead out the source electrode 22. Optionally, referring to fig. 11 and 12, an electrode lead 24 may be disposed to electrically connect one end of the electrode lead 24 to the source 22, the electrode lead 24 and the first common electrode 311 are disposed in the same layer, the first common electrode 311 is disposed with an opening 3110, and the other end of the electrode lead 24 is led out from the opening 3110.
Based on the thin film transistor provided by the embodiment, the embodiment of the invention also provides an array substrate. Fig. 13 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and referring to fig. 13, the array substrate includes any one of the thin film transistors 100 according to the embodiment of the present invention. Since the array substrate employs the thin film transistor 100 provided in the above embodiments, the same advantages as those of the thin film transistor 100 are obtained.
Fig. 14 is a partially enlarged view of the array substrate shown in fig. 13, and referring to fig. 14, the array substrate optionally further includes a scan line 200, a data line 300, and a pixel electrode 400; the gate 21 of the thin film transistor 100 is a split electrode 32, and the source 22 and the drain 23 of the thin film transistor 100 are a common electrode 31; at least two sub-electrodes 321 of the gate electrode 21 of the thin film transistor 100 are electrically connected to one scan line 200, the source electrode 22 of the thin film transistor 100 is electrically connected to the data line 300, and the drain electrode 23 of the thin film transistor 100 is electrically connected to the pixel electrode 400.
The array substrate is used for preparing a liquid crystal display panel, wherein the pixel electrode 400 is matched with a common electrode, and an electric field can be formed to drive the deflection of liquid crystal molecules, so that the backlight transmission is controlled, and the lightening of pixels is realized. The pixel electrode 400 is electrically connected to the data line 300 through the thin film transistor 100, and receives a data signal provided from the data line 300. The thin film transistor 100 is substantially a switching transistor, and the thin film transistor 100 switches the switching under the control of the scanning signal of the scanning line 200, thereby controlling the introduction of the data signal into the pixel electrode 400. In the thin film transistor shown in the figure, the gate 21 is a split electrode 32, and the thin film transistor can be split into two small thin film transistors, and the two sub-electrodes 321 of the gate are respectively controlled. The array substrate includes two data lines 300 corresponding to each row of tfts, and the two data lines 300 are respectively connected to the two sub-electrodes 321 of the gate 21, so as to control the on/off of the two small tfts. In the process of driving the display, voltage signals are respectively applied to the two sub-electrodes 321, so that the corresponding small thin film alert tube can be controlled to be turned on, and further, the aspect ratio of the thin film transistor 100 can be adjusted, so as to adjust the input signal of the pixel unit.
Fig. 15 is a partial enlarged view of another array substrate according to an embodiment of the present invention, and referring to fig. 15, the source 22 of the thin film transistor 100 is a split electrode 32, and the gate 21 and the drain 23 of the thin film transistor 100 are a common electrode 31; the gate electrode 21 of the thin film transistor 100 is electrically connected to the scan line 200, at least two sub-electrodes 321 of the source electrode 22 of the thin film transistor 100 are electrically connected to one data line 300, and the drain electrode 23 of the thin film transistor 100 is electrically connected to the pixel electrode 400.
The thin film transistor 100 in the array substrate has the source 22 as two sub-electrodes 321, i.e., the thin film transistor 100 is split into two small thin film transistors by the two sub-electrodes 321 of the source 22. In driving the display, the value of the input signal to the data line 300 by the thin film transistor can be adjusted by supplying different data signals to the two small thin film transistors. Therefore, for the liquid crystal display panel, the input signal value can be adjusted by utilizing the characteristics of the thin film transistor on the array substrate through the matching of the data signal provided by the data line and the on-off control of the small thin film transistor, and the uniformity of the brightness of the pixel unit is ensured.
Further, on the basis of the array substrate provided in the above embodiments, a person skilled in the art may also reasonably design the layout structure of the array substrate. For example, with respect to the array substrate shown in fig. 14, an array substrate is further provided in the embodiments of the present invention. Fig. 16 is a partially enlarged view of another array substrate according to an embodiment of the present invention, and referring to fig. 16, in the array substrate, two scan lines 200 connected to a same row of pixel electrodes 400 may be disposed, one scan line 200 extends in a row direction, and the other scan line 200 extends in a column direction. Obviously, compared with the array substrate shown in fig. 14, in the array substrate shown in fig. 16, two scan lines 200 connecting the pixel electrodes 400 in the same row do not overlap with each other, and thus, there is no need to perform an insulating cross-line arrangement, so that the two scan lines 200 can be formed in the same process, which is helpful for reducing the process procedure and saving the process cost.
The array substrate is mainly used for preparing liquid crystal display panels, and various array substrates are provided for LED display panels, mini-LED display panels, micro-LED display panels and organic light-emitting display panels. In the array substrates, pixel driving circuits may be disposed to drive corresponding led, mini-led, micro-led, or OLED light emitting units. Specifically, on the basis of the thin film transistor provided by the embodiment of the present invention, the embodiment of the present invention provides the pixel driving circuit in the array substrate as described above. Fig. 17 is a structural diagram of a pixel driving circuit of another array substrate according to an embodiment of the present invention, referring to fig. 17, in which a thin film transistor 100 is a driving transistor 110, the array substrate further includes a scan line 200, a data line 300, a first power voltage line 510, a light emitting diode 600, and a second power voltage line 520; the gate 21 of the driving transistor 110 is a split electrode 32, and the source 22 and the drain 23 of the driving transistor 100 are a common electrode 31; the array substrate further includes at least two switching transistors 120; the gates 21 of the at least two switching transistors 120 are respectively connected with one scanning line 200, the sources 22 of the at least two switching transistors 120 are electrically connected with the data line 300, and the drains 23 of the at least two switching transistors 120 are electrically connected with the at least two sub-electrodes 321 of the gate 21 of the driving transistor 110 in a one-to-one correspondence manner; the source 22 of the driving transistor 110 is electrically connected to the first power voltage line 510, and the drain 23 of the driving transistor 110 is electrically connected to the anode 610 of the light emitting diode 600; the cathode 620 of the light emitting diode 600 is electrically connected to the second power voltage line 520.
In the display driving process, the scan line 200 provides scan signals to the gates 21 of the three switching transistors 120 respectively to control the three switching transistors 120 to be turned on, the data line 300 provides data signals to the sources 23 of the switching transistors 120, the three sub-electrodes 321 of the gates 21 of the driving transistors 110 respectively receive the data signals to control the three small thin film transistors in the driving transistors 110 to be turned on or off, and under the power voltage signals provided by the first power voltage line 510 and the second power voltage line 520, the driving transistors 110 are turned on to light the light emitting diodes 600 on the paths. The gate 21 of the driving transistor 110 can switch the aspect ratio of the driving transistor 110 according to the data signals input from the three sub-electrodes 321, and adjust the output current value, thereby controlling and adjusting the brightness of the light emitting diode 600.
Fig. 18 is a structural diagram of a pixel driving circuit of another array substrate according to an embodiment of the present invention, referring to fig. 18, in which a thin film transistor 100 is a driving transistor 110, the array substrate further includes a scan line 200, a data line 300, a first power voltage line 510, a light emitting diode 600, and a second power voltage line 520; the source 22 of the driving transistor 110 is a split electrode 32, and the gate 21 and the drain 23 of the driving transistor 110 are a common electrode 31; the array substrate further includes a switching transistor 120; the gate 21 of the switching transistor 120 is electrically connected to one scanning line 200, the source 22 of the switching transistor 120 is electrically connected to one data line 300, and the drain 23 of the switching transistor 120 is electrically connected to the gate 21 of the driving transistor 110; at least two sub-electrodes 321 of the source 22 of the driving transistor 110 are electrically connected to one first power voltage line 510, respectively, and the drain 23 of the driving transistor 110 is electrically connected to the anode 610 of the light emitting diode 600; the cathode 620 of the light emitting diode 600 is electrically connected to the second power voltage line 520.
In the array substrate, the source 22 of the driving transistor 110 is split into three sub-electrodes 321. During the display driving process, the scan line 200 provides a scan signal to the gate 21 of the switching transistor 120 to control the switching transistor 120 to be turned on, the data line 300 provides a data signal to the source of the switching transistor 120, and the gate 21 of the driving transistor 110 receives the data signal to control the driving transistor 110 to be turned on. Since the source 22 of the driving transistor 110 includes three sub-electrodes 321, the three sub-electrodes 321 are respectively controlled to be supplied with the first power voltage signal, so that the three small thin film transistors of the driving transistor 110 can be turned on or off, and the switching of the width-to-length ratio of the driving transistor 110 is realized. When the gate 21 of the driving transistor 110 receives a fixed data signal, the output current of the driving transistor 110 can be adjusted by controlling whether the first power voltage signal is provided to the three sub-electrodes 321, i.e., by using the width-to-length ratio conversion of the driving transistor 10, thereby realizing the lighting and brightness adjustment of the light emitting diode 600.
Fig. 19 is a structural diagram of a pixel driving circuit of another array substrate according to an embodiment of the present invention, referring to fig. 19, in which a thin film transistor 100 is a driving transistor 110, the array substrate further includes a scan line 200, a data line 300, a first power voltage line 510, a light emitting diode 600, and a second power voltage line 520; the drain 23 of the driving transistor 110 is a split electrode 32, and the gate 21 and the source 22 of the driving transistor 110 are a common electrode 31; the array substrate further includes a switching transistor 120; the gate 21 of the switching transistor 120 is electrically connected to one scanning line 200, the source 22 of the switching transistor 120 is electrically connected to one data line 300, and the drain 23 of the switching transistor 120 is electrically connected to the gate 21 of the driving transistor 110; the source 22 of the driving transistor 110 is electrically connected to the cathode 620 of the light emitting diode 600, and at least two sub-electrodes 321 of the drain 23 of the driving transistor 110 are respectively electrically connected to a second power voltage line 520; the anode 610 of the light emitting diode 600 is electrically connected to the first power voltage line 510.
In the array substrate, since the drain 23 of the driving transistor 110 includes three sub-electrodes 321, when the light emitting diode 600 is disposed, the light emitting diode 600 needs to be electrically connected to the source 22 of the driving transistor 110. Specifically, during the display driving process, the scan line 200 provides a scan signal to the gate 21 of the switching transistor 120 to control the switching transistor 120 to be turned on, the data line 300 provides a data signal to the source of the switching transistor 120, and the gate 21 of the driving transistor 110 receives the data signal to control the driving transistor 110 to be turned on. Since the drain 23 of the driving transistor 110 includes three sub-electrodes 321, and the second power voltage signals are respectively controlled to be provided to the three sub-electrodes 321, the three small thin film transistors of the driving transistor 110 can be turned on or off, so as to switch the width-to-length ratio of the driving transistor 110. When the gate 21 of the driving transistor 110 receives a fixed data signal, the current flowing through the driving transistor 110, that is, the current value flowing through the light emitting diode 600, can be adjusted by controlling whether the second power voltage signal is supplied to the three sub-electrodes 321 or not, i.e., by using the width-to-length ratio conversion of the driving transistor 10, thereby realizing the lighting and brightness adjustment of the light emitting diode 600.
In the array substrate pixel driving circuit shown in fig. 17-19, the driving transistor 110 can be alternatively configured as the thin film transistor structure shown in fig. 1-4, i.e. the vertical projection of the common electrode 31 and the split electrode 32 on the substrate 10 is in a bar shape; alternatively, the thin film transistor structure shown in fig. 7 to 12 may be alternatively configured, that is, the common electrode 31 and the split electrode 32 are in a circular or polygonal ring shape in vertical projection on the substrate 10. Further, in the array substrate, the light emitting diode may be disposed on a side of the driving transistor away from the substrate; and, the vertical projection of the driving transistor on the substrate, locate in the vertical projection of the luminescent diode on the substrate; the anode of the light emitting diode is electrically connected with the drain electrode of the driving transistor through the through hole, and the cathode of the light emitting diode is electrically connected with the second power supply voltage line through the through hole; or the source of the driving transistor is electrically connected with the cathode of the light emitting diode through the via hole, and the anode of the light emitting diode is electrically connected with the first power voltage line through the via hole.
Fig. 20 is a schematic cross-sectional structure view of an array substrate according to an embodiment of the present invention, and referring to fig. 20, for example, a thin film transistor in the array substrate is a driving transistor 110, and the driving transistor 110 is shown in fig. 7. The following explains a specific film structure of the driving transistor and the light emitting diode in the array substrate, taking the structure of the thin film transistor shown in fig. 7 as an example. The light emitting diode 600 in the array substrate is located on the side of the driving transistor 110 away from the substrate 10, and the vertical projection of the driving transistor 110 on the substrate 10 is located in the vertical projection of the light emitting diode 600 on the substrate 10. The anode 610 of the light emitting diode 600 is electrically connected to the drain 23 of the driving transistor 110 through a via hole, and the cathode 620 of the light emitting diode 600 is electrically connected to the second power voltage line 520 through a via hole.
At this time, the light emitting diode 600 is substantially located on the upper portion of the driving transistor 110, and when the light emitting diode 600 is mounted, the light emitting diode can be electrically connected to the pixel driving circuit on the array substrate through a mounting process. It should be noted that, in order to ensure the electrical connection between the electrode of the light emitting diode 600 and the pixel driving circuit on the array substrate, the shape of the anode 610 of the light emitting diode can be designed according to the shape of the driving transistor 110 in the pixel driving circuit. In the array substrate shown in fig. 20, the vertical projection of the drain of the driving transistor 110 on the substrate 10 is a circular ring, and the anode 610 of the corresponding light emitting diode 600 is a circular ring. In addition, the second power voltage line 520 may be disposed to pass through the bottom of the driving transistor 110, and may be connected to the cathode 610 of the light emitting diode 600 positioned at the upper portion of the driving transistor 110 through a via hole.
Fig. 21 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 21, the display device includes a display panel 1, and the display panel 1 includes any one of the array substrates according to the embodiments. Specifically, the display panel 1 may be a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel. The display device can be a mobile phone, a computer, an intelligent wearable device and the like.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (16)

1. A thin film transistor includes a substrate, and a first conductive layer, a semiconductor layer, and a second conductive layer provided over the substrate, the semiconductor layer including an active region;
the first conducting layer comprises a grid electrode, the second conducting layer comprises a source electrode and a drain electrode, and the first conducting layer and the second conducting layer are different in layer;
the grid electrode, the source electrode and the drain electrode comprise two common electrodes and one split electrode, the split electrode comprises at least two sub-electrodes which are insulated from each other, and the vertical projection of each common electrode and each sub-electrode on the substrate is overlapped with the vertical projection of the active region on the substrate.
2. The thin film transistor of claim 1, wherein the common electrode and the split electrode are projected vertically in a closed loop pattern on the substrate.
3. The thin film transistor according to claim 2, wherein a vertical projection of the common electrode and the split electrode on the substrate is a circular ring type or a polygonal ring type.
4. The thin film transistor according to claim 2, wherein the two common electrodes are disposed in the same layer, and the two common electrodes include a first common electrode and a second common electrode;
the vertical projection of the first common electrode on the substrate surrounds the vertical projection of the second common electrode on the substrate; the thin film transistor further comprises an electrode outgoing line, and one end of the electrode outgoing line is electrically connected with the second common electrode.
5. The thin film transistor according to claim 4, wherein the electrode lead-out line and the first common electrode are disposed on the same layer, the first common electrode is provided with an opening, and the other end of the electrode lead-out line is led out from the opening.
6. The thin film transistor of claim 1, wherein a perpendicular projection of the common electrode and the split electrode on the substrate is an open loop pattern.
7. The thin film transistor of claim 6, wherein a vertical projection of the common electrode and the split electrode on the substrate is in a stripe shape.
8. The thin film transistor according to any one of claims 1 to 7, wherein the gate electrode and the source electrode are common electrodes, the drain electrode is the split electrode, and the drain electrode comprises at least two sub-drain electrodes insulated from each other;
or the grid and the drain are common electrodes, the source is the split electrode, and the source comprises at least two sub-sources which are insulated from each other;
or the source electrode and the drain electrode are common electrodes, the gate electrode is the split electrode, and the gate electrode comprises at least two sub-gate electrodes which are insulated from each other.
9. The thin film transistor according to any one of claims 1 to 7, further comprising an insulating layer;
the first conductive layer, the insulating layer, the second conductive layer and the semiconductor layer are sequentially arranged on the substrate;
or the first conductive layer, the insulating layer, the semiconductor layer and the second conductive layer are sequentially arranged on the substrate;
or the second conductive layer, the semiconductor layer, the insulating layer and the first conductive layer are sequentially arranged on the substrate;
or, the semiconductor layer, the second conductive layer, the insulating layer, and the first conductive layer are sequentially disposed on the substrate.
10. The thin film transistor according to claim 1, wherein the thin film transistor is any one of an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, a metal oxide thin film transistor, and an organic thin film transistor.
11. An array substrate comprising the thin film transistor according to any one of claims 1 to 10.
12. The array substrate of claim 11, further comprising scan lines, data lines, and pixel electrodes;
the grid electrode of the thin film transistor is a split electrode, and the source electrode and the drain electrode of the thin film transistor are common electrodes; at least two sub-electrodes of a grid electrode of the thin film transistor are respectively electrically connected with one scanning line, a source electrode of the thin film transistor is electrically connected with the data line, and a drain electrode of the thin film transistor is electrically connected with the pixel electrode;
or the source electrode of the thin film transistor is a split electrode, and the grid electrode and the drain electrode of the thin film transistor are common electrodes; the grid electrode of the thin film transistor is electrically connected with the scanning line, at least two sub-electrodes of the source electrode of the thin film transistor are respectively electrically connected with one data line, and the drain electrode of the thin film transistor is electrically connected with the pixel electrode.
13. The array substrate of claim 11, wherein the thin film transistor is a driving transistor, the array substrate further comprising a scan line, a data line, a first power voltage line, a light emitting diode, and a second power voltage line;
the grid electrode of the driving transistor is a split electrode, and the source electrode and the drain electrode of the driving transistor are common electrodes; the array substrate further comprises at least two switch transistors; the grid electrodes of the at least two switch transistors are respectively connected with a scanning line, the source electrodes of the at least two switch transistors are electrically connected with the data line, and the drain electrodes of the at least two switch transistors are electrically connected with the at least two sub-electrodes of the grid electrode of the driving transistor in a one-to-one correspondence manner; the source electrode of the driving transistor is electrically connected with the first power supply voltage line, and the drain electrode of the driving transistor is electrically connected with the anode electrode of the light-emitting diode; the cathode of the light emitting diode is electrically connected with the second power supply voltage line;
or the source electrode of the driving transistor is a split electrode, and the grid electrode and the drain electrode of the driving transistor are common electrodes; the array substrate further comprises a switch transistor; the grid electrode of the switch transistor is electrically connected with one scanning line, the source electrode of the switch transistor is electrically connected with one data line, and the drain electrode of the switch transistor is electrically connected with the grid electrode of the driving transistor; the at least two sub-electrodes of the source electrode of the driving transistor are respectively and electrically connected with one first power supply voltage line, and the drain electrode of the driving transistor is electrically connected with the anode of the light-emitting diode; the cathode of the light emitting diode is electrically connected with the second power supply voltage line;
or the drain electrode of the driving transistor is a split electrode, and the grid electrode and the source electrode of the driving transistor are common electrodes; the array substrate further comprises a switch transistor; the grid electrode of the switch transistor is electrically connected with one scanning line, the source electrode of the switch transistor is electrically connected with one data line, and the drain electrode of the switch transistor is electrically connected with the grid electrode of the driving transistor; the source electrode of the driving transistor is electrically connected with the cathode electrode of the light emitting diode, and the at least two sub-electrodes of the drain electrode of the driving transistor are respectively electrically connected with one second power supply voltage line; and the anode of the light emitting diode is electrically connected with the first power supply voltage line.
14. The array substrate of claim 11, wherein in the driving transistor, the vertical projection of the common electrode and the split electrode on the substrate is in a shape of a bar, or the vertical projection of the common electrode and the split electrode on the substrate is in a shape of a circular ring or a polygonal ring;
the light emitting diode is positioned on one side of the driving transistor, which is far away from the substrate; and the vertical projection of the driving transistor on the substrate is positioned in the vertical projection of the light emitting diode on the substrate;
the anode of the light emitting diode is electrically connected with the drain of the driving transistor through a via hole, and the cathode of the light emitting diode is electrically connected with the second power voltage line through a via hole; or the source of the driving transistor is electrically connected with the cathode of the light emitting diode through a via hole, and the anode of the light emitting diode is electrically connected with the first power voltage line through a via hole.
15. A display panel comprising the array substrate according to any one of claims 11 to 14.
16. A display device comprising the display panel according to claim 15.
CN202010610483.2A 2020-06-29 2020-06-29 Thin film transistor, array substrate, display panel and display device Active CN111969066B (en)

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Citations (3)

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Publication number Priority date Publication date Assignee Title
US20080258138A1 (en) * 2007-04-23 2008-10-23 Samsung Electronics Co., Ltd. Thin film transistor array panel and fabricating method thereof, and flat panel display with the same
CN103489923A (en) * 2013-10-16 2014-01-01 京东方科技集团股份有限公司 Film transistor as well as manufacturing method and repairation method thereof and array substrate
CN110931504A (en) * 2019-09-17 2020-03-27 深圳市华星光电半导体显示技术有限公司 Array substrate and display panel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258138A1 (en) * 2007-04-23 2008-10-23 Samsung Electronics Co., Ltd. Thin film transistor array panel and fabricating method thereof, and flat panel display with the same
CN103489923A (en) * 2013-10-16 2014-01-01 京东方科技集团股份有限公司 Film transistor as well as manufacturing method and repairation method thereof and array substrate
CN110931504A (en) * 2019-09-17 2020-03-27 深圳市华星光电半导体显示技术有限公司 Array substrate and display panel

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