CN111968918B - Method for reducing thickness of gallium oxide substrate layer - Google Patents
Method for reducing thickness of gallium oxide substrate layer Download PDFInfo
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- CN111968918B CN111968918B CN202010874399.1A CN202010874399A CN111968918B CN 111968918 B CN111968918 B CN 111968918B CN 202010874399 A CN202010874399 A CN 202010874399A CN 111968918 B CN111968918 B CN 111968918B
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 109
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 109
- 239000000758 substrate Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000009616 inductively coupled plasma Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000012298 atmosphere Substances 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 3
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 abstract description 13
- QUCZBHXJAUTYHE-UHFFFAOYSA-N gold Chemical compound [Au].[Au] QUCZBHXJAUTYHE-UHFFFAOYSA-N 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 40
- 239000010931 gold Substances 0.000 description 34
- 239000000463 material Substances 0.000 description 23
- 239000010949 copper Substances 0.000 description 19
- 230000000694 effects Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 9
- 238000011282 treatment Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 241001354791 Baliga Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007500 overflow downdraw method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
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- 230000003746 surface roughness Effects 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
The invention provides a method for reducing the thickness of a gallium oxide substrate layer, which comprises the following steps: s1, etching the upper surface of gallium oxide; s2, sequentially growing a first metal layer and a second metal layer on the upper surfaces of the gallium oxide and the silicon wafer respectively; s3, etching the gallium oxide and the second metal layer of the silicon wafer; s4, bonding the second metal layer of the gallium oxide and the second metal layer of the silicon wafer to enable the gallium oxide to be adhered to the silicon wafer; s5, thinning the thickness of the gallium oxide adhered on the silicon wafer. The method provided by the invention can enable Ga to be bonded through gold-gold 2 O 3 The substrate layer is adhered on a large silicon wafer to realize Ga 2 O 3 The substrate layer continues to be thinned.
Description
Technical Field
The invention relates to the technical field of semiconductor material preparation, in particular to a method for reducing the thickness of a gallium oxide substrate layer.
Background
Gallium oxide is a novel ultra-wide forbidden band semiconductor material, the forbidden band width of the novel ultra-wide forbidden band semiconductor material exceeds the traditional wide forbidden band semiconductor materials such as SiC, gaN and the like, the novel ultra-wide forbidden band semiconductor material has ultra-wide forbidden band (4.8 eV) and large breakdown field intensity (8 MV/cm), the thermal stability and the chemical stability are very good, the forbidden band width and the breakdown field intensity are inferior to those of diamond, the price of the novel ultra-wide forbidden band semiconductor material is lower than that of diamond, and the novel ultra-wide forbidden band semiconductor material is an excellent substitute material for diamond in high-power and optical devices. beta-Ga 2 O 3 Under the condition of the same withstand voltage as GaN and SiC, the power device has lower on-resistance, lower power consumption and higher high temperature resistance, and can greatly save the electric energy loss when the high-voltage device works. Meanwhile, the preparation methods of gallium oxide are also rich and various, such as a guided mode method, hydride vapor phase epitaxy (Hydride Vapor Phase Epitaxy, HVPE), molecular beam epitaxy (Molecular beam epitaxy, MBE), metal-organic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD), pulse laser deposition (Pulsed Laser Deposition, PLD) and the like, and powerful support is provided for the design scheme of the device.
Self-heating effect (Self-heat Effects, SHE) has become a significant cause of device performance and reliability. In some cases with low thermal conductivity (e.g. beta-Ga 2 O 3 ) The consequences of this self-heating effect will become more severe in high power devices where the material acts as a substrate. Although the gallium oxide semiconductor material has large forbidden bandwidth (Eg-4.8 eV), high breakdown field strength (Ebr-8 MV/cm), and high Baliga quality factor (εμE) br 3 3444), low growth cost (single crystal substrate can be produced by a fusion method), and the like, is one of the preferred materials for next-generation high-voltage high-power devices (schottky barrier diode (Schottky barrier diode, SBD), metal-Oxide-semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) and solar blind ultraviolet (wavelength 200-280 nm) photodetectors. However, bulk beta-Ga 2 O 3 The crystals generally have very low thermal conductivity (10-25W/(mK)), and severe self-heating effects limit beta-Ga 2 O 3 Many practical applications of materials.
By beta-Ga 2 O 3 SBD prepared as substrate material generates 70% of heat from the substrate layer, leaving 30% from the schottky junction. Thus, ga is thinned 2 O 3 The substrate layer is a method that is effective in mitigating the self-heating effect and reducing the peak temperature inside the device. However, ga is currently thinned 2 O 3 The substrate layer is mainly directly thinned, i.e. directly against Ga by chemical mechanical polishing (Chemical Mechanical Polishing, CMP) 2 O 3 The substrate is slowly thinned. However, this method is currently only capable of converting Ga 2 O 3 The substrate is thinned to about 500 μm. If CMP thinning is continued, ga due to device and material limitations 2 O 3 The substrate is very fragile and the yield of thinning is low.
The gallium oxide material has lower heat conductivity, and the self-heating effect of the device is serious. Thicker substrates often give rise to more heat generation and thus a peak temperature rise inside the device. The prior proposal is to directly utilize CMP to Ga 2 O 3 The substrate layer is thinned, the polishing rate and the pressure intensity are reasonably controlled,ga may be added 2 O 3 The thickness of the substrate layer is reduced to about 500 mu m, and the surface roughness is about 2nm or less. But this method can only convert Ga 2 O 3 The thickness of the substrate layer is reduced to about 500 mu m, and the yield of the method is lower for less than 500 mu m, ga 2 O 3 The substrate layer is very fragile. Thus, thinner Ga cannot be obtained 2 O 3 A substrate layer, which greatly limits the versatility of gallium oxide material devices.
Disclosure of Invention
First, the technical problem to be solved
In view of the above problems, the present invention provides a method for reducing the thickness of a gallium oxide substrate layer for at least partially solving the problem that the conventional method can only convert Ga 2 O 3 The thickness of the substrate layer is reduced to about 500 mu m, and the method has low yield and Ga for less than 500 mu m 2 O 3 The substrate layer is very easy to crack and the like.
(II) technical scheme
The invention provides a method for reducing the thickness of a gallium oxide substrate layer, which comprises the following steps: s1, etching the upper surface of gallium oxide; s2, sequentially growing a first metal layer and a second metal layer on the upper surfaces of the gallium oxide and the silicon wafer respectively; s3, etching the gallium oxide and the second metal layer of the silicon wafer; s4, bonding the second metal layer of the gallium oxide and the second metal layer of the silicon wafer to enable the gallium oxide to be adhered to the silicon wafer; s5, thinning the thickness of the gallium oxide adhered on the silicon wafer.
Further, in S2, the first metal layer is Ti, and the second metal layer is Au or Cu.
Further, in S1, the upper surface of the gallium oxide is etched by using an inductively coupled plasma method, wherein O2 is used as an etching gas.
Further, S2 further includes, before: and S201, annealing the gallium oxide.
Further, in S201, the gallium oxide is annealed in an N2 atmosphere by rapid thermal processing.
Further, the thickness of the second metal layer grown in S2 is 200-1000nm.
Further, the bonding temperature in S4 is 300-600 ℃.
Further, in S3, the gallium oxide and the second metal layer of the silicon wafer are etched by using an inductively coupled plasma method, wherein Ar is used as an etching gas.
Further, the thickness of Ti grown in S2 is 40-200nm, and the thickness ratio of Ti to Au is about 1:3-1:6.
Further, the bonding pressure of the second metal layer of gallium oxide and the second metal layer of the silicon wafer in the step S4 is 80-200mbar, and the bonding time is 45-80min.
(III) beneficial effects
The method for reducing the thickness of the gallium oxide substrate layer provided by the embodiment of the invention utilizes gold-gold bonding to bond Ga 2 O 3 The substrate layer is adhered to a larger substrate silicon wafer; since silicon wafer is used as a larger substrate, ga is smaller than 500 mu m 2 O 3 Ga when the substrate layer is continuously thinned 2 O 3 The substrate layer is no longer susceptible to chipping.
Drawings
FIG. 1 schematically illustrates a flow chart of a method of reducing the thickness of a gallium oxide substrate layer according to an embodiment of the invention;
FIG. 2A schematically illustrates a schematic diagram of preparing gallium oxide and silicon wafers to reduce the thickness of a gallium oxide substrate layer according to an embodiment of the invention;
FIG. 2B schematically illustrates a schematic diagram of an etching process of a gallium oxide upper surface using ICP for reducing the thickness of a gallium oxide substrate layer according to an embodiment of the invention;
FIG. 2C schematically illustrates a schematic view of reducing the thickness of a gallium oxide substrate layer to grow Ti and Au on the upper surface of gallium oxide and the upper surface of a silicon wafer, respectively, in accordance with an embodiment of the invention;
FIG. 2D schematically illustrates a schematic diagram of reducing the thickness of a gallium oxide substrate layer versus etching an inert gas on the upper surface of gallium oxide, according to an embodiment of the invention;
FIG. 2E schematically illustrates a schematic view of the upper surface of gallium oxide and the upper surface of a silicon wafer bonded together with reduced thickness of the gallium oxide substrate layer according to an embodiment of the invention;
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
An embodiment of the present invention provides a method for reducing a thickness of a gallium oxide substrate layer, referring to fig. 1, including:
s1, etching the upper surface of gallium oxide;
and the upper surface of the gallium oxide is etched by utilizing ICP, so that the temperature of the subsequent bonding step can be reduced by etching, and the bonding success rate is improved.
S2, sequentially growing a first metal layer and a second metal layer on the upper surfaces of the gallium oxide and the silicon wafer respectively;
two layers of metal are grown together, wherein the first metal layer is positioned between the gallium oxide and the second metal layer, and the metal layer is required to ensure that the contact with the gallium oxide material is ohmic contact and also has better adhesiveness, so that the first metal layer is optionally provided with Ti metal; the second metal layer needs to have better ductility to meet the bonding process requirements, and thus Au and Cu are optional, with Au being the most ductile of the common metals.
S3, etching the gallium oxide and the second metal layer of the silicon wafer;
before bonding, some activation treatments are carried out on the upper surface of gallium oxide and the upper surface of a silicon wafer, which is favorable for cleaning the surface to improve bonding quality, and simultaneously, the Au surface is activated to reduce bonding temperature.
S4, bonding the second metal layer of the gallium oxide and the second metal layer of the silicon wafer to enable the gallium oxide to be adhered to the silicon wafer;
gallium oxide material is adhered to the silicon substrate by gold-gold bonding.
S5, thinning the thickness of the gallium oxide adhered to the silicon wafer;
the upper surface of the gallium oxide and the silicon wafer are adhered together, and the upper surface of the gallium oxide is changed to the lower surface due to the adhesion operation position, so that the thickness of the upper surface (the original lower surface) of the gallium oxide adhered to the silicon wafer is thinned by utilizing CMP, and after bonding, the gallium oxide substrate is not easily broken when the silicon wafer with a large substrate is continuously thinned.
On the basis of the above embodiment, in S2, the first metal layer is Ti, and the second metal layer is Au or Cu.
Ti and Au are sequentially grown on the upper surface of gallium oxide and the upper surface of a silicon wafer by utilizing a magnetron sputtering method, and metal Ti is selected because the adhesion between Ti and gallium oxide is good, and secondly, the work function of Ti is 4.33eV, and the contact with gallium oxide materials is ohmic contact; the metal Au is chosen because Au has good ductility, and the material Cu is a good choice in addition to Au. The thermal conductivity of the copper sheet is about 380W/(m.long), which is slightly higher than that of Au and lower in cost. However, since Cu is easily oxidized, a thick Cu layer (1 μm or more) needs to be grown to reduce the bonding temperature to prevent oxidation of Cu.
Based on the above embodiment, in S1, the upper surface of gallium oxide is etched by using an inductively coupled plasma method, where O is used 2 As an etching gas.
In the ICP etching treatment of gallium oxide, oxygen ions are mainly used for bombarding the upper surface of the gallium oxide substrate, so that the adhesiveness between Ti and the gallium oxide substrate layer which are grown by magnetic control at the back is improved, the falling-off between the Ti and the gallium oxide is prevented, and the bonding power can be improved.
On the basis of the above embodiment, S2 further includes, before: s201, annealing treatment is carried out on gallium oxide.
The annealing step can improve ohmic contact between gallium oxide and Ti/Au electrode to form beta-Ga 2 O 3 As the ohmic electrode is prepared in advance, the SBD prepared by the substrate material only needs to continuously finish the Schottky electrode in the follow-up process.
On the basis of the above embodiment, rapid thermal processing is used in S201 for N 2 And annealing the gallium oxide in atmosphere.
The rapid heat treatment is a heat treatment mode with very rapid heating speed and very short heat preservation time, and is commonly used for simple annealing treatment. The annealing treatment can be performed by rapid heatingProcessing at N 2 Annealing is carried out in atmosphere, taking the equipment of rapid heat treatment of Quaif low therm, jetFirst 200 as an example, the specific process comprises 1) placing a sample and vacuumizing to isolate the influence of air on the experiment; 2) N-filled 2 The temperature of the gas is increased to 470 ℃ from the ambient temperature, and the temperature is controlled to be below 10 ℃ per second due to the limitation of equipment, so the temperature-increasing time is set to be 60 seconds; 3) Ensure that the sample is N at 470 DEG C 2 30s under the gas environment; 4) Cooling to ambient temperature, breaking vacuum and taking out the sample.
On the basis of the above embodiment, the thickness of the second metal layer grown in S2 is 200-1000nm.
The second metal layer is Au or Cu, and when Ti/Au grows on the surfaces of gallium oxide and silicon wafers, the thickness of the Au is most suitable for 200-1000nm. If the Au layer is too thin, the bonding surface is more in gaps and bubbles after bonding; if the Au layer is too thick, it is not cost-effective. Through testing, the thickness of the Au layer is optimal in the range; when Ti/Cu grows on the surfaces of gallium oxide and silicon wafers, the thickness of Cu is most suitable to be 1-3 mu m, and the bonding effect is good within the thickness range, and bubbles and gaps are fewer. Since Cu is easily oxidized, a very thick Cu layer (1 μm or more) needs to be grown to reduce the temperature at the time of bonding to prevent Cu from being oxidized.
On the basis of the embodiment, the bonding temperature of the Au surface of gallium oxide and the Au surface of the silicon wafer in the S4 is 300-600 ℃, and the bonding temperature of the Cu surface of gallium oxide and the Cu surface of the silicon wafer is 100-250 ℃.
Because the thermal expansion coefficients of gallium oxide, gold and silicon chip are inconsistent, too high a temperature can generate great thermal stress, and too low a temperature requires longer time to ensure the bonding effect, so that the bonding effect is not lost in terms of time cost. Thus, the bonding temperature is a key parameter for bonding.
On the basis of the above embodiment, in S3, the second metal layer of the silicon wafer and gallium oxide are etched by using an inductively coupled plasma method, wherein Ar is used as an etching gas.
Ar treatment is carried out on the Au surface before bonding, which is favorable for cleaning the surface and improving bonding quality, and simultaneously, the Au surface is activated and bonding temperature is reduced.
On the basis of the above embodiment, the thickness of Ti grown in S2 is 40-200nm, and the ratio of Ti to Au is about 1:3-1:6.
When Ti/Au is grown on the surfaces of gallium oxide and silicon wafers, the thickness of Ti is most suitable at 40-200 nm. If the Ti layer is thin, the adhesion is poor, the metal layer is liable to fall off, and the bonding fails. It was tested that the ratio of the thicknesses of the Ti layer and the Au layer was about 1:5 for best results, and therefore the Ti layer was best within this range.
On the basis of the embodiment, the bonding pressure of the second metal layer of gallium oxide and the second metal layer of the silicon wafer is 800-2000mbar, and the bonding time is 45-90min.
When Ti/Au grows on the surfaces of the gallium oxide and the silicon wafer, the bonding pressure between the Au surface of the gallium oxide in S4 and the Au surface of the silicon wafer is 800-2000mbar, and the bonding time is 45-80min; when Ti/Cu is grown on the surfaces of gallium oxide and silicon chips, the bonding pressure between the Cu surface of gallium oxide and the Cu surface of the silicon chips is 1000-2000mbar, and the bonding time is 60-90min.
In the bonding pressure and time range, the internal bubbles and gaps in the bonding layer are minimum, and the bonding quality is best.
A detailed method of reducing the thickness of the gallium oxide substrate layer is described below in one specific embodiment.
(1) Preparing high-quality monocrystalline gallium oxide and a silicon wafer, and respectively ultrasonically cleaning the high-quality monocrystalline gallium oxide and the silicon wafer for 3 minutes by using acetone, isopropanol and deionized water in sequence; please refer to fig. 2A.
(2) Etching the upper surface of gallium oxide by ICP, etching gas O 2 The gas flow is 40sccm for 30s; please refer to fig. 2B.
(3) Ti (50 nm) and Au (200 nm) are respectively grown on the upper surface of gallium oxide and the upper surface of a silicon wafer by using a magnetron sputtering method, and after the growth is finished, the gallium oxide is subjected to 470 ℃ for 30s and N by using RTP 2 Atmosphere annealing; please refer to fig. 2C.
(4) Before bonding, performing some activation treatment on the upper surface of gallium oxide and the upper surface of a silicon wafer, and selecting Ar (Ar) by using an ICP (inductively coupled plasma) etching machine, wherein the gas flow is 40sccm, and the time is 15s; please refer to fig. 2D.
(5) Bonding the upper surface of gallium oxide and the upper surface of a silicon wafer together, and adhering a gallium oxide material on a silicon substrate by gold-gold bonding by a wafer bonding machine, wherein the bonding temperature is 380 ℃, the pressure is 100mbar, and the time is 60min; please refer to fig. 2E.
(6) And carrying out CMP thickness reduction on the gallium oxide adhered on the silicon wafer.
The present embodiment is directed to a gallium oxide schottky barrier diode, which has the same effect on other devices using gallium oxide materials as the substrate. The thickness of Au growth before bonding, the temperature and pressure during bonding and the bonding time are all four parameters, the value of one parameter is arbitrarily increased, and the values of the other three parameters can be properly reduced. Au thickness 200nm, bonding temperature 380 ℃, bonding pressure 100mbar and bonding time 60min are just one set of suitable parameters provided in this example. If the device is high temperature resistant, the bonding pressure can be properly increased to 200mbar under the condition that the Au thickness is 200nm, so that the bonding time can be shortened to 30 min.
The invention utilizes gold-gold bonding to bond Ga 2 O 3 The substrate layer adheres to a larger substrate silicon wafer. Since there is a silicon wafer as a larger substrate. Thus, the content of Ga is 500 μm or less 2 O 3 Ga when the substrate layer is continuously thinned 2 O 3 The substrate layer is no longer susceptible to chipping. Thereby Ga having a thickness of less than 500 μm can be obtained 2 O 3 Substrate layer and SBD device with good heat dissipation performance prepared based on the substrate layer
While the foregoing is directed to embodiments of the present invention, other and further details of the invention may be had by the present invention, it should be understood that the foregoing description is merely illustrative of the present invention and that no limitations are intended to the scope of the invention, except insofar as modifications, equivalents, improvements or modifications are within the spirit and principles of the invention.
Claims (7)
1. A method of reducing the thickness of a gallium oxide substrate layer, comprising:
s1, etching the upper surface of gallium oxide;
s2, sequentially growing a first metal layer and a second metal layer on the upper surfaces of the gallium oxide and the substrate silicon wafer respectively; the first metal layer is Ti, and the second metal layer is Au or Cu; the thickness of the first metal layer is 40-200nm; the thickness of the second metal layer is 200-1000nm; the thickness ratio of the first metal layer to the second metal layer is 1:3-1:6;
s3, etching the gallium oxide and the second metal layer of the substrate silicon wafer;
s4, bonding the second metal layer of the gallium oxide and the second metal layer of the substrate silicon wafer to enable the gallium oxide to be adhered to the substrate silicon wafer;
s5, thinning the thickness of the gallium oxide adhered to the substrate silicon wafer; after bonding, the gallium oxide is not easy to crack when being thinned due to the existence of the substrate silicon wafer.
2. The method for reducing thickness of gallium oxide substrate layer as defined in claim 1, wherein in S1, the upper surface of gallium oxide is etched by using an inductively coupled plasma method, wherein O is used 2 As an etching gas.
3. The method of reducing the thickness of a gallium oxide substrate layer according to claim 1, wherein prior to S2, further comprising:
and S201, annealing the gallium oxide.
4. A method for reducing thickness of a gallium oxide substrate layer according to claim 3, wherein said rapid thermal processing is used in S201 in N 2 And annealing the gallium oxide in atmosphere.
5. The method of reducing the thickness of a gallium oxide substrate layer according to claim 1, wherein the bonding temperature in S4 is 300-600 ℃.
6. The method of claim 1, wherein in S3, the second metal layer of the silicon wafer and the gallium oxide are etched by using an inductively coupled plasma method, wherein Ar is used as an etching gas.
7. The method of reducing the thickness of a gallium oxide substrate layer according to claim 2, wherein the bonding pressure between the second metal layer of gallium oxide and the second metal layer of the silicon wafer in S4 is 80-200mbar and the bonding time is 45-90mmin.
Priority Applications (1)
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