CN111968696A - Read-only memory circuit and design method thereof, read-only memory and electronic equipment - Google Patents
Read-only memory circuit and design method thereof, read-only memory and electronic equipment Download PDFInfo
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- CN111968696A CN111968696A CN202010882767.7A CN202010882767A CN111968696A CN 111968696 A CN111968696 A CN 111968696A CN 202010882767 A CN202010882767 A CN 202010882767A CN 111968696 A CN111968696 A CN 111968696A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
- G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series
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Abstract
The application relates to a read-only memory circuit and a design method thereof, a read-only memory and an electronic device, and belongs to the technical field of storage. The method for designing the read-only memory circuit comprises the following steps: designing the row number of the cell array according to the repetition condition of M row codes to be stored, so that the row number of the cell array is the same as the row number N of the M row codes after the repetition codes are removed, wherein each row code in the M row codes corresponds to a unique read address; the logic circuit in the read word line driving circuit is designed according to the repetition condition of M rows of codes, so that pre-decoding signals corresponding to different read addresses for reading the same code are all connected to the same logic circuit, and finally, only one read word line signal pointing to the same row of unit arrays for storing the same code is output, so that the read word line driving circuit only comprises N paths of logic circuits. In the embodiment of the application, the circuit is simplified according to the repeatability of the code, and the redundant circuit is removed, so that the circuit area and the power consumption are reduced.
Description
Technical Field
The application belongs to the technical field of storage, and particularly relates to a read-only memory circuit, a design method thereof, a read-only memory and an electronic device.
Background
A Read Only Memory (ROM) circuit, which mainly includes a cell array, a decoding circuit, a Read word line driving circuit, and the like. The cell array is used to store a code such as "0101 …", for example, a code such as 16 lines "0101 …" requires a cell array of 16 lines, and 16 Read Word Line signals (RWL) are correspondingly required. Taking the example of storing 16 lines of codes (each line of codes corresponds to a unique read address), the corresponding conventional ROM circuit architecture is shown in fig. 1, and includes a decoding circuit, a 16-line cell array, and a read wordline driver circuit including 16 logic circuits (the read circuit and the control circuit are omitted). Since there may be duplicate codes in the codes stored in the ROM, the description will be given by taking the code duplication of the 0 th line and the 1 st line as an example, as shown in the upper left part of the code in fig. 1. Although two lines of codes are repeated in the 16 lines of codes, the conventional ROM circuit stores the 16 lines of codes respectively by using the 16 lines of cell arrays, and accordingly, 16-way logic circuits are required for outputting 16 Read Word Line signals (RWL), which results in a waste of area and power consumption of the circuit.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a rom circuit, a design method thereof, a rom, and an electronic device, so as to solve the problems of large circuit area and waste in power consumption caused by circuit redundancy due to code duplication in the existing rom circuit.
The embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a method for designing a read only memory circuit, including: designing the row number of a unit array according to the repetition condition of M rows of codes to be stored, so that the row number of the unit array is the same as the row number N of the M rows of codes after the repetition codes are removed, wherein each row of codes in the M rows of codes corresponds to a unique read address, N, M is a positive integer, and M is larger than N; and designing a logic circuit in the read word line driving circuit according to the repetition condition of the M rows of codes, so that pre-decoding signals corresponding to different read addresses for reading the same code are all connected to the same logic circuit, and finally, only one read word line signal pointing to the same row of unit arrays for storing the same code is output, so that the read word line driving circuit only comprises N logic circuits. In the embodiment of the application, the circuit is simplified according to the repeatability of the code, so that only N rows of unit arrays are needed for storing M rows of codes, and only N paths of logic circuits in the word line reading driving circuit are needed correspondingly, so that M reading word lines are simplified to N, redundant circuits are removed, and the circuit area and the power consumption are reduced.
In combination with a possible implementation manner of the embodiment of the first aspect, the precoding signal includes: a high address predecode signal and a low address predecode signal; designing a logic circuit in a read word line driving circuit according to the repetition condition of the M rows of codes, wherein the logic circuit comprises: for each kind of repeated codes, according to a high-order address predecoding signal and a low-order address predecoding signal corresponding to each row for reading the repeated codes, an OR gate and an AND gate are combined to obtain a final logic circuit, the logic circuit enables predecoding signals corresponding to different reading addresses for reading the same codes to be connected to the logic circuit, and finally only one reading word line signal pointing to the same row unit array for storing the same codes is output. In the embodiment of the application, for the logic circuit with the repeated codes, the final logic circuit is obtained by combining the OR gate and the AND gate, so that the pre-decoding signals corresponding to different reading addresses for reading the same codes are all connected to the logic circuit, and finally, only one reading word line signal pointing to the same row of unit arrays for storing the same codes is output, so that a plurality of reading word lines are simplified to one, the same function as that of the traditional ROM circuit is realized, the area and the power consumption of the storage circuit are reduced, and the complexity of circuit design is not increased.
With reference to a possible implementation manner of the embodiment of the first aspect, according to reading the high address predecoding signal and the low address predecoding signal corresponding to each row of the repeated code, the final logic circuit is obtained by combining an or gate and an and gate, and includes: if the high address pre-decoding signals corresponding to each row in the repeated code are the same and the low address pre-decoding signals are different, the low address pre-decoding signals corresponding to each row are OR-ed by using an OR gate, and the output of the OR gate is AND-ed with the high address pre-decoding signals to obtain a final logic circuit. In the embodiment of the application, if the high-order address pre-decoding signals corresponding to each row in the repeated code are the same and the low-order address pre-decoding signals are different, the low-order address pre-decoding signals corresponding to each row are subjected to phase OR by using an OR gate, and then the output of the OR gate is subjected to phase AND with the high-order address pre-decoding signals, so that a final logic circuit can be obtained, the same function as that of a traditional ROM circuit can be realized, and the complexity and the redundant cost of circuit design can not be increased.
With reference to a possible implementation manner of the embodiment of the first aspect, according to reading the high address predecoding signal and the low address predecoding signal corresponding to each row of the repeated code, the final logic circuit is obtained by combining an or gate and an and gate, and includes: if the high-order address pre-decoding signals corresponding to each row in the repeated code are different and the low-order address pre-decoding signals are the same, the high-order address pre-decoding signals corresponding to each row are OR-ed by an OR gate, and the output of the OR gate is AND-ed with the low-order address pre-decoding signals to obtain a final logic circuit. In the embodiment of the application, if the high-order address pre-decoding signals corresponding to each row in the repeated code are different and the low-order address pre-decoding signals are the same, the high-order address pre-decoding signals corresponding to each row are subjected to phase OR by using an OR gate, and then the output of the OR gate is subjected to phase AND with the low-order address pre-decoding signals, so that a final logic circuit can be obtained, the same function as that of a traditional ROM circuit can be realized, and the complexity and the redundant cost of circuit design can not be increased.
With reference to a possible implementation manner of the embodiment of the first aspect, according to reading the high address predecoding signal and the low address predecoding signal corresponding to each row of the repeated code, the final logic circuit is obtained by combining an or gate and an and gate, and includes: if the high-order address pre-decoding signals corresponding to each row in the repeated code are different and the low-order address pre-decoding signals are different, the high-order address pre-decoding signals and the low-order address pre-decoding signals in the same row are subjected to AND operation by an AND gate, and the AND gates in each row are subjected to OR operation by an OR gate to obtain a final logic circuit. In the embodiment of the application, if the high-order address pre-decoding signals corresponding to each row in the repeated code are different and the low-order address pre-decoding signals are different, the high-order address pre-decoding signals and the low-order address pre-decoding signals in the same row are subjected to phase-AND operation by using an AND gate, and then the AND gates in each row are subjected to phase-OR operation by using an OR gate, so that a final logic circuit can be obtained, the same function as that of a traditional ROM circuit can be realized, and the complexity and the redundant cost of circuit design can not be increased.
In a second aspect, an embodiment of the present application further provides a read only memory circuit, including: n unit arrays, a decoding circuit and a read word line driving circuit; the N unit arrays are used for storing N lines of codes, the N lines of codes are obtained by removing repeated codes from M lines of codes, each line of codes in the M lines of codes corresponds to a unique read address, N, M is a positive integer, and M is larger than N; the decoding circuit is used for outputting a pre-decoding signal for selecting the corresponding unit array according to the read address of the input M-row code; the read word line driving circuit is used for outputting a read word line signal for selecting the corresponding cell array according to the pre-decoding signal; the read word line driving circuit includes: n logic circuits in one-to-one correspondence with the N cell arrays, wherein there is at least one logic circuit: the input end of the logic circuit is connected with the predecoding signals corresponding to different reading addresses for reading the same code, and the output end of the logic circuit is connected with the unit array for storing the same code.
In combination with one possible implementation manner of the embodiment of the second aspect, the logic circuit includes: the circuit is formed by combining an OR gate and an AND gate.
In combination with one possible implementation manner of the embodiment of the second aspect, the pre-decoded signal includes: a high address predecode signal and a low address predecode signal; if the high address pre-decoding signals corresponding to each row in the repeated codes corresponding to the logic circuit are the same, and the low address pre-decoding signals are different, the input end of the OR gate in the logic circuit is the low address pre-decoding signals corresponding to each row, the input of the AND gate is the output of the OR gate and the high address pre-decoding signals, and the output of the AND gate is connected with the unit array for storing the same codes.
In combination with one possible implementation manner of the embodiment of the second aspect, the pre-decoded signal includes: a high address predecode signal and a low address predecode signal; if the high-order address pre-decoding signals corresponding to each row in the repeated codes corresponding to the logic circuit are different and the low-order address pre-decoding signals are the same, the input end of an OR gate in the logic circuit is the high-order address pre-decoding signals of each row, the input end of the AND gate is the output of the OR gate and the low-order address pre-decoding signals, and the output of the AND gate is connected with a unit array for storing the same codes.
In combination with one possible implementation manner of the embodiment of the second aspect, the pre-decoded signal includes: a high address predecode signal and a low address predecode signal; if the high address pre-decoding signals corresponding to each row in the repeated codes corresponding to the logic circuit are different, and the low address pre-decoding signals are different, the input of the AND gate in the logic circuit is the high address pre-decoding signal and the low address pre-decoding signal of the same row, the input of the OR gate is the output of the AND gate of each row, and the output of the OR gate is connected with the unit array for storing the same codes.
In a third aspect, an embodiment of the present application further provides a read only memory, which includes a control circuit, a sensing circuit, and the read only memory circuit provided in the embodiment of the second aspect and/or in combination with any possible implementation manner of the embodiment of the second aspect, where the control circuit is connected to a decoding circuit in the read only memory circuit, and the sensing circuit is connected to each row of cell arrays in the read only memory circuit.
In a fourth aspect, an embodiment of the present application further provides an electronic device, which includes a body and the read-only memory provided in the embodiment of the third aspect.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.
FIG. 1 is a diagram of a conventional ROM circuit architecture.
Fig. 2 is a schematic flowchart illustrating a method for designing a rom circuit according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram illustrating an architecture of a simplified rom circuit according to an embodiment of the present disclosure.
FIG. 4 is a schematic diagram illustrating an architecture of a simplified ROM circuit according to an embodiment of the present application.
FIG. 5 is a schematic diagram illustrating an architecture of a simplified ROM circuit according to an embodiment of the present application.
FIG. 6 is a schematic diagram illustrating an architecture of a simplified ROM circuit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.
Taking the traditional ROM circuit architecture for storing 16 lines of codes shown in FIG. 1 as an example, 4-Bit addresses (ADR <0> -ADR <3>) of the decoding circuit are input, wherein the lower two-Bit addresses ADR <0> and ADR <1> are input into a 2-4 decoder (LSB, wherein the LSB is short for a Least symmetric Bit), and YL <0> -YL <3> are output; the upper two-Bit address ADR <3>, ADR <4> is inputted into the 2-4 decoder (MSB, where MSB is short for Most Significant Bit), and outputted YH <0> to YH <3 >. Signals YL <0> YL <3> and YH <0> YH <3> are input to input terminals of 16 two-input AND gates of the read word line driving circuit, respectively, so that 16 read word lines (RWL0 RWL15) are output to control reading of the cell array of 16 rows, respectively. The relationship between the address signals ADR <3:0> and the selected RWL is shown in the lower left table of FIG. 1. When the 4-bit address (ADR <0> -ADR <3>) is "0000", YL <0> outputted from the 2-4 decoder is 1, YH <0> is 1 (wherein, the correspondence between the upper address pre-decode signal and the lower address pre-decode signal corresponding to different read addresses is shown in Table 1), and the corresponding YL <0> and YH <0> phases are outputted, and then the read word line RWL0 is 1, and the cell array of the 0 th row corresponding thereto is selected, and the code content "10001001" is read out. When the 4-bit address (ADR <0> -ADR <3>) is "0001", YL <1> outputted from the 2-4 decoder is 1, YH <0> is 1, and the corresponding YL <1> and YH <0> phases are outputted and the read word line RWL1 is 1, and the corresponding cell array of the 1 st row is selected to read out the code content "10001001". It can be seen that the two read contents are completely identical, and the circuit is implemented by two rows of cell arrays and their corresponding read word lines RWL0 and RWL1, which causes redundancy in the circuit and results in a waste of area and power consumption of the circuit.
The upper address pre-decoding signal and the lower address pre-decoding signal corresponding to different read addresses are shown in table 1.
TABLE 1
In view of this, the present disclosure provides a method for designing a rom circuit, which removes redundant circuits according to the repeatability of codes, thereby reducing the area and power consumption of the circuit. The method for designing the rom circuit provided by the embodiment of the present application will be described with reference to fig. 2.
Step S101: and designing the row number of the cell array according to the repetition condition of the M rows of codes to be stored, so that the row number of the cell array is the same as the row number N of the M rows of codes after the repetition codes are removed.
In view of the possibility of existence of repeated codes, in order to reduce the number of cell arrays, in the embodiment of the present application, the number of rows of cell arrays is designed according to the repeated condition of M rows of codes to be stored, so that the number of rows of cell arrays is the same as the number N of rows of codes of M rows of codes after removing the repeated codes. Each line code in the M line codes corresponds to a unique read address, N, M is a positive integer, and M is greater than N.
For the sake of easy understanding, taking the case of storing 16 lines of codes as an example, assuming that the 0 th line of codes is repeated with the 1 st line of codes, the number of lines after the repeated codes are removed is 15 lines (one line is removed in the 0 th line of codes and the 1 st line of codes), and thus the number of lines of the corresponding cell array is 15. For another example, assuming that the 16 lines of codes have a 0 th line of codes overlapping with a 1 st line of codes and a 5 th line of codes overlapping with a 10 th line of codes, the number of lines after the overlapping codes are removed is 14 lines (one line is removed in the 0 th line of codes and the 1 st line of codes and one line is removed in the 5 th line of codes and the 10 th line of codes). For another example, if 5 lines of the 16 lines of codes are all the same, the number of lines after the duplicate codes are removed is 12 lines (4 lines are removed from the 5 lines of the same codes).
It should be noted that the number of lines of the code to be stored is not limited to 16, and may be any positive integer, such as 12, 32, 48, etc., and therefore the above example should not be construed as limiting the present application.
Step S102: and designing a logic circuit in the read word line driving circuit according to the repetition condition of the M rows of codes, so that pre-decoding signals corresponding to different read addresses for reading the same code are all connected to the same logic circuit, and finally, only one read word line signal pointing to the same row of unit arrays for storing the same code is output, so that the read word line driving circuit only comprises N logic circuits.
Accordingly, when the logic circuit in the read wordline driver circuit is designed, the design is also performed according to the repetition condition of the M rows of codes, so that the predecode signals (including the high address predecode signal (YH) and the low address predecode signal (YL)) corresponding to different read addresses reading the same code are both connected to the same logic circuit, and finally only one read wordline signal pointing to the same row of cell arrays storing the same code is output, so that the final read wordline driver circuit only includes N logic circuits, instead of M logic circuits as in the prior art.
If there is no duplication, i.e. the M rows of codes are all different, the logic circuit in the read word line driving circuit is the same as the existing one, i.e. includes M logic circuits, each logic circuit includes an and gate, a first input end of the and gate is connected to the corresponding high address predecode signal (YH), a second input end of the and gate is connected to the corresponding low address predecode signal (YL), and an output end of the and gate is connected to the corresponding cell array.
If the M lines of codes have repeated codes, the design of the corresponding logic circuit is the same as that of the existing logic circuit without the repeated codes, and for the logic circuit with the repeated codes (in the case that a plurality of different repeated codes may exist), aiming at each repeated code, according to a high-bit address predecoding signal (YH) and a low-bit address predecoding signal (YL) corresponding to each line of the read repeated codes, a final logic circuit is obtained by combining an OR gate and an AND gate, and the logic circuit enables predecoding signals corresponding to different read addresses of the same code to be connected to the logic circuit, and finally only one read word line signal pointing to the same line unit array storing the same code is output.
The process of obtaining the final logic circuit by combining the or gate and the and gate according to the high address predecoding signal (YH) and the low address predecoding signal (YL) corresponding to each line of the read repetitive code may be:
for example, if the high address pre-decoding signals (YH) corresponding to each row in the repeated code are the same and the low address pre-decoding signals (YL) are different, the low address pre-decoding signals (YL) corresponding to each row are OR-ed by an OR gate, and the output of the OR gate is AND-ed with the high address pre-decoding signals (YH) to obtain the final logic circuit. Still taking the example of storing 16 lines of codes shown in fig. 1, the low address predecode signal (YL) of these 2 lines (line 0 and line 1) is or-ed by using an or gate, and then the output of the or gate is anded with the high address predecode signal (the same as the high address predecode signal of line 0 and line 1), and the simplified rom circuit has the structure shown in fig. 3. The main change is that the circuit in the black bold rectangle in fig. 1 is simplified, two RWL signals are changed into 1 RWL signal, two rows of cell arrays are changed into 1 row of cell arrays, and the 15 rows of codes in the upper left part of fig. 2 are the two repeated rows of codes (0 th row and 1 st row) in fig. 1 are removed by one row, so that only 15 rows of codes without repeated contents are reserved. Accordingly, in the ROM circuit of fig. 3, the cell array is also reduced from 16 lines to 15 lines in fig. 1. The table in the lower left portion of FIG. 3 shows the relationship of address signals ADR <3:0> to the selected RWL, which is reduced from 16 read word lines in FIG. 1 to 15 read word lines in FIG. 3. Further, the read word lines RWL0 and RWL1 in fig. 1 are reduced to reserve only RWL0, so that only 15 read word lines in fig. 3 are needed to control the reading of 15 rows of cell arrays respectively. Wherein at time clk0, when the 4-bit address (ADR <0> -ADR <3> is "0000", YL <0> of the output of the 2-4 decoder is 1, YH <0> is 1, the output of the corresponding YL <0> and YL <1> is 1, and then ANDed with YH <0> and the output read word line RWL0 is 1, thereby selecting the cell array of its corresponding row 0, the code content "10001001" is read out, at time clk1, when the 4-bit address (ADR <0> -ADR <3>) is "0001", YL <1> of the output of the 2-4 decoder is 1, YH <0> is 1, the output of the corresponding YL <0> and YL <1> is still 1, which is ANDed with YH <0> and the selected read word line is still RWL0, thereby selecting the cell array of its corresponding row 0, the read code content is still "10001001", and the read-out cell array is simplified as seen in ROM circuit diagram 10001001, the read result is still the same as in the conventional ROM circuit of fig. 1, i.e. the circuit of fig. 3 performs the same function as in the conventional circuit with less circuit logic. Since the cell array and the read word line in fig. 3 are reduced, circuit area and static power consumption may be reduced.
Wherein, if the number of the repetition lines of the repetition code is larger than 2, the implementation mode of OR gate phase-OR of the low-order address pre-decoding signal (YL) corresponding to each line can be various, for ease of understanding, the repetition number of such repetition code is 4 (assuming lines 0 to 3), and in one embodiment, the low address predecode signal (YL) of any two rows (assumed as row 0 and row 1) may be ored, the output of the or gate is then ored with the low address predecode signal (YL) of one of the remaining rows (assumed to be row 2), then the OR gate is further ANDed with the low address predecode signal (YL) of the remaining row (assumed to be row 3) or finally the output of the last OR gate is ANDed with the high address predecode signal (YH), as shown in FIG. 4. In another embodiment, the low address predecoding signal (YL) of any two rows (assumed as rows 0 and 1) may be phase-summed by using the or gate 1, or the low address predecoding signals (YL) of the remaining two rows (assumed as rows 2 and 3) may be phase-summed by using the or gate, then the outputs of the 2 or gates are phase-summed, and finally the output of the last or gate is phase-summed with the high address predecoding signal (YH), which is schematically illustrated in fig. 5.
For another example, if the high address predecode signals (YH) corresponding to each row in the repetitive code are different and the low address predecode signals (YL) are the same, the high address predecode signals (YH) corresponding to each row are or-ored by an or gate, and the output of the or gate is anded with the low address predecode signals (YL) to obtain the final logic circuit. The process is similar to the above-mentioned principle that if the high address pre-decoding signals (YH) corresponding to each row in the repeated codes are the same, the low address pre-decoding signals (YL) are all different, and for avoiding redundancy, the above-mentioned principle is not illustrated here.
For another example, if the high address pre-decoding signals and the low address pre-decoding signals corresponding to each row in the repetitive code are different, the high address pre-decoding signals and the low address pre-decoding signals in the same row are subjected to phase-and-inversion by using an and gate, and the and gates in each row are subjected to phase-or-inversion by using an or gate, so as to obtain a final logic circuit. Assuming that the codes of the 0 th row and the 5 th row are repeated as an example, as can be seen from the correspondence relationship in table 1, when the upper address pre-decoding signal (YH <0>) corresponding to the 0 th row is different from the upper address pre-decoding signal (YH <1>) corresponding to the 5 th row, and the lower address pre-decoding signal (YL <0>) corresponding to the 0 th row is different from the lower address pre-decoding signal (YL <1>) corresponding to the 5 th row, the upper address pre-decoding signal and the lower address pre-decoding signal of the 0 th row are anded by using the AND gate, and the upper address pre-decoding signal and the lower address pre-decoding signal of the 5 th row are anded by using the AND gate, and then the AND gates of the 0 th row and the 5 th row are output and are anded by using the OR gate, so that the logic circuit corresponding to the repeated codes can be obtained. If the number of the repeated lines of the repeated code is greater than 2, there are various implementations of performing or on the and gate outputs of the lines by using an or gate, taking the code repetition of the 0 th line, the 5 th line, the 10 th line and the 15 th line as an example, performing or on the and gate outputs of any two lines (assumed to be the 0 th line and the 5 th line) by using an or gate, performing or on the or gate output of the remaining line (assumed to be the 10 th line), and performing or on the or gate and the and gate of the remaining line (assumed to be the 15 th line), where the principle refers to the or gate part in fig. 4. In yet another embodiment, the output of any two rows (assumed as 0 th row and 5 th row) of the and gates may be output or the output of the remaining two rows (assumed as 10 th row and 15 th row) of the and gates may be output or output by the or gates, and then the output of the 2 or gates may be output or output, the principle of which is shown in fig. 5 or the gate section.
It should be noted that, in addition to the final logic circuit obtained by combining the or gate and the and gate, other logic gates that realize the same logic may be combined to obtain the final logic circuit, which only increases the complexity and cost of the circuit relatively, for example, the final logic circuit obtained by combining the nand gate and the and gate is also replaced by the nand gate (that is, only one read address is input into the decoding circuit at the same time, and accordingly the high address pre-decoding signal and the low address pre-decoding signal corresponding to the read address are 1, and the high address pre-decoding signal and the low address pre-decoding signal corresponding to each row of the repeated code are both 0 and the output is still 1); for another example, the final logic circuit is obtained by combining an or gate and a nand gate and a not gate, that is, the nand gate and the not gate replace an and gate. The use of or gates and gates in the above examples, therefore, is not to be combined to form the final logic circuit, and should not be construed as limiting the present application.
If at least two of the three conditions (the high address pre-decoding signals (YH) corresponding to each row are different, the low address pre-decoding signals (YL) are the same, the high address pre-decoding signals (YH) corresponding to each row are the same, the low address pre-decoding signals (YL) are different, the high address pre-decoding signals (YH) corresponding to each row are different, and the low address pre-decoding signals (YL) are different) exist in the repeated code at the same time, the repeated code is designed according to the design principle of the logic circuit of each condition, and then the output results of different conditions are compared or compared by using an OR gate, so that the final logic circuit can be obtained. For example, if there are the same high address predecode signal (YH) and different low address predecode signal (YL) for 2 rows, and there are also the different high address predecode signals (YH) and different low address predecode signals (YL) for 1 row, then for the case where there are the same high address predecode signal (YH) and different low address predecode signals (YL) for 2 rows, the low address predecode signals of the 2 rows are first or 'ed' by or gates, and then the output of or gates and the high address predecode signals are anded; for the row with different high address pre-decoding signals (YH) and low address pre-decoding signals (YL), the high address pre-decoding signal and the low address pre-decoding signal of the row are AND-ed by using AND gates, and finally, the output of 2 AND gates are OR-ed by using OR gates. For the sake of easy understanding, the 16 lines of codes stored in fig. 1 are taken as an example, and it is assumed that the codes in lines 0, 3 and 5 are repeated, wherein the high address pre-decoded signal and the low address pre-decoded signal corresponding to the code in line 0 are YH <0>, YL <0>, respectively; the high address pre-decoding signal and the low address pre-decoding signal corresponding to the 3 rd row code are YH <0>, YL <3> respectively, the high address pre-decoding signal and the low address pre-decoding signal corresponding to the 5 th row code are YH <1>, YL <1> respectively, as can be seen, the 0 th row code is the same as the high address pre-decoding signal corresponding to the 3 rd row code, the low address pre-decoding signal is different, and the 5 th row code is the same as the high address pre-decoding signal and the low address pre-decoding signal corresponding to the 0 th row code and the 3 rd row code, then the low address pre-decoding signals of the 0 th row and the 3 rd row are either connected or connected by using a gate, and the output of the gate is connected with the high address pre-decoding signals of the 0 th row and the 3 rd row; for the code of line 5, the same high address pre-decoded signal as the line 5 is pre-decoded by the gate and the low address pre-decoded signal are anded, and finally the outputs of the two and gates are ored by the or gate, and the architecture of the simplified rom circuit is shown in fig. 6. The main change is that RWL0, RWL3 and RWL5 are reduced to only reserve RWL0, and at the same time, the original 3-row cell array in fig. 1 is reduced to 1-row cell array, and the 14-row code in the upper left part of fig. 6 is obtained by removing 2 rows from the three repeated rows of codes (0 th row, 3 rd row and 5 th row) in fig. 1, so that only 14 rows of codes without repeated contents are reserved.
In the embodiment of the application, through simplifying the logic circuit of the read only memory, the area and the power consumption of the read only memory circuit are reduced while the same function as that of the traditional ROM circuit is realized, and the complexity of circuit design is not increased. In addition, for different repeated codes, the read word line driving circuit in the rom circuit and the simplified circuit logic of the cell array have different implementation examples (the same principle) which are not listed here.
It should be noted that, the above-mentioned example is 2 decoding circuits 2-4, and it can also adopt 1 decoder 1-2 and one decoder 3-8 to implement the same control logic, where the lower three-bit addresses ADR <0>, ADR <1>, ADR <2> are input into the 3-8 decoders, and output YL <0> to YL <7 >; the high address ADR <3> is inputted to the 1-2 decoders YH <0> to YH <1 >. The upper address pre-decoded signal and the lower address pre-decoded signal corresponding to different read addresses are shown in table 2. In addition, it should be noted that the number of rows of the code to be stored is not limited to 16, and if 35, the corresponding decoding circuit also needs to be adjusted accordingly, so that it can output the pre-decoded signal for selecting the corresponding 35 cell arrays, which may be implemented by using 2 decoders of 3 to 8, or a 2 to 4 decoder and a 4 to 16 decoder. The exemplary 2-4 decoding circuits described above are therefore not to be construed as limiting the present application. For different decoding circuits, the read word line driving circuit in the rom circuit and the simplified circuit logic of the cell array have different implementation examples (same principle) which are not listed here.
TABLE 2
By using the above method for designing the ROM circuit, the finally obtained ROM circuit comprises: n unit arrays, a decoding circuit and a read word line driving circuit. The N unit arrays are used for storing N lines of codes, the N lines of codes are obtained by removing repeated codes from M lines of codes, each line of codes in the M lines of codes corresponds to a unique read address, N, M is a positive integer, and M is larger than N.
And the decoding circuit is used for outputting a pre-decoding signal for selecting the corresponding unit array according to the read address of the input M-row code.
And the read word line driving circuit is used for outputting a read word line signal for selecting the corresponding cell array according to the pre-decoding signal. The read word line driving circuit includes: n-way logic circuits in one-to-one correspondence with the N cell arrays, wherein there is at least one logic circuit: the input end of the logic circuit is connected with the predecoding signals corresponding to different reading addresses for reading the same code, and the output end of the logic circuit is connected with the unit array for storing the same code.
In one embodiment, the logic circuit includes: the circuit is formed by combining an OR gate and an AND gate. Besides, the logic circuit can be obtained by combining an or gate and an and gate, or by combining other logic gates that implement the same logic, for example, the logic circuit can be obtained by combining a nand gate and an and gate, that is, the or gate is replaced by the nand gate; for another example, the logic circuit is obtained by combining an or gate and a nand gate + not gate, that is, the nand gate + not gate replaces the and gate. Therefore, the embodiment of the logic circuit obtained by combining the or gate and the and gate provided by the embodiment of the present application cannot be understood as a limitation of the present application.
Different implementation examples of the corresponding logic circuits are also available for different code repetition cases, but the corresponding principle is always the same no matter how the code repetition cases change. For example, if the high address predecode signals corresponding to each row in the repeated codes corresponding to the logic circuit are the same, and the low address predecode signals are different, the input end of the or gate in the logic circuit is the low address predecode signal of each row, the input of the and gate is the output of the or gate and the high address predecode signal, and the output of the and gate is connected with the unit array storing the same code, that is, the or gate is used to phase or phase the low address predecode signals of each row, and the output result is then anded with the high address predecode signal. The specific principle of the method can be seen in the corresponding parts of the method embodiments. For another example, if the high address predecoding signals corresponding to each row in the repetitive code corresponding to the logic circuit are all different, and the low address predecoding signals are all the same, the input end of the or gate in the logic circuit is the high address predecoding signal of each row, the input end of the and gate is the output of the or gate and the low address predecoding signal, and the output of the and gate is connected with the cell array storing the same code. That is, the high address pre-decoding signal phase corresponding to each row of the or gate is used or the output result is compared with the low address pre-decoding signal phase. The specific principle of the method can be seen in the corresponding parts of the method embodiments.
For another example, if the high address predecode signals and the low address predecode signals corresponding to each row in the repetitive code corresponding to the logic circuit are all different, then the input of the and gate in the logic circuit is the high address predecode signal and the low address predecode signal of the same row, or the input of the gate is the output of the and gate of each row, or the output of the gate is connected to the cell array storing the same code. That is, the high address pre-decoding signal and the low address pre-decoding signal in the same row are anded by the and gates, and then the output of each and gate is anded by the or gate, and the specific principle thereof is as follows.
If at least 2 of the 3 cases exist at the same time, the design is performed according to the design principle of the logic circuit of each case, and then the output results of different cases are subjected to or by using an or gate, taking the 16-line code stored in fig. 1 as an example, and assuming that the codes of the 0 th line, the 3 rd line and the 5 th line are repeated, the logic circuits corresponding to the codes of the 0 th line, the 3 rd line and the 5 th line are as shown in fig. 6.
The implementation principle and the resulting technical effect of the rom circuit provided in the embodiments of the present application are the same as those of the method embodiments described above, and for the sake of brief description, reference may be made to the corresponding contents in the method embodiments described above where no part of the embodiments of the apparatus is mentioned.
The embodiment of the application also provides a read-only memory, which comprises the read-only memory circuit and other components, such as a control circuit, a read-out circuit and the like, wherein the control circuit is connected with the decoding circuit in the read-only memory circuit, and the read-out circuit is connected with each row of unit arrays in the read-only memory circuit.
The embodiment of the application also provides an electronic device comprising the read-only memory, wherein the electronic device comprises but is not limited to a computer, a tablet computer, a smart phone, a server and the like.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. A method for designing a read-only memory circuit, comprising:
designing the row number of a unit array according to the repetition condition of M rows of codes to be stored, so that the row number of the unit array is the same as the row number N of the M rows of codes after the repetition codes are removed, wherein each row of codes in the M rows of codes corresponds to a unique read address, N, M is a positive integer, and M is larger than N;
and designing a logic circuit in the read word line driving circuit according to the repetition condition of the M rows of codes, so that pre-decoding signals corresponding to different read addresses for reading the same code are all connected to the same logic circuit, and finally, only one read word line signal pointing to the same row of unit arrays for storing the same code is output, so that the read word line driving circuit only comprises N logic circuits.
2. The method of claim 1, wherein the pre-coded signal comprises: a high address predecode signal and a low address predecode signal; designing a logic circuit in a read word line driving circuit according to the repetition condition of the M rows of codes, wherein the logic circuit comprises:
for each kind of repeated codes, according to a high-order address predecoding signal and a low-order address predecoding signal corresponding to each row for reading the repeated codes, an OR gate and an AND gate are combined to obtain a final logic circuit, the logic circuit enables predecoding signals corresponding to different reading addresses for reading the same codes to be connected to the logic circuit, and finally only one reading word line signal pointing to the same row unit array for storing the same codes is output.
3. The method of claim 2, wherein the final logic circuit is obtained by combining the high address predecode signal and the low address predecode signal corresponding to each row of the read repetitive code by using an or gate and an and gate, comprising:
if the high address pre-decoding signals corresponding to each row in the repeated code are the same and the low address pre-decoding signals are different, the low address pre-decoding signals corresponding to each row are OR-ed by using an OR gate, and the output of the OR gate is AND-ed with the high address pre-decoding signals to obtain a final logic circuit.
4. The method of claim 2, wherein the final logic circuit is obtained by combining the high address predecode signal and the low address predecode signal corresponding to each row of the read repetitive code by using an or gate and an and gate, comprising:
if the high-order address pre-decoding signals corresponding to each row in the repeated code are different and the low-order address pre-decoding signals are the same, the high-order address pre-decoding signals corresponding to each row are OR-ed by an OR gate, and the output of the OR gate is AND-ed with the low-order address pre-decoding signals to obtain a final logic circuit.
5. The method of claim 2, wherein the final logic circuit is obtained by combining the high address predecode signal and the low address predecode signal corresponding to each row of the read repetitive code by using an or gate and an and gate, comprising:
if the high-order address pre-decoding signals corresponding to each row in the repeated code are different and the low-order address pre-decoding signals are different, the high-order address pre-decoding signals and the low-order address pre-decoding signals in the same row are subjected to AND operation by an AND gate, and the AND gates in each row are subjected to OR operation by an OR gate to obtain a final logic circuit.
6. A read-only memory circuit, comprising:
the N unit arrays are used for storing N lines of codes, the N lines of codes are obtained by removing repeated codes from M lines of codes, each line of codes in the M lines of codes corresponds to a unique read address, N, M is a positive integer, and M is larger than N;
the decoding circuit is used for outputting a pre-decoding signal for selecting the corresponding unit array according to the read address of the input M-row code;
the read word line driving circuit is used for outputting a read word line signal for selecting the corresponding cell array according to the pre-decoding signal; the read word line driving circuit includes: n logic circuits in one-to-one correspondence with the N cell arrays, wherein there is at least one logic circuit: the input end of the logic circuit is connected with the predecoding signals corresponding to different reading addresses for reading the same code, and the output end of the logic circuit is connected with the unit array for storing the same code.
7. The ROM circuit of claim 6, wherein the logic circuit comprises: the circuit is formed by combining an OR gate and an AND gate.
8. The rom circuit of claim 7, wherein the predecode signal comprises: a high address predecode signal and a low address predecode signal;
if the high address pre-decoding signals corresponding to each row in the repeated codes corresponding to the logic circuit are the same, and the low address pre-decoding signals are different, the input end of the OR gate in the logic circuit is the low address pre-decoding signals corresponding to each row, the input of the AND gate is the output of the OR gate and the high address pre-decoding signals, and the output of the AND gate is connected with the unit array for storing the same codes.
9. The rom circuit of claim 7, wherein the predecode signal comprises: a high address predecode signal and a low address predecode signal;
if the high-order address pre-decoding signals corresponding to each row in the repeated codes corresponding to the logic circuit are different and the low-order address pre-decoding signals are the same, the input end of an OR gate in the logic circuit is the high-order address pre-decoding signals of each row, the input end of the AND gate is the output of the OR gate and the low-order address pre-decoding signals, and the output of the AND gate is connected with a unit array for storing the same codes.
10. The rom circuit of claim 7, wherein the predecode signal comprises: a high address predecode signal and a low address predecode signal;
if the high address pre-decoding signals corresponding to each row in the repeated codes corresponding to the logic circuit are different, and the low address pre-decoding signals are different, the input of the AND gate in the logic circuit is the high address pre-decoding signal and the low address pre-decoding signal of the same row, the input of the OR gate is the output of the AND gate of each row, and the output of the OR gate is connected with the unit array for storing the same codes.
11. A rom comprising a control circuit, a readout circuit and the rom circuit of any one of claims 6-10, wherein the control circuit is connected to a decoding circuit in the rom circuit, and the readout circuit is connected to each row of the cell array in the rom circuit.
12. An electronic device comprising a body and a read only memory according to claim 11.
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| US6021085A (en) * | 1997-04-25 | 2000-02-01 | Mitsubishi Denki Kabushiki Kaisha | Read only semiconductor memory device |
| CN102360568A (en) * | 2011-08-24 | 2012-02-22 | 北京兆易创新科技有限公司 | Parallel asynchronous memory and data reading method thereof |
| CN103518193A (en) * | 2011-04-08 | 2014-01-15 | 美光科技公司 | Data deduplication |
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| US6021085A (en) * | 1997-04-25 | 2000-02-01 | Mitsubishi Denki Kabushiki Kaisha | Read only semiconductor memory device |
| CN103518193A (en) * | 2011-04-08 | 2014-01-15 | 美光科技公司 | Data deduplication |
| CN102360568A (en) * | 2011-08-24 | 2012-02-22 | 北京兆易创新科技有限公司 | Parallel asynchronous memory and data reading method thereof |
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