CN111968567B - Display panel and electronic equipment - Google Patents
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- CN111968567B CN111968567B CN202010899782.2A CN202010899782A CN111968567B CN 111968567 B CN111968567 B CN 111968567B CN 202010899782 A CN202010899782 A CN 202010899782A CN 111968567 B CN111968567 B CN 111968567B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
The embodiment of the invention discloses a display panel and an electronic device, wherein the display panel comprises: the display panel comprises a display area and a non-display area, wherein the display area comprises a plurality of pixel driving circuits, the non-display area comprises a plurality of display driving circuits, and the display driving circuits provide data signals for the pixel driving circuits through data lines; the display driving circuit comprises a pulse width modulation unit and a digital-to-analog conversion unit, and the pixel driving circuit comprises an analog-to-digital conversion unit and a digital memory; the digital-to-analog conversion unit is used for receiving the digital data signals sent by the pulse width modulation unit and converting the digital data signals into analog data signals, and the analog data signals are transmitted to the analog-to-digital conversion unit through data lines; the analog-to-digital conversion unit is used for converting the analog data signal into a digital data signal and transmitting the digital data signal to the digital memory for storage. In the embodiment of the invention, the transmission loss of the data signal on the data line is reduced.
Description
Technical Field
The present invention relates to display technologies, and in particular, to a display panel and an electronic device.
Background
The display device is composed of a display device and related circuits, and can provide visual information in accordance with visual perception factors. With the rapid development of network communication technology, more and more users watch videos on display devices, and thus the requirements on the resolution and picture quality of the display devices are higher and higher.
The micro light emitting diode display is a display device formed by thinning, microminiaturizing and arraying light emitting diode LEDs and then encapsulating the light emitting diode LEDs with a circuit substrate. Such micro-led displays have very high color saturation, and thus are the mainstream direction for the development of display devices at present.
However, the data signal transmission loss of the conventional micro light emitting diode display is too large, which affects the display effect of the display.
Disclosure of Invention
The embodiment of the invention provides a display panel and an electronic device, which are used for reducing the transmission loss of data signals on data lines.
An embodiment of the present invention provides a display panel, including: the display panel comprises a display area and a non-display area, wherein the display area comprises a plurality of pixel driving circuits, the non-display area comprises a plurality of display driving circuits, and the display driving circuits are electrically connected with the pixel driving circuits through data lines and provide data signals for the pixel driving circuits through the data lines;
the display driving circuit comprises a pulse width modulation unit and a digital-to-analog conversion unit, and the pixel driving circuit comprises an analog-to-digital conversion unit and a digital memory;
the digital-to-analog conversion unit is electrically connected with the pulse width modulation unit and is electrically connected with the analog-to-digital conversion unit through the data line, the digital-to-analog conversion unit is used for receiving a digital data signal sent by the pulse width modulation unit and converting the digital data signal into an analog data signal, and the analog data signal is transmitted to the analog-to-digital conversion unit through the data line;
the analog-to-digital conversion unit is electrically connected with the digital memory and is used for converting the analog data signals into digital data signals and transmitting the digital data signals to the digital memory for storage.
Based on the same inventive concept, the embodiment of the invention also provides an electronic device, which comprises the display panel.
In the embodiment of the invention, the non-display area comprises a plurality of display driving circuits, the display area comprises a plurality of pixel driving circuits, and the display driving circuits are connected with the pixel driving circuits by adopting data lines; in the non-display area, the digital-to-analog conversion unit receives the digital data signal sent by the pulse width modulation unit, converts the digital data signal into an analog data signal, and outputs the analog data signal through a data line; in the display area, an analog-to-digital conversion unit of the pixel driving circuit receives an analog data signal through a data line, converts the analog digital signal into a digital data signal, and transmits the digital data signal to a digital memory for storage. In the embodiment of the invention, the display driving circuit of the non-display area transmits the analog data signal to the pixel driving circuit through the data line, and the data line is long, so that the transmission time of the data signal transmitted from the non-display area to the display area can be reduced by transmitting the analog data signal, the loss of the data signal in the transmission process can be reduced, and the signal transmission efficiency and the signal accuracy are improved.
Drawings
To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description, although being some specific embodiments of the present invention, can be extended and extended to other structures and drawings by those skilled in the art according to the basic concepts of the device structure, the driving method and the manufacturing method disclosed and suggested by the various embodiments of the present invention, without making sure that these should be within the scope of the claims of the present invention.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a first display element driving circuit;
FIG. 3 is a schematic diagram of a second display element driving circuit;
FIG. 4 is a schematic diagram of a third display element driving circuit;
FIG. 5 is a schematic diagram of a fourth display element driving circuit;
FIG. 6 is a schematic diagram of a fifth display element driving circuit;
FIG. 7 is a schematic diagram of a sixth display element driving circuit;
fig. 8 is a schematic diagram of a seventh display element driving circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described through embodiments with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the basic idea disclosed and suggested by the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, a schematic diagram of a display panel according to an embodiment of the invention is shown, and fig. 2 is a schematic structural diagram of a display driving circuit and a pixel driving circuit. The display panel provided by the embodiment comprises: a display area 10 and a non-display area 20, the display area 10 including a plurality of pixel driving circuits 11, the non-display area 20 including a plurality of display driving circuits 21, the display driving circuits 21 being electrically connected to the pixel driving circuits 11 through data lines 30 and supplying data signals to the pixel driving circuits 11 through the data lines 30; the display drive circuit 21 includes a pulse width modulation unit 21a and a digital-to-analog conversion unit 21b, and the pixel drive circuit 11 includes an analog-to-digital conversion unit 11a and a digital memory 11 b; the digital-to-analog conversion unit 21b is electrically connected with the pulse width modulation unit 21a and is electrically connected with the analog-to-digital conversion unit 11a through a data line 30, the digital-to-analog conversion unit 21b is used for receiving the digital data signal sent by the pulse width modulation unit 21a and converting the digital data signal into an analog data signal, and the analog data signal is transmitted to the analog-to-digital conversion unit 11a through the data line 30; the analog-to-digital conversion unit 11a is electrically connected to the digital memory 11b, and is configured to convert the analog data signal into a digital data signal, and transmit the digital data signal to the digital memory 11b for storage.
In this embodiment, the data lines 30 extend from the non-display area 20 to the display area 10 for electrically connecting the display driving circuits 21 and the pixel driving circuits 11, and one display driving circuit 21 provides data signals to one or more pixel driving circuits 11 electrically connected correspondingly in a time-sharing manner through one data line 30. As shown in fig. 1, one display driving circuit 21 may be selected to be electrically connected to one data line 30, one data line 30 is disposed corresponding to one column of display units 12 having the same color, and one column of pixel driving circuits 11 drives 3 columns of display units 12 having different colors, where one pixel driving circuit 11 drives 3 display units 12 having different colors, and the 3 display units 12 having different colors may be selected to be R, G, B. Taking the display driving circuit 21x as an example, it provides the required data signals to a row of display units G through a data line 30, the display driving circuit 21x provides the data signals to each pixel driving circuit 11 in a row through the data line 30 in a time-sharing manner, so that the pixel driving circuit 11 drives the display units G electrically connected correspondingly to emit or not according to the stored data signals, and displays the corresponding gray scale. If one pixel driving circuit 11 is electrically connected to a plurality of display units having the same color, the display driving circuit 12 inputs a plurality of data signals to the pixel driving circuit 11 in a time-sharing manner through one data line 30.
It is to be understood that the color, number, etc. of the display units driven by the pixel driving circuit are not limited to those shown in fig. 1, and the number of the data lines electrically connected to the pixel driving circuit is different according to the color and number of the display units driven by the pixel driving circuit, and is not particularly limited and described in the present invention.
The display drive circuit 21 is located in the non-display area 20, and mainly includes a pulse width modulation unit 21a and a digital-to-analog conversion unit 21 b. The output end of the pulse width modulation unit 21a is electrically connected with the input end of the digital-to-analog conversion unit 21b, and the pulse width modulation unit 21a receives a first display unit data signal, converts the first display unit data signal into a digital data signal, and sends the digital data signal to the digital-to-analog conversion unit 21 b; the digital-to-analog conversion unit 21b is used to convert the digital data signal into an analog data signal. It can be understood that the first display unit is any one display unit correspondingly driven by the display driving circuit, and the display driving circuit transmits a plurality of data signals to the plurality of pixel driving circuits in a time-sharing manner through the data lines.
The optional non-display area 20 includes a display driving chip 20a, and a plurality of display driving circuits 21 are provided in the display driving chip 20 a. The display driving chip 20a determines a data signal of each display unit 12 according to a picture to be displayed, and sends the data signal of the display unit 12 to the corresponding display driving circuit 21, the display driving circuit 21 converts the data signal of the display unit 12 into an analog signal and sends the analog signal to the pixel driving circuit 11 through the data line 30, and the pixel driving circuit 11 drives the corresponding display unit 12 according to the data signal. It can be understood that when one display driving circuit 21 drives a plurality of display units 12, the display driving chip 20a time-divisionally obtains the data signal of each corresponding display unit 12, and time-divisionally outputs the analog data signal of each display unit 12 to the pixel driving circuit 11 through the data line 30.
The pixel driving circuit 11 is located in the display area 10, and mainly includes an analog-to-digital conversion unit 11a and a digital memory 11 b. The input end of the analog-to-digital conversion unit 11a is electrically connected with the output end of the digital-to-analog conversion unit 21b through the data line 30, and the output end of the analog-to-digital conversion unit 11a is electrically connected with the input end of the digital memory 11 b. The digital-to-analog conversion unit 21b transmits the analog data signal to the analog-to-digital conversion unit 11a through the data line 30; the analog-to-digital conversion unit 11a converts the analog data signal into a digital data signal, and transmits the digital data signal to the digital memory 11b for storage. The display driving circuit 21 transmits the analog data signal to the pixel driving circuit 11 through the data line 30, improving data transmission efficiency.
In the embodiment of the invention, the non-display area comprises a plurality of display driving circuits, the display area comprises a plurality of pixel driving circuits, and the display driving circuits are connected with the pixel driving circuits by adopting data lines; in the non-display area, the digital-to-analog conversion unit receives the digital data signal sent by the pulse width modulation unit, converts the digital data signal into an analog data signal, and outputs the analog data signal through a data line; in the display area, an analog-to-digital conversion unit of the pixel driving circuit receives an analog data signal through a data line, converts the analog digital signal into a digital data signal, and transmits the digital data signal to a digital memory for storage. In the embodiment of the invention, the display driving circuit of the non-display area transmits the analog data signal to the pixel driving circuit through the data line, and the data line is long, so that the transmission time of the data signal transmitted from the non-display area to the display area can be reduced by transmitting the analog data signal, the loss of the data signal in the transmission process can be reduced, and the signal transmission efficiency and the signal accuracy are improved.
The analog data signal may be a voltage signal reflecting a gray level (e.g., a voltage value reflecting a gray level), and the digital data signal may be a digital signal reflecting a gray level and having a bit (bit) as a storage unit.
Illustratively, on the basis of the above technical solution, the selectable analog-to-digital conversion unit transmits the digital data signal to the digital memory in a parallel output manner; or the analog-to-digital conversion unit transmits the digital data signal to the digital memory in a serial output mode.
The analog-to-digital conversion unit 11a transmits the digital data signal to the digital memory 11b in a serial output manner as shown in fig. 2. As shown in fig. 3, the analog-to-digital conversion unit 11a transmits the digital data signal to the digital memory 11b in a parallel output manner, so that the transmission time of the data signal in the pixel driving circuit 11 can be reduced, and the signal transmission efficiency can be improved; for example, the analog-to-digital conversion unit 11a is electrically connected to the digital memory 11b through four transmission lines, each transmission line adopts a serial output mode, and the four transmission lines adopt a parallel transmission mode, so that the transmission efficiency of the data signal in the pixel driving circuit 11 is greatly improved.
Illustratively, on the basis of the above technical solution, the digital-to-analog converting unit 21b shown in fig. 4 may optionally include a first digital-to-analog converter 211 and a second digital-to-analog converter 212, the analog-to-digital converting unit 11a includes a first analog-to-digital converter 111 and a second analog-to-digital converter 112, the data line 30 includes a first data line 31 and a second data line 32, the first digital-to-analog converter 211 is electrically connected to the first analog-to-digital converter 111 through the first data line 31, and the second digital-to-analog converter 212 is electrically connected to the second analog-to-digital converter 112 through the second data line 32; the digital data signal is an n-bit digital signal; the first digital-to-analog converter 211 is configured to convert odd-numbered digital signals in the digital data signals into first analog data signals and transmit the first analog data signals to the first analog-to-digital converter 111, so that the first analog-to-digital converter 111 transmits the converted first digital data signals to the digital memory 11 b; the second digital-to-analog converter 212 is configured to convert even-numbered digital signals in the digital data signals into second analog data signals and transmit the second analog data signals to the second analog-to-digital converter 112, so that the second analog-to-digital converter 112 transmits the converted second digital data signals to the digital memory 11 b.
As shown in fig. 4, a digital-to-analog converter is electrically connected to an analog-to-digital converter through a data line. The first dac 211 receives the digital data signal sent by the pwm unit 21a, converts the odd-numbered digital data signal in the digital data signal into a first analog data signal, and transmits the first analog data signal to the first adc 111 through the first data line 31, and the first adc 111 converts the received first analog data signal into a first digital data signal, and transmits the first digital data signal to the digital memory 11 b. Synchronously, the second digital-to-analog converter 212 receives the digital data signal sent by the pulse width modulation unit 21a, converts the even-numbered digital data signal in the digital data signal into a second analog data signal, and transmits the second analog data signal to the second analog-to-digital converter 112 through the second data line 32, and the second analog-to-digital converter 112 converts the received second analog data signal into a second digital data signal, and transmits the second digital data signal to the digital memory 11 b. The digital memory 11b receives the first digital data signal and the second digital data signal, and processes the first digital data signal and the second digital data signal to obtain an n-bit digital data signal of one display unit electrically connected to the pixel driving circuit 11.
In this embodiment, the odd-numbered digital signals in the n-bit digital data signals are converted into the first analog data signals and output through the first data line 31, and the even-numbered digital signals in the n-bit digital data signals are converted into the second analog data signals and output through the second data line 32, so that the transmission time of the data signals on the data lines can be further reduced, the transmission efficiency of the data signals on the data lines can be improved, and the signal transmission loss can be reduced.
The optional digital-to-analog conversion unit comprises a first digital-to-analog converter and a second digital-to-analog converter, the analog-to-digital conversion unit comprises a first analog-to-digital converter and a second analog-to-digital converter, the data line comprises a first data line and a second data line, the first digital-to-analog converter is electrically connected with the first analog-to-digital converter through the first data line, and the second digital-to-analog converter is electrically connected with the second analog-to-digital converter through the second data line; the digital data signal is an n-bit digital signal, and n is an even number; the first digital-to-analog converter is used for converting the 1 st bit to the n/2 th bit digital signals in the digital data signals into first analog data signals and transmitting the first analog data signals to the first analog-to-digital converter, so that the first analog-to-digital converter transmits the converted first digital data signals to the digital memory; the second digital-to-analog converter is used for converting the digital signals of (n/2) +1 th bit to the nth bit in the digital data signals into second analog data signals and transmitting the second analog data signals to the second analog-to-digital converter, so that the second analog-to-digital converter transmits the converted second digital data signals to the digital memory.
Different from the above embodiment, referring to fig. 4, it is also possible to select the first digital-to-analog converter 211 for converting the first n/2-bit digital signal in the digital data signal into the first analog data signal and outputting the first analog data signal through the first data line 31, and the second digital-to-analog converter 212 for converting the last n/2-bit digital signal in the digital data signal into the second analog data signal and outputting the second analog data signal through the second data line 32. It is understood that the digital data signal output by the pulse width modulation unit may also be distributed to the first digital-to-analog converter and the second digital-to-analog converter according to other distribution modes, and is not limited to the above embodiments.
The optional analog-to-digital converter transmits the digital data signal to the digital memory in a parallel or serial output mode. As shown in fig. 4, the digital data signal is transmitted between the analog-to-digital converter in the pixel driving circuit 11 and the digital memory 11b in a serial output manner. As shown in fig. 5, the digital data signal is transmitted between the analog-to-digital converter in the pixel driving circuit 11 and the digital memory 11b in a parallel output manner, so that the transmission time of the data signal in the pixel driving circuit 11 can be reduced, and the signal transmission efficiency can be improved.
For example, on the basis of the above technical solution, the digital-to-analog converting unit 21b may include a 1 st digital-to-analog converter 211 to an m th digital-to-analog converter 21m as shown in fig. 6, the analog-to-digital converting unit 11a includes a 1 st analog-to-digital converter 111 to an m th analog-to-digital converter 11m, the data line 30 includes a 1 st data line 31 to an m th data line 3m, and the i th digital-to-analog converter is electrically connected to the i th analog-to-digital converter through the i th data line; the digital data signal is an n-bit digital signal, m and n are even numbers and n is a multiple of m; the ith digital-to-analog converter is used for converting the mk + i-th bit digital signal in the digital data signal into an ith analog data signal and transmitting the ith analog data signal to the ith analog-to-digital converter, so that the ith analog-to-digital converter transmits the converted ith digital data signal to the digital memory 11b, wherein i is 1,2, …, m, k is 0,1, …, (n/m) -1.
As shown in fig. 6, a digital-to-analog converter is electrically connected to an analog-to-digital converter through a data line. The first dac 211 receives the digital data signal sent by the pwm unit 21a, converts the digital signals of the 1 st bit, the m +1 th bit, the 2m +1 th bit, …, and the n-m +1 th bit in the digital data signal into a first analog data signal, and transmits the first analog data signal to the first adc 111 through the first data line 31, and the first adc 111 converts the received first analog data signal into a first digital data signal, and transmits the first digital data signal to the digital memory 11 b.
Synchronously, the second digital-to-analog converter 212 receives the digital data signal sent by the pulse width modulation unit 21a, converts the digital signals of the 2 nd bit, the m +2 th bit, the 2m +2 th bit, …, and the n-m +2 th bit in the digital data signal into a second analog data signal, and transmits the second analog data signal to the second analog-to-digital converter 112 through the second data line 32, and the second analog-to-digital converter 112 converts the received second analog data signal into a second digital data signal, and transmits the second digital data signal to the digital memory 11 b.
Synchronously, the ith digital-to-analog converter receives the digital data signal sent by the pulse width modulation unit 21a, converts the digital signals of the ith bit, the (m + i) th bit, the (2 m + i) th bit, … and the (n-m + i) th bit in the digital data signal into the ith analog data signal, and transmits the ith analog data signal to the ith analog-to-digital converter through the ith data line, and the ith analog-to-digital converter converts the received ith analog data signal into the ith digital data signal and transmits the ith digital data signal to the digital memory 11 b.
By analogy, the mth dac 21m receives the digital data signal sent by the pwm unit 21a, converts the mth bit, 2 mth bit, 3 mth bit, …, and nth bit digital signals in the digital data signal into an mth analog data signal, and transmits the mth analog data signal to the mth adc 11m through the mth data line 3m, and the mth adc 11m converts the received mth analog data signal into an mth digital data signal and transmits the mth digital data signal to the digital memory 11 b.
The digital memory 11b receives the first digital data signal, the second digital data signal, …, the ith digital data signal, …, and the mth digital data signal, and processes the signals to obtain an n-bit digital data signal of one display unit electrically connected to the pixel driving circuit 11.
In this embodiment, the n-bit digital data signals are converted into m analog data signals and output through m data lines, so that the transmission time of the data signals on the data lines can be further reduced, the transmission efficiency of the data signals on the data lines can be improved, and the signal transmission loss can be reduced.
The optional digital-to-analog conversion unit comprises a 1 st digital-to-analog converter, the analog-to-digital conversion unit comprises a 1 st analog-to-digital converter, the data lines comprise a 1 st data line and an m th data line, and the ith digital-to-analog converter is electrically connected with the ith analog-to-digital converter through the ith data line; the digital data signal is an n-bit digital signal, m and n are even numbers and n is a multiple of m; the ith digital-to-analog converter is used for converting the digital signals from (ni-n + m)/m bits to the digital signals from the (ni/m) th bit to the (ni/m) th bit in the digital data signals into ith analog data signals and transmitting the ith analog-to-digital converter to enable the ith analog-to-digital converter to transmit the converted ith digital data signals to the digital memory, wherein i is 1,2, … and m.
Unlike the above embodiment, referring to fig. 6, it is also possible to select a first digital-to-analog converter 211 for converting the 1 st to n/m-th digital signals in the digital data signals into first analog data signals and outputting the first analog data signals through the first data line 31, a second digital-to-analog converter 212 for converting the (n/m) +1 st to 2 n/m-th digital signals in the digital data signals into second analog data signals and outputting the second analog data signals through the second data line 32, an ith digital-to-analog converter for converting the (ni-n + m)/m-th to ni/m-th digital signals in the digital data signals into ith analog data signals and outputting the ith analog data signals through the ith data line, in analogy, the mth dac 21m is configured to convert the digital signals from the (n) - (n/m) +1 th bit to the nth bit in the digital data signals into an mth analog data signal and output the mth analog data signal through the mth data line 3 m. It is understood that the digital data signal output by the pulse width modulation unit may also be distributed to the first to m-th digital-to-analog converters according to other distribution modes, and is not limited to the above embodiments.
The optional analog-to-digital converter transmits the digital data signal to the digital memory in a parallel or serial output mode. As shown in fig. 6, the digital data signal is transmitted between the analog-to-digital converter in the pixel driving circuit 11 and the digital memory 11b in a serial output manner. As shown in fig. 7, the digital data signal is transmitted between the analog-to-digital converter in the pixel driving circuit 11 and the digital memory 11b in a parallel output manner, so that the transmission time of the data signal in the pixel driving circuit 11 can be reduced, and the signal transmission efficiency can be improved.
For the display panel of any of the above embodiments, the selectable display area includes a plurality of display units, one pixel driving circuit is electrically connected to one or more of the display units, the pixel driving circuit further includes a switch controller, and the display units include a light emission control switch, a light emitting element, a high voltage terminal, and a low voltage terminal; the input end of the light-emitting control switch is electrically connected with the high-voltage end, and the light-emitting element is coupled between the output end of the light-emitting control switch and the low-voltage end; the switch controller is respectively electrically connected with the digital memory and the control end of each corresponding light-emitting control switch and is used for controlling the on-off of the light-emitting control switches according to the digital data signals stored in the digital memory.
Referring to fig. 1 and 8, the display area 10 includes a plurality of display units 12, fig. 8 shows a structure in which the pixel driving circuit 11 is electrically connected to one display unit 12, the input terminal of the light-emitting control switch 12a is electrically connected to the high-voltage terminal VDD, and the light-emitting element 12b is coupled between the output terminal of the light-emitting control switch 12a and the low-voltage terminal VEE; the switch controller 11c is electrically connected to the digital memory 11b and the control end of each corresponding light-emitting control switch 12a, and is configured to control the on/off of the light-emitting control switch 12a according to the digital data signal stored in the digital memory 11 b. The optional light emitting element 12b is a light emitting diode LED, but is not limited thereto.
Alternatively, the pixel driving Circuit 11 may be a micro Integrated Circuit (micro Integrated Circuit).
In the present embodiment, the digital data signal of each display unit 12 driven by the pixel driving circuit 11 has been stored in the digital memory 11b in advance, and the display driving chip 20a outputs the clock signal CK to cause the switch controller 11c to control the on time of the corresponding light emission control switch 12a in accordance with the data signal stored in the digital memory 11b, thereby controlling the light emission time of the light emitting element 12b and realizing the current control of the light emitting element 12 b.
Based on the same inventive concept, embodiments of the present invention further provide an electronic device, which includes the display panel according to any of the above embodiments. The optional electronic equipment is display equipment such as a smart phone.
In the display panel provided by this embodiment, the driving circuit of the display unit includes a digital-to-analog conversion unit located in the non-display area and an analog-to-digital conversion unit located in the display area, and the digital-to-analog conversion unit in the non-display area converts the data signal of the display unit into an analog data signal and transmits the analog data signal to the analog-to-digital conversion unit through the data line. The length of the data line in the display panel is usually longer, the data line is adopted to transmit the analog data signal, the transmission time of the data signal on the data line can be reduced, the transmission loss of the data signal on the data line can also be reduced, and the transmission accuracy of the data signal on the data line is improved, so that the transmission pressure of the data signal in the display panel is reduced, and the high-frequency display driving of the display panel is realized.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (6)
1. A display panel, comprising: the display panel comprises a display area and a non-display area, wherein the display area comprises a plurality of pixel driving circuits, the non-display area comprises a plurality of display driving circuits, and the display driving circuits are electrically connected with the pixel driving circuits through data lines and provide data signals for the pixel driving circuits through the data lines;
the display driving circuit comprises a pulse width modulation unit and a digital-to-analog conversion unit, and the pixel driving circuit comprises an analog-to-digital conversion unit and a digital memory;
the digital-to-analog conversion unit is electrically connected with the pulse width modulation unit and is electrically connected with the analog-to-digital conversion unit through the data line, the digital-to-analog conversion unit is used for receiving a digital data signal sent by the pulse width modulation unit and converting the digital data signal into an analog data signal, and the analog data signal is transmitted to the analog-to-digital conversion unit through the data line;
the analog-to-digital conversion unit is electrically connected with the digital memory and is used for converting the analog data signals into digital data signals and transmitting the digital data signals to the digital memory for storage;
the digital-to-analog conversion unit comprises a first digital-to-analog converter and a second digital-to-analog converter, the analog-to-digital conversion unit comprises a first analog-to-digital converter and a second analog-to-digital converter, the data line comprises a first data line and a second data line, the first digital-to-analog converter is electrically connected with the first analog-to-digital converter through the first data line, and the second analog-to-digital converter is electrically connected with the second analog-to-digital converter through the second data line; the digital data signal is an n-bit digital signal; the first digital-to-analog converter is used for converting odd-number digital signals in the digital data signals into first analog data signals and transmitting the first analog data signals to the first analog-to-digital converter, so that the first analog-to-digital converter transmits the converted first digital data signals to the digital memory; the second digital-to-analog converter is used for converting even-numbered digital signals in the digital data signals into second analog data signals and transmitting the second analog data signals to the second analog-to-digital converter, so that the second analog-to-digital converter transmits the converted second digital data signals to the digital memory; alternatively, the first and second electrodes may be,
the digital-to-analog conversion unit comprises a first digital-to-analog converter and a second digital-to-analog converter, the analog-to-digital conversion unit comprises a first analog-to-digital converter and a second analog-to-digital converter, the data line comprises a first data line and a second data line, the first digital-to-analog converter is electrically connected with the first analog-to-digital converter through the first data line, and the second analog-to-digital converter is electrically connected with the second analog-to-digital converter through the second data line; the digital data signal is an n-bit digital signal, and n is an even number; the first digital-to-analog converter is used for converting the 1 st bit to the n/2 th bit digital signals in the digital data signals into first analog data signals and transmitting the first analog data signals to the first analog-to-digital converter, so that the first analog-to-digital converter transmits the converted first digital data signals to the digital memory; the second digital-to-analog converter is used for converting digital signals of (n/2) +1 th bit to nth bit in the digital data signals into second analog data signals and transmitting the second analog data signals to the second analog-to-digital converter, so that the second analog-to-digital converter transmits the converted second digital data signals to the digital memory; alternatively, the first and second electrodes may be,
the digital-to-analog conversion unit comprises a 1 st digital-to-analog converter, the analog-to-digital conversion unit comprises a 1 st analog-to-digital converter, the data lines comprise a 1 st data line and an m th data line, and the ith digital-to-analog converter is electrically connected with the ith analog-to-digital converter through the ith data line; the digital data signal is an n-bit digital signal, m and n are even numbers, and n is a multiple of m; the ith digital-to-analog converter is used for converting an mk + i-th bit digital signal in the digital data signals into an ith analog data signal and transmitting the ith analog data signal to the ith analog-to-digital converter, so that the ith analog-to-digital converter transmits the converted ith digital data signal to the digital memory, wherein i is 1,2, …, m, k is 0,1, …, (n/m) -1; alternatively, the first and second electrodes may be,
the digital-to-analog conversion unit comprises a 1 st digital-to-analog converter, the analog-to-digital conversion unit comprises a 1 st analog-to-digital converter, the data lines comprise a 1 st data line and an m th data line, and the ith digital-to-analog converter is electrically connected with the ith analog-to-digital converter through the ith data line; the digital data signal is an n-bit digital signal, m and n are even numbers, and n is a multiple of m; the ith digital-to-analog converter is used for converting the (ni-n + m)/m bit to the ni/m bit digital signals in the digital data signals into ith analog data signals and transmitting the ith analog data signals to the ith analog-to-digital converter, so that the ith analog-to-digital converter transmits the converted ith digital data signals to the digital memory, wherein i is 1,2, …, m.
2. The display panel according to claim 1, wherein the analog-to-digital conversion unit transmits the digital data signal to the digital memory in a parallel output manner; alternatively, the first and second electrodes may be,
and the analog-to-digital conversion unit transmits the digital data signal to the digital memory in a serial output mode.
3. The display panel of claim 1, wherein the analog-to-digital converter transmits digital data signals to the digital memory in a parallel or serial output manner.
4. The display panel according to claim 1, wherein the non-display region includes a display driving chip, and the plurality of display driving circuits are provided in the display driving chip.
5. The display panel according to claim 1, wherein the display region includes a plurality of display units, one of the pixel driving circuits is electrically connected to one or more of the display units, the pixel driving circuit further includes a switch controller, and the display unit includes a light emission control switch, a light emitting element, a high voltage terminal, and a low voltage terminal;
the input end of the light-emitting control switch is electrically connected with the high-voltage end, and the light-emitting element is coupled between the output end of the light-emitting control switch and the low-voltage end;
the switch controller is respectively electrically connected with the digital memory and the control end of each corresponding light-emitting control switch and is used for controlling the on-off of the light-emitting control switches according to the digital data signals stored in the digital memory.
6. An electronic device characterized by comprising the display panel according to any one of claims 1 to 5.
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