CN111968502A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
- Publication number
- CN111968502A CN111968502A CN202010753392.4A CN202010753392A CN111968502A CN 111968502 A CN111968502 A CN 111968502A CN 202010753392 A CN202010753392 A CN 202010753392A CN 111968502 A CN111968502 A CN 111968502A
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- pixel circuit
- array substrate
- circuit units
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- insulating layer
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The application discloses array substrate and display panel, array substrate includes: a plurality of pixel circuit units; the pixel circuit units are arranged in a staggered mode in the stress stretching direction of the array substrate. Through the design mode, the local stress applied to the array substrate during stretching or bending can be reduced.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate and a display panel.
Background
In recent years, flexible stretchable or foldable array substrates have attracted attention. During the stretching or folding process of the array substrate, the length of the array substrate in the stress stretching direction increases, and the length of the array substrate perpendicular to the stress stretching direction decreases to some extent. Such deformation may cause local stress concentration of the array substrate, thereby causing damage to the array substrate.
Disclosure of Invention
The application provides an array substrate and a display panel, which can reduce local stress applied to the array substrate when the array substrate is stretched or bent.
In order to solve the technical problem, the application adopts a technical scheme that: provided is an array substrate including: a plurality of pixel circuit units; the pixel circuit units are arranged in a staggered mode in the stress stretching direction of the array substrate.
Wherein the pixel circuit units are arranged in a straight line in a direction perpendicular to the stress stretching direction.
In the stress stretching direction, the size of the dislocation of the adjacent pixel circuit units is smaller than the size of the pixel circuit units in the direction perpendicular to the stress stretching direction.
In the stress stretching direction, the size of the dislocation of the adjacent pixel circuit units is 5 to 30 percent of the size of the pixel circuit units in the direction vertical to the stress stretching direction.
The pixel circuit units are arranged in a straight line in a direction perpendicular to the stress stretching direction to form a pixel circuit unit set; in the stress stretching direction, a plurality of adjacent pixel circuit units are grouped into a group, and the dislocation directions of the pixel circuit unit groups in the same group are the same and opposite to the dislocation direction of the adjacent group.
Wherein a plurality of adjacent groups of the pixel circuit unit sets form a repeating unit, and the pixel circuit unit sets in the repeating unit are arranged in a C type or an S type.
In the stress stretching direction, the adjacent pixel circuit units are electrically connected through a conducting wire; the conducting wire parts positioned in the pixel circuit units are parallel to the stress stretching direction, and the conducting wire parts positioned between the adjacent pixel circuit units and the conducting wire parts positioned in the pixel circuit units are obliquely arranged.
The array substrate further comprises an inorganic insulating layer and an organic insulating layer, and the conducting wire part positioned between the adjacent pixel circuit units is positioned between the inorganic insulating layer and the organic insulating layer; the organic insulating layer is provided with a plurality of pixel circuit units, the inorganic insulating layer is provided with at least one groove corresponding to the position between the adjacent pixel circuit units, the conducting wire is provided with a bent part, the organic insulating layer is provided with a protrusion, and the groove is filled with the bent part of the conducting wire and the protrusion of the organic insulating layer together.
Wherein, the orthographic projection of the conducting wire part between two adjacent pixel circuit units on the surface of the inorganic insulating layer is S-shaped, V-shaped or linear.
In order to solve the above technical problem, another technical solution adopted by the present application is: a display panel is provided, comprising the array substrate of any of the above embodiments.
Being different from the prior art situation, the beneficial effect of this application is: the array substrate provided by the application comprises a plurality of pixel circuit units, and the pixel circuit units are arranged in a staggered mode in the stress stretching direction of the array substrate. The dislocation arrangement mode can decompose the tensile stress on the array substrate at the dislocation position, so that the probability of local stress concentration of the array substrate is reduced, and the probability of damage of the array substrate is reduced.
In addition, in the stress stretching direction, the adjacent pixel circuit units are electrically connected through a lead, the lead part positioned in the pixel circuit unit is parallel to the stress stretching direction, and the lead part positioned between the adjacent pixel circuit units is obliquely arranged with the stress stretching direction. When the length of the array substrate is increased along the stress stretching direction in the stretching or folding process, the design mode can enable the wires at the dislocation part to have enough allowance to deal with the deformation, so that the stretching stress applied to the wires at the dislocation part is reduced, the probability of breaking the wires at the dislocation part is reduced, and the probability of damaging the array substrate is further reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic structural diagram of an embodiment of an array substrate according to the present application;
FIG. 2 is a schematic cross-sectional view of one embodiment of the array substrate shown in FIG. 1;
FIG. 3 is a schematic structural diagram of another embodiment of an array substrate of the present application;
FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an embodiment of a display device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of an array substrate of the present application, where the array substrate 10 may include a plurality of pixel circuit units 100, and each pixel circuit unit 100 is used for driving at least one sub-pixel to emit light. Each pixel circuit unit 100 may include a driving transistor, a capacitor, a signal line, and the like, and the pixel circuit unit 100 may have a common driving circuit structure of 7T1C, 7T2C, 2T1C, and the like. In general, the signal lines in the pixel circuit unit 100 may include first signal lines and second signal lines arranged to intersect, the first signal lines may include scanning signal lines, electroluminescence signal lines, and the like, the second signal lines may include data lines, and the like, the capacitors, driving transistors, and the like in the pixel circuit unit 100 may be located in regions where the corresponding first and second signal lines intersect, and the regions where the first and second signal lines intersect may be rectangular, and the like.
The array substrate 10 may generate a tensile stress when being bent along a predetermined bending line or stretched along a predetermined stretching direction, and the pixel circuit units 100 are arranged in a staggered manner in the stress stretching direction (as shown by a hollow arrow in fig. 1) of the array substrate 10. The misalignment refers to that, in the stress stretching direction, the connecting line L1 of the geometric center points of two adjacent pixel circuit units 100 is not parallel to the stress stretching direction, and the geometric center point of the pixel circuit unit 100 can be understood as the geometric center point of the region formed by the intersection of the first signal line and the second signal line in the pixel circuit unit 100.
By the above-mentioned dislocation arrangement, the tensile stress applied to the array substrate 10 is decomposed at the dislocation, so that the probability of local stress concentration of the array substrate 10 is reduced, and the probability of damage to the array substrate 10 is reduced.
In one embodiment, at least one pixel circuit unit 100 is arranged in a staggered manner with respect to other pixel circuit units 100 in the stress stretching direction. Preferably, as shown in fig. 1, any two adjacent pixel circuit units 100 are arranged in a staggered manner in the stress stretching direction. The design method can maximally disperse the tensile stress applied to the array substrate 10, so as to further reduce the probability of local stress concentration of the array substrate 10 and reduce the probability of damage to the array substrate 10.
In another embodiment, with reference to fig. 1, the pixel circuit units 100 are arranged in a straight line perpendicular to the stress stretching direction; that is, the plurality of pixel circuit units 100 are arranged in a straight line along a first direction X, and the plurality of pixel unit cells 100 are arranged in a staggered manner in a second direction Y perpendicular to the first direction X. The design mode can ensure that the arrangement of the pixel circuit units 100 is regular, and the process is easy to prepare.
Further, in the stress stretching direction, a dimension d1 of misalignment between two adjacent pixel circuit units 100 is smaller than a dimension d2 of the pixel circuit unit 100 in the direction perpendicular to the stress stretching direction. In the stress stretching direction, a projection dimension of the geometric center point connecting line L1 of two adjacent pixel circuit units 100 in the direction perpendicular to the stress stretching direction can be regarded as a misalignment dimension d 1. The design method can make the offset between two adjacent pixel circuit units 100 smaller than the width of one pixel circuit unit 100, so as to facilitate the routing and not excessively increase the frame width of the array substrate 10.
Preferably, in the stress stretching direction, the dimension d1 of the misalignment between two adjacent pixel circuit units 100 is 5% to 30% of the dimension d2 of the pixel circuit unit 100 in the direction perpendicular to the stress stretching direction; e.g., 10%, 20%, 30%, etc. The design manner of the proportional range can make the position arrangement of the pixel circuit unit 100 on the array substrate 10 more reasonable and easy to route.
In yet another embodiment, referring again to fig. 1, in a direction perpendicular to the stress stretching direction, a plurality of pixel circuit units 100 arranged in a straight line form a pixel circuit unit set 120; in the stress stretching direction, the adjacent pixel circuit unit sets 120 are in one group, and the dislocation directions between the pixel circuit unit sets 120 in the same group are the same and opposite to the dislocation direction of the pixel circuit unit sets in the adjacent group. For example, five pixel circuit cell sets 120 are shown in fig. 1, wherein the first three pixel circuit cell sets 120 are a first group, and the misalignment direction between the pixel circuit cell sets 120 within the group is to the left; the last two pixel circuit cell sets 120 are a second group, and the misalignment direction between the pixel circuit cell sets 120 within the group is to the right. The design method can reduce the area of the non-display area of the array substrate 10 in the direction perpendicular to the stress stretching direction, so as to reduce the frame width of the array substrate 10.
In this embodiment, the number of the pixel circuit unit sets 120 in adjacent groups may be the same or different, a plurality of pixel circuit unit sets 120 in adjacent groups may form a repeating unit, and the pixel circuit unit sets 120 in the repeating unit are arranged in a C-type or S-type. The above design can make the structure of the array substrate 10 simpler and the manufacturing process easier. In addition, the misalignment degrees between two adjacent pixel circuit unit sets 120 in the repeating unit may be the same, and the misalignment degrees are the ratio of the misalignment sizes mentioned in the above embodiments, and are not described in detail again.
In one application scenario, as shown in fig. 1, a total of five pixel circuit unit sets 120 of two adjacent groups may form a repeating unit, the five pixel circuit unit sets 120 in the repeating unit are divided into two groups, the offset direction of one group is left, and the offset direction of one group is right, so as to form a C-shape. And the dislocation degree between two adjacent pixel circuit unit sets 120 in the repeating unit is the same, and the dislocation degree between the head and tail two pixel circuit unit sets 120 is zero. Of course, in other embodiments, the C-type repeating unit may be formed by more or fewer pixel circuit unit sets 120. When the number of the pixel circuit unit sets 120 in the repeating unit is odd, the other pixel circuit unit sets 120 in the repeating unit may be arranged in axial symmetry with respect to the middle row of the pixel circuit unit sets 120 in the repeating unit.
In another application scenario, a total of N pixel circuit unit sets 120 of three adjacent groups may form a repeating unit, and the misalignment direction of one group in the repeating unit is left, the misalignment direction of one group is right, and the misalignment direction of the other group is left, so as to form an S-shape. And the degree of misalignment between two adjacent sets of pixel circuit cells 120 within a repeating unit is the same. The above design can make the structure of the array substrate 10 simpler and the manufacturing process easier.
In another embodiment, referring to fig. 1 again, in the stress stretching direction, the adjacent pixel circuit units 100 are electrically connected to each other through a conducting wire 102. In this embodiment, the conductive line 102 may be referred to as a signal line, and may be specifically any one of a data line, a scan line, an electroluminescent signal line, and the like. The wires 102 connecting at least two pixel circuit units 100 extend into the pixel circuit units 100, the wire portions 102a in the pixel circuit units 100 are parallel to the stress stretching direction, and the wire portions 102b between adjacent pixel circuit units 100 are inclined from the wire portions 102a in the pixel circuit units 100. When the length of the array substrate 10 in the stretching direction of the stress increases during the stretching or folding process, the above design manner may allow the wire portion 102b between at least two pixel circuit units 100 to have enough margin to cope with the deformation, thereby reducing the tensile stress applied to the wire portion 102b between two pixel circuit units 100, reducing the probability of breaking the wire portion 102b, and further reducing the probability of damaging the array substrate 10.
In another embodiment, referring to fig. 2, fig. 2 is a schematic cross-sectional view of an embodiment of the array substrate of fig. 1. In the present embodiment, the array substrate 10 further includes an inorganic insulating layer 220 and an organic insulating layer 222, and in the stress stretching direction, the wire portion 102b between the adjacent pixel circuit units 100 is between the inorganic insulating layer 220 and the organic insulating layer 222; at least one groove (not labeled) is formed in the inorganic insulating layer 220 corresponding to the position between the adjacent pixel circuit units 100; the shape of the groove may be an inverted trapezoid in fig. 2, or the like, in the direction from the inorganic insulating layer 220 to the organic insulating layer 222. The above design can reduce the amount of the inorganic insulating layer having a larger elastic modulus between the adjacent pixel circuit units 100 in the stress stretching direction, and can reduce the possibility of stress concentration between the adjacent pixel circuit units 100.
Further, the conductive line 102 extends along the surface of the groove, and has a curved portion C1, the organic insulation layer 222 has a protrusion C2, and the curved portion C1 of the conductive line 102 and the protrusion C2 of the organic insulation layer 222 together fill the groove. Generally, the organic insulating layer 222 has a low elastic modulus and good flexibility and buffering, and when the groove is filled with the organic insulating layer 222, the organic insulating layer 222 at the position of the groove can buffer the stress at the position to reduce the possibility of stress concentration.
Preferably, the orthogonal projection of the conductive line portion 102b between two adjacent pixel circuit units 100 on the surface of the inorganic insulating layer 220 is S-shaped, V-shaped or linear. This design can make the wiring simpler and is helpful to reduce the stress between adjacent pixel circuit units 100.
For example, as shown in fig. 1, in at least two pixel circuit units 100 connected by the same wire 102 in the stress stretching direction, the orthogonal projection of the wire portion 102b between two adjacent pixel circuit units 100 on the surface of the inorganic insulating layer 220 is in a tilted linear shape.
For another example, as shown in fig. 3, fig. 3 is a schematic structural diagram of another embodiment of the array substrate of the present application. In at least two pixel circuit units 100a connected by the same wire 102c in the stress stretching direction, the orthogonal projection of the wire portion 102d between two adjacent pixel circuit units 100a on the surface of the inorganic insulating layer 220 is V-shaped. In fig. 3, the orthogonal projection of the conducting line portion 102d between two adjacent pixel circuit units 100a on the surface of the inorganic insulating layer 220 is a V shape, and in other embodiments, the orthogonal projection may be a plurality of continuous V shapes, i.e. a zigzag shape.
In a specific embodiment, as shown in fig. 1, the pixel circuit units 100 in the array substrate 10 are arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y are perpendicular to each other.
When the stress stretching direction of the array substrate 10 is parallel to the second direction Y, the plurality of pixel circuit units 100 may be linearly arranged along the first direction X; and in the second direction Y, adjacent pixel circuit units 100 may be arranged with a shift therebetween. The conductive line 102 may include a data line extending substantially in the second direction Y, and a scan line and an electric signal light emitting signal line extending in the first direction X, and a portion of the data line between the adjacent pixel circuit units 100 may be inclined to each other in the first and second directions X and Y.
Similarly, when the stress stretching direction of the array substrate 10 is parallel to the first direction X, the plurality of pixel circuit units 100 may be linearly arranged along the first direction Y; and in the first direction X, adjacent pixel circuit units 100 may be disposed with a misalignment therebetween. The conductive line 102 may include a data line extending in the second direction Y and a scan line and an electro-luminescence signal line extending substantially in the first direction X, and at this time, portions of the scan line and the electro-luminescence signal line between the adjacent pixel circuit units 100 may be inclined to each other with respect to the first direction X and the second direction Y.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of a display panel according to the present application. The display panel 20 includes the array substrate in any of the above embodiments. In addition, the display panel 20 may further include a light emitting layer, where the light emitting layer includes a plurality of sub-pixels 22, and one sub-pixel 22 may be electrically connected to one pixel circuit unit 24. On the plane of the array substrate, the projection of the sub-pixels 22 may or may not at least partially overlap with the projection position of the pixel circuit unit 24, that is, the arrangement of the sub-pixels 22 may or may not be shifted in the stress stretching direction, which is not limited in this application.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of a display device according to the present application. The display device may include the display panel in the above embodiments, and the display device 30 may be a mobile phone, a tablet, or the like.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.
Claims (10)
1. An array substrate, comprising:
a plurality of pixel circuit units;
the pixel circuit units are arranged in a staggered mode in the stress stretching direction of the array substrate.
2. The array substrate of claim 1,
the pixel circuit units are linearly arranged in a direction perpendicular to the stress stretching direction.
3. The array substrate of claim 2,
in the stress stretching direction, the size of the dislocation of the adjacent pixel circuit units is smaller than the size of the pixel circuit units in the direction perpendicular to the stress stretching direction.
4. The array substrate of claim 3,
in the stress stretching direction, the size of the dislocation of the adjacent pixel circuit units is 5 to 30 percent of the size of the pixel circuit units in the direction vertical to the stress stretching direction.
5. The array substrate of claim 2,
in the direction perpendicular to the stress stretching direction, a plurality of pixel circuit units which are arranged in a straight line form a pixel circuit unit set;
in the stress stretching direction, a plurality of adjacent pixel circuit units are grouped into a group, and the dislocation directions of the pixel circuit unit groups in the same group are the same and opposite to the dislocation direction of the pixel circuit unit groups in the adjacent group.
6. The array substrate of claim 5,
the pixel circuit unit sets of a plurality of adjacent groups form a repeating unit, and the pixel circuit unit sets in the repeating unit are arranged in a C type or an S type.
7. The array substrate of claim 2,
in the stress stretching direction, the adjacent pixel circuit units are electrically connected through a conducting wire; the conducting wire parts positioned in the pixel circuit units are parallel to the stress stretching direction, and the conducting wire parts positioned between the adjacent pixel circuit units and the conducting wire parts positioned in the pixel circuit units are obliquely arranged.
8. The array substrate of claim 7,
the array substrate further comprises an inorganic insulating layer and an organic insulating layer, and the conducting wire part positioned between the adjacent pixel circuit units is positioned between the inorganic insulating layer and the organic insulating layer;
the organic insulating layer is provided with a plurality of pixel circuit units, the inorganic insulating layer is provided with at least one groove corresponding to the position between the adjacent pixel circuit units, the conducting wire is provided with a bent part, the organic insulating layer is provided with a protrusion, and the groove is filled with the bent part of the conducting wire and the protrusion of the organic insulating layer together.
9. The array substrate of claim 8,
the orthographic projection of the wire part between two adjacent pixel circuit units on the surface of the inorganic insulating layer is S-shaped, V-shaped or linear.
10. A display panel, comprising: an array substrate as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010753392.4A CN111968502A (en) | 2020-07-30 | 2020-07-30 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010753392.4A CN111968502A (en) | 2020-07-30 | 2020-07-30 | Array substrate and display panel |
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| CN111968502A true CN111968502A (en) | 2020-11-20 |
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| CN202010753392.4A Pending CN111968502A (en) | 2020-07-30 | 2020-07-30 | Array substrate and display panel |
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| CN109830504A (en) * | 2019-01-08 | 2019-05-31 | 云谷（固安）科技有限公司 | Stretchable display structure and its manufacturing method and display device |
| CN111326067A (en) * | 2018-12-13 | 2020-06-23 | 昆山工研院新型平板显示技术中心有限公司 | Display panel, manufacturing method thereof and display device |
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| US20070019143A1 (en) * | 2005-07-20 | 2007-01-25 | Industrial Technology Research Institute | Pixel array with flexible circuit layout |
| US20090051640A1 (en) * | 2007-08-21 | 2009-02-26 | Masahiro Tanaka | Display Device |
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