CN111966298B - Reverse programming implementation method and device based on Flash memory - Google Patents
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Abstract
The invention discloses a reverse order programming realization method and a device based on a Flash memory, wherein the method comprises the following steps: detecting a data writing instruction, and acquiring a data writing state; judging whether the data writing state is reverse writing; and if the data writing state is reverse-order writing, the data writing address is mapped to the reverse-order physical block, and the mapping relation between the data and the address mapping reverse-order physical block is stored in the block mapping table. The embodiment of the invention improves the random writing performance of the nand flash storage device based on the block management algorithm, particularly aims at that the reverse-order continuous writing data can be completely the same as the sequential writing performance, reduces the writing limit of the nand flash storage device and improves the writing efficiency of the nand flash storage device.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a reverse programming implementation method and device based on a Flash memory.
Background
The Nand Flash memory is one of Flash memories, adopts a nonlinear macro-unit mode in the Nand Flash memory, and provides a cheap and effective solution for realizing a solid-state large-capacity memory. The Nand-flash memory has the advantages of large capacity, high rewriting speed and the like, is suitable for storing a large amount of data, and is widely applied in the industry.
The mainstream implementation method of the management algorithm of the Nand Flash memory at present is a block management and page management algorithm. A memory has a plurality of physical blocks, and a plurality of physical pages are arranged in one physical block. There are several physical partitions within a physical page. In the prior art, when a Nand Flash memory is programmed, data can only be written in physical blocks according to the sequence of addresses from large to small, and if data is written in a certain physical block, the data cannot be read correctly, so that inconvenience is brought to programming of the Nand Flash memory by a user.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
In view of the defects of the prior art, the present invention aims to provide a method and an apparatus for implementing reverse programming based on a Flash memory, and aims to solve the technical problem that when a Nand Flash memory in the prior art is programmed, data can only be written in physical blocks according to the sequence from large to small of addresses, and when data is written, data can not be correctly read if a certain physical block writes data in a reverse sequence.
The technical scheme of the invention is as follows:
a reverse programming implementation method based on a Flash memory comprises the following steps:
detecting a data writing instruction, and acquiring a data writing state;
judging whether the data writing state is reverse writing;
and if the data writing state is reverse-order writing, the data writing address is mapped to the reverse-order physical block, and the mapping relation between the data and the address mapping reverse-order physical block is stored in the block mapping table.
Further, after determining whether the data writing state is the reverse writing, the method further includes:
if the data is written in the state sequence, the data is fixed into the address mapping sequence physical block, and the mapping relation between the data and the address mapping sequence physical block is stored in the block mapping table.
Further preferably, if the data writing status is reverse writing, writing the data into the reverse physical block mapped by the address, and storing the mapping relationship between the data and the reverse physical block mapped by the address into the block mapping table, including:
if the data writing state is reverse-order writing, mapping the data writing address to a reverse-order physical block, and judging whether the reverse-order physical block is completely written;
if the data is written, storing the mapping relation between the data and the address mapping reverse order physical block to a block mapping table;
if the data is not written completely, whether the data writing state is written in the reverse order or not is continuously detected until the data of the reverse order physical block is written completely, and the mapping relation between the data and the address mapping reverse order physical block is stored in the block mapping table.
Further preferably, if the data writing state is reverse writing, writing the data into the address mapping reverse physical block, and storing the mapping relationship between the data and the address mapping reverse physical block to the block mapping table, includes:
if the data writing state is reverse-order writing, acquiring a reverse-order physical block with an address mapped to a reverse order, and writing the data into the reverse-order physical block;
and reading the data of the reverse order physical block, mapping the data to the order physical block according to the order, and storing the order physical block in a block mapping table.
Preferably, if the data writing status is reverse order writing, acquiring a reverse order physical block whose address is mapped to a reverse order, and writing the data into the reverse order physical block includes:
and if the data writing state is reverse-order writing, taking out the idle block from the idle block queue, marking the idle block as a reverse-order physical block with an address mapped into a reverse order, and writing the data into the reverse-order physical block.
Further, the reading data of the reverse physical block, mapping the data to the sequential physical block according to the order, and storing the sequential physical block in the block mapping table includes:
taking out a free block from the free queue, wherein the free block is marked as a sequential physical block with an address mapped as a sequence;
reading data of the reverse physical block, and mapping the data to the sequential physical block according to the sequence;
the sequential physical blocks are stored in a block mapping table.
Further, the reading the data of the reverse physical block, and mapping to the sequential physical block according to the order specifically includes:
reading data of the reverse physical block, and mapping the data to the sequential physical block according to the sequence;
and putting the reverse order physical block into a free block queue.
The invention also provides a device for realizing reverse-order programming based on the Flash memory, which comprises at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the above-described reverse order programming implementation method based on Flash memory.
Another embodiment of the present invention also provides a non-volatile computer-readable storage medium storing computer-executable instructions that, when executed by one or more processors, may cause the one or more processors to perform the above-described method for implementing reverse-order programming based on Flash memory.
Another embodiment of the present invention provides a computer program product comprising a computer program stored on a non-volatile computer-readable storage medium, the computer program comprising program instructions that, when executed by a processor, cause the processor to perform the above-described Flash memory-based reverse order programming implementation method.
Has the advantages that: the embodiment of the invention improves the random writing performance of the nand flash storage device based on the block management algorithm, particularly aims at that the reverse-order continuous writing data can be completely the same as the sequential writing performance, reduces the writing limit of the nand flash storage device and improves the writing efficiency of the nand flash storage device.
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The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a flow chart of a preferred embodiment of a reverse programming implementation method based on a Flash memory according to the present invention;
FIG. 2 is a schematic diagram of address mapping according to a preferred embodiment of a reverse programming implementation method based on a Flash memory according to the present invention;
FIG. 3 is a schematic diagram of a hardware structure of a reverse programming implementation apparatus based on a Flash memory according to a preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Embodiments of the present invention will be described below with reference to the accompanying drawings.
The embodiment of the invention provides a reverse programming implementation method based on a Flash memory. Referring to fig. 1, fig. 1 is a flowchart illustrating a method for implementing reverse programming based on a Flash memory according to a preferred embodiment of the present invention. As shown in fig. 1, it includes the steps of:
s100, detecting a data writing instruction, and acquiring a data writing state;
step S200, judging whether the data writing state is reverse writing, if so, executing step S300, and if not, executing step S400;
step S300, writing data into the address mapping reverse order physical block, and storing the mapping relation between the data and the address mapping reverse order physical block into a block mapping table;
step S400, the data is fixed into the address mapping sequence physical block, and the mapping relation between the data and the address mapping sequence physical block is stored in the block mapping table.
In specific implementation, the embodiment of the invention is applied to flash memory erasing equipment. In particular to a Flash Translation Layer (FTL) management algorithm. Taking the model MT29F4G08BxB as an example, an NAND FLASH structure consists of 4096 blocks, one block consists of 64 pages, and one page consists of 4 vectors.
As shown in fig. 2, an address mapping diagram of a preferred embodiment of a reverse programming implementation method based on a Flash memory is provided, where one logical address has N addresses, one logical address includes M +1 logical blocks, each logical block has 100 data blocks, and a mapping relationship between a physical block and a logical block can be set by itself. For example, logical block 0 may correspond to physical block 2, logical block 1 may correspond to physical block 0, and logical block 0 may be written first when data is written, so as to implement processing the contents of physical block 2 first.
And detecting a data writing state when a data writing instruction of the flash memory is detected, if the data writing state is reverse writing, writing data into an address mapping reverse physical block, and storing a mapping relation between the data and the address mapping reverse physical block into a block mapping table.
If the data writing state is sequential writing, mapping the data writing address into a sequential physical block, and storing the mapping relation between the data and the address mapping sequential physical block into a block mapping table. Therefore, both data sequence and reverse sequence can be written, and the writing efficiency of the flash memory device is improved.
Further, if the data writing state is reverse writing, writing the data into the address mapping reverse physical block, and storing the mapping relationship between the data and the address mapping reverse physical block to the block mapping table, including:
if the data writing state is reverse-order writing, mapping the data writing address to a reverse-order physical block, and judging whether the reverse-order physical block is completely written;
if the data is written, storing the mapping relation between the data and the address mapping reverse order physical block to a block mapping table;
if the data is not written completely, whether the data writing state is written in the reverse order or not is continuously detected until the data of the reverse order physical block is written completely, and the mapping relation between the data and the address mapping reverse order physical block is stored in the block mapping table.
During specific implementation, when data is written, the data is written into the address mapping physical block, whether the reverse order physical block is written completely or not is judged, if the data is written completely, the mapping relation between the data and the address mapping reverse order physical block is stored into the block mapping table, and if the data is not written completely, whether the data writing state is written reversely or not is continuously detected until the data of the reverse order physical block is written completely, and the mapping relation between the data and the address mapping reverse order physical block is stored into the block mapping table.
Further, if the data writing state is reverse writing, writing the data into the address mapping reverse physical block, and storing the mapping relationship between the data and the address mapping reverse physical block to the block mapping table, including:
if the data writing state is reverse-order writing, acquiring a reverse-order physical block with an address mapped to a reverse order, and writing the data into the reverse-order physical block;
and reading the data of the reverse order physical block, mapping the data to the order physical block according to the order, and storing the order physical block in a block mapping table.
In specific implementation, if the data writing state is reverse-order writing, a reverse-order physical block with an address mapped to a reverse order is obtained, the data is written into the reverse-order physical block, after the reverse-order physical block is written, the data of the reverse-order physical block is read out, the sequential physical block is written according to sequential mapping, and the sequential physical block is stored in a block mapping table.
Further, if the data writing state is reverse order writing, acquiring a reverse order physical block with an address mapped to a reverse order, and writing the data into the reverse order physical block, including:
and if the data writing state is reverse-order writing, taking out the idle block from the idle block queue, marking the idle block as a reverse-order physical block with an address mapped into a reverse order, and writing the data into the reverse-order physical block.
In specific implementation, if the data writing state is reverse-order writing, taking out the idle block from the idle block queue, and marking the idle block as a physical block with an address mapped to be a reverse order; the data is written to the reverse order physical block.
Further, reading data of the reverse order physical block, mapping the data to the order physical block according to the order, and storing the order physical block in the block mapping table, including:
taking out a free block from the free queue, wherein the free block is marked as a sequential physical block with an address mapped as a sequence;
reading data of the reverse physical block, and mapping the data to the sequential physical block according to the sequence;
the sequential physical blocks are stored in a block mapping table.
In specific implementation, acquiring a sequential physical block which is marked as an address mapping sequence from an idle queue and is taken out; reading the data of the reverse physical block, and writing the data into the sequential physical block according to sequential mapping; and storing the sequential physical blocks into a block mapping table.
Further, reading data of the reverse physical block, and mapping the data to the sequential physical block according to the sequence, specifically including:
reading data of the reverse physical block, and mapping the data to the sequential physical block according to the sequence;
and putting the reverse order physical block into a free block queue.
In specific implementation, acquiring an idle block from an idle block queue; marking the free blocks; and recording the marked physical blocks as reverse-order physical blocks with addresses mapped to reverse orders. Writing data in the reverse order physical port; acquiring a sequential physical block which is marked as an address mapping sequence from an idle block in an idle queue; reading the data of the reverse physical block, and writing the data into the sequential physical block according to sequential mapping; putting the reverse order physical block into an idle block queue; and storing the sequential physical blocks into a block mapping table.
As can be seen from the above method embodiments, the embodiment of the present invention provides a method for implementing reverse programming based on a Flash memory, where a data write-in state is obtained by detecting a data write-in instruction; judging whether the data writing state is reverse writing; and if the data writing state is reverse-order writing, the data writing address is mapped to the reverse-order physical block, and the mapping relation between the data and the address mapping reverse-order physical block is stored in the block mapping table. The embodiment of the invention improves the random writing performance of the nand flash storage device based on the block management algorithm, particularly aims at that the reverse-order continuous writing data can be completely the same as the sequential writing performance, reduces the writing limit of the nand flash storage device and improves the writing efficiency of the nand flash storage device.
It should be noted that, a certain order does not necessarily exist between the above steps, and those skilled in the art can understand, according to the description of the embodiment of the present invention, that in different embodiments, the above steps may have different execution orders, that is, may be executed in parallel, may be executed interchangeably, and the like.
Another embodiment of the present invention provides a device for implementing reverse programming based on a Flash memory, as shown in fig. 3, the device 10 includes:
one or more processors 110 and a memory 120, where one processor 110 is illustrated in fig. 3, the processor 110 and the memory 120 may be connected by a bus or other means, and the connection by the bus is illustrated in fig. 3.
The processor 110 is used to implement the various control logic of the apparatus 10, which may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a single chip, an ARM (Acorn RISC machine) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. Also, the processor 110 may be any conventional processor, microprocessor, or state machine. Processor 110 may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The memory 120 is a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions corresponding to the Flash memory-based reverse programming implementation method in the embodiment of the present invention. The processor 110 executes various functional applications and data processing of the apparatus 10 by running the nonvolatile software programs, instructions and units stored in the memory 120, that is, implements the Flash memory-based reverse order programming implementation method in the above-described method embodiments.
The memory 120 may include a storage program area and a storage data area, wherein the storage program area may store an application program required for operating the device, at least one function; the storage data area may store data created according to the use of the device 10, and the like. Further, the memory 120 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 120 optionally includes memory located remotely from processor 110, which may be connected to device 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more units are stored in the memory 120, and when executed by the one or more processors 110, perform the Flash memory-based reverse order programming implementation method in any of the above-described method embodiments, for example, perform the above-described method steps S100 to S400 in fig. 1.
Embodiments of the present invention provide a non-transitory computer-readable storage medium storing computer-executable instructions for execution by one or more processors, e.g., to perform method steps S100-S400 of fig. 1 described above.
By way of example, non-volatile storage media can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as Synchronous RAM (SRAM), dynamic RAM, (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The disclosed memory components or memory of the operating environment described herein are intended to comprise one or more of these and/or any other suitable types of memory.
Another embodiment of the present invention provides a computer program product comprising a computer program stored on a non-volatile computer-readable storage medium, the computer program comprising program instructions that, when executed by a processor, cause the processor to perform the method for Flash memory based reverse order programming implementation of the above-described method embodiments. For example, the method steps S100 to S400 in fig. 1 described above are performed.
The above-described embodiments are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the embodiment.
Through the above description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a general hardware platform, and may also be implemented by hardware. Based on such understanding, the above technical solutions essentially or contributing to the related art can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of the various embodiments or some parts of the embodiments.
Conditional language such as "can," "might," or "may" is generally intended to convey that a particular embodiment can include (yet other embodiments do not include) particular features, elements, and/or operations, among others, unless specifically stated otherwise or otherwise understood within the context as used. Thus, such conditional language is also generally intended to imply that features, elements, and/or operations are in any way required for one or more embodiments or that one or more embodiments must include logic for deciding, with or without input or prompting, whether such features, elements, and/or operations are included or are to be performed in any particular embodiment.
What has been described herein in this specification and the accompanying drawings includes examples that can provide a Flash memory based reverse order programming implementation method and apparatus. It will, of course, not be possible to describe every conceivable combination of components and/or methodologies for purposes of describing the various features of the disclosure, but it can be appreciated that many further combinations and permutations of the disclosed features are possible. It is therefore evident that various modifications can be made to the disclosure without departing from the scope or spirit thereof. In addition, or in the alternative, other embodiments of the disclosure may be apparent from consideration of the specification and drawings and from practice of the disclosure as presented herein. It is intended that the examples set forth in this specification and the drawings be considered in all respects as illustrative and not restrictive. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (6)
1. A reverse programming implementation method based on a Flash memory is characterized by comprising the following steps:
detecting a data writing instruction, and acquiring a data writing state;
judging whether the data writing state is reverse writing;
if the data writing state is reverse-order writing, the data is written into the address mapping reverse-order physical block, and the mapping relation between the data and the address mapping reverse-order physical block is stored in a block mapping table;
after judging whether the data writing state is the reverse writing, the method further comprises the following steps:
if the data is written in the state sequence, writing the data into the address mapping sequence physical block, and storing the mapping relation between the data and the address mapping sequence physical block into a block mapping table;
if the data writing state is reverse-order writing, the data writing address is mapped to a reverse-order physical block, and the mapping relation between the data and the address mapping reverse-order physical block is stored in a block mapping table, which comprises the following steps:
if the data writing state is reverse-order writing, mapping the data writing address to a reverse-order physical block, and judging whether the reverse-order physical block is completely written;
if the data is written, storing the mapping relation between the data and the address mapping reverse order physical block to a block mapping table;
if the data is not completely written, continuously detecting whether the data writing state is written in the reverse order or not until the data of the reverse order physical block is completely written, and storing the mapping relation between the data and the address mapping reverse order physical block to a block mapping table;
if the data writing state is reverse-order writing, the data writing address is mapped to a reverse-order physical block, and the mapping relation between the data and the address mapping reverse-order physical block is stored in a block mapping table, which comprises the following steps:
if the data writing state is reverse-order writing, acquiring a reverse-order physical block with an address mapped to a reverse order, and writing the data into the reverse-order physical block;
and reading the data of the reverse order physical block, mapping the data to the order physical block according to the order, and storing the order physical block in a block mapping table.
2. The method for implementing reverse-order programming based on the Flash memory according to claim 1, wherein if the data writing status is reverse-order writing, the method for obtaining the reverse-order physical block with the address mapped as the reverse order and writing the data into the reverse-order physical block comprises the following steps:
and if the data writing state is reverse-order writing, taking out the idle block from the idle block queue, marking the idle block as a reverse-order physical block with an address mapped into a reverse order, and writing the data into the reverse-order physical block.
3. The method for implementing reverse order programming based on Flash memory according to claim 2, wherein the reading data of the reverse order physical block, mapping to the sequential physical block in order, and storing the sequential physical block in the block mapping table includes:
taking out a free block from the free queue, wherein the free block is marked as a sequential physical block with an address mapped as a sequence;
reading data of the reverse physical block, and mapping the data to the sequential physical block according to the sequence;
the sequential physical blocks are stored in a block mapping table.
4. The method for implementing reverse-order programming based on the Flash memory according to claim 3, wherein the reading of the data of the reverse-order physical block is mapped to the sequential physical block in order, and specifically comprises:
reading data of the reverse physical block, and mapping the data to the sequential physical block according to the sequence;
and putting the reverse order physical block into a free block queue.
5. The device for realizing reverse programming based on the Flash memory is characterized by comprising at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the Flash memory based reverse order programming implementation method of any one of claims 1-4.
6. A non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by one or more processors, cause the one or more processors to perform the Flash memory-based reverse order programming implementation method of any one of claims 1-4.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102067237A (en) * | 2008-06-16 | 2011-05-18 | 桑迪士克以色列有限公司 | Reverse order page writing in flash memories |
| CN102135943A (en) * | 2011-03-23 | 2011-07-27 | 华为终端有限公司 | Storing and accessing method of flash memory data and device thereof |
| CN102819494A (en) * | 2012-07-18 | 2012-12-12 | 山东华芯半导体有限公司 | Optimization method for writing in flash memory in sequence |
| CN107256196A (en) * | 2017-06-13 | 2017-10-17 | 北京中航通用科技有限公司 | The caching system and method for support zero-copy based on flash array |
| CN108614781A (en) * | 2016-12-09 | 2018-10-02 | 北京京存技术有限公司 | Valid data lookup method based on NANDflash and NANDflash storage devices |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10126964B2 (en) * | 2017-03-24 | 2018-11-13 | Seagate Technology Llc | Hardware based map acceleration using forward and reverse cache tables |
| CN108415853A (en) * | 2018-03-15 | 2018-08-17 | 深圳市江波龙电子有限公司 | A kind of method, apparatus and storage device of garbage reclamation |
| CN108536616B (en) * | 2018-03-28 | 2021-10-15 | 华中科技大学 | Mapping method for improving PCM data encryption writing performance and service life |
| CN111190835B (en) * | 2019-12-29 | 2022-06-10 | 北京浪潮数据技术有限公司 | Data writing method, device, equipment and medium |
-
2020
- 2020-08-24 CN CN202010858452.9A patent/CN111966298B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102067237A (en) * | 2008-06-16 | 2011-05-18 | 桑迪士克以色列有限公司 | Reverse order page writing in flash memories |
| CN102135943A (en) * | 2011-03-23 | 2011-07-27 | 华为终端有限公司 | Storing and accessing method of flash memory data and device thereof |
| CN102819494A (en) * | 2012-07-18 | 2012-12-12 | 山东华芯半导体有限公司 | Optimization method for writing in flash memory in sequence |
| CN108614781A (en) * | 2016-12-09 | 2018-10-02 | 北京京存技术有限公司 | Valid data lookup method based on NANDflash and NANDflash storage devices |
| CN107256196A (en) * | 2017-06-13 | 2017-10-17 | 北京中航通用科技有限公司 | The caching system and method for support zero-copy based on flash array |
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