CN111952360B - Field effect transistor and preparation method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a field effect transistor and a preparation method thereof. The field effect transistor comprises an epitaxial layer, a gate dielectric layer, a gate field plate, a source electrode and a drain electrode, wherein the epitaxial layer comprises a substrate, and a channel layer, a barrier layer and a passivation layer which are sequentially stacked on the substrate; a window exposing part of the passivation layer is arranged in the gate dielectric layer, the side wall of the window close to the drain electrode is provided with a breakdown voltage enhancement structure, and in the breakdown voltage enhancement structure, the distance between the side wall and the drain electrode is gradually reduced along the direction far away from the passivation layer; a gate field plate covers the sidewalls of the opening and contacts the passivation layer. The field effect transistor can effectively solve the problem that a grid electrode is close to a drain electrode and has a very high electric field peak value, and the breakdown voltage of the field effect transistor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor field effect transistors, in particular to a field effect transistor and a preparation method thereof.
Background
The gallium nitride material and the device have the superior performances of high frequency, high efficiency, high pressure resistance, high temperature resistance, strong radiation resistance and the like, and meet the national important strategic demands of energy conservation, emission reduction, intelligent manufacturing, information safety and the like. The method is particularly suitable for manufacturing high-voltage-resistant, high-temperature-resistant, high-frequency and high-power electronic devices, for example, a field effect transistor is one of the most representative electronic devices.
Conventional field effect transistors typically include a passivation layer disposed below a gate electrode, and a barrier layer and a channel layer disposed below the passivation layer, with a two-dimensional electron gas (2 DEG) formed between the barrier layer and the channel layer. However, the field effect transistor with the structure has the inherent defect that the distribution of the electric field intensity in the channel of the device is distorted, and particularly, an extremely high electric field peak exists near a grid electrode and a drain electrode, so that the actual breakdown voltage of the device during operation is far lower than the theoretical expected value.
Disclosure of Invention
Based on the above, there is a need to further design the gate dielectric layer structure of the field effect transistor to improve the breakdown voltage of the device, and a corresponding preparation method is provided.
A field effect transistor comprises an epitaxial layer, a gate dielectric layer, a gate field plate, a source electrode and a drain electrode, wherein the epitaxial layer comprises a substrate, and a channel layer, a barrier layer and a passivation layer which are sequentially stacked on the substrate;
a window exposing a part of the passivation layer is arranged in the gate dielectric layer, the side wall of the window close to the drain electrode is provided with a breakdown voltage enhancement structure, and the distance between the side wall and the drain electrode is gradually reduced along the direction far away from the passivation layer in the breakdown voltage enhancement structure;
the gate field plate covers a sidewall of the window and contacts the passivation layer.
In one embodiment, the breakdown voltage enhancement structure has a variation in which a distance between the sidewall and the drain continuously decreases in a direction away from the passivation layer.
In one embodiment, in the variation section, the continuous decreasing manner is a linear decreasing manner.
In one embodiment, the breakdown voltage enhancement structure has a plurality of the variation segments, and the sidewalls of adjacent variation segments are connected in a plane parallel to the passivation layer.
In one embodiment, the included angle between the connecting line of the bottom end and the top end of each change section and the surface of the passivation layer is less than or equal to 60 degrees.
In one embodiment, the height difference between the bottom end and the top end of the change section is
In one embodiment, the material of the gate dielectric layer is silicon dioxide, the silicon dioxide crystal lattice has crystal lattice defects, and in a single variation section, the farther away from the passivation layer, the more defects are in the silicon dioxide crystal lattice; and/or
The thickness of the gate dielectric layer is
In one embodiment, the material of the passivation layer is silicon nitride; and/or
The thickness of the passivation layer is
In one embodiment, a buffer layer is further disposed between the substrate and the channel layer, and the material of the buffer layer is gallium nitride.
In one embodiment, the sidewall of the window near the source is also provided with a structure corresponding to the breakdown voltage enhancement structure.
Further, a preparation method of the field effect transistor comprises the following steps: preparing an epitaxial layer, wherein the epitaxial layer comprises a substrate, and a channel layer, a barrier layer and a passivation layer which are sequentially stacked on the substrate, preparing a gate dielectric layer on the passivation layer, and preparing a source electrode and a drain electrode on two sides of the gate dielectric layer respectively;
the preparation of the gate dielectric layer comprises the following preparation steps: depositing a gate dielectric material, forming a mask on the surface of the gate dielectric material, etching the gate dielectric material to form a window which exposes part of the passivation layer, forming a breakdown voltage enhancement structure on the side wall of the window close to the drain electrode, wherein in the breakdown voltage enhancement structure, the distance between the side wall and the drain electrode is gradually reduced along the direction far away from the passivation layer.
In one embodiment, the preparation of the gate dielectric layer further comprises a step of performing ion implantation on the gate dielectric material before etching the gate dielectric material, wherein the etching is wet etching.
In one embodiment, the manufacturing step is repeated for a plurality of times, and the mask in the subsequent manufacturing step also covers a part of the area not covered by the mask in the previous manufacturing process, so as to form a gate dielectric layer with a plurality of variation sections, wherein the distance between the side wall and the drain electrode is continuously reduced along the direction far away from the passivation layer in the variation sections.
In one embodiment, the ion source used for ion implantation has one or more elements selected from boron, phosphorus, arsenic, and argon; and/or
The dose of the ion implantation is 10 12 ～10 15 Per cm 2 (ii) a And/or
The energy of the ion implantation is 40 keV-150 keV.
In one embodiment, the gate dielectric material is silicon dioxide; the etchant used for the wet etching is an etchant containing hydrofluoric acid.
In one embodiment, the gate dielectric layer is deposited by a method selected from low pressure chemical vapor deposition or metal organic compound vapor deposition.
In another aspect, a field effect transistor according to any one of the above embodiments or a field effect transistor manufactured by the method according to any one of the above embodiments is used for manufacturing an integrated circuit.
In the field effect transistor, the window in the gate dielectric layer is arranged to be a breakdown voltage enhancement structure along the direction far away from the passivation layer, the distance between the side wall and the drain is gradually reduced, the gate field plate covers the side wall of the window of the gate dielectric layer, and the gate field plate with the structure can improve the breakdown voltage of the device as much as possible by regulating and controlling the reduction amplitude of the distance and the reduction mode.
Drawings
FIG. 1 illustrates an embodiment of a field effect transistor;
fig. 2 is a schematic diagram of a process for manufacturing a fet according to an embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and as used herein, a "plurality" includes two or more items.
Herein, unless otherwise specified, the individual preparation steps may be performed sequentially or may not be performed in sequence. For example, other steps may be included between the individual reaction steps, and the order may be reversed between the reaction steps. As can be determined by the skilled person based on routine knowledge and experience. Preferably, the reaction processes herein are carried out sequentially. In addition, the terms "upper" and "lower" as used herein are to be understood with reference to a certain reference and are not intended to be absolute limits of actual positions.
According to an embodiment of the invention, a field effect transistor comprises an epitaxial layer, a gate dielectric layer, a gate field plate, a source electrode and a drain electrode, wherein the epitaxial layer comprises a substrate, and a channel layer, a barrier layer and a passivation layer which are sequentially stacked on the substrate;
a window exposing part of the passivation layer is arranged in the gate dielectric layer, the side wall of the window close to the drain electrode is provided with a breakdown voltage enhancement structure, and in the breakdown voltage enhancement structure, the distance between the side wall and the drain electrode is gradually reduced along the direction far away from the passivation layer;
a gate field plate covers the sidewalls of the opening and contacts the passivation layer.
Where "sidewall" is to be understood as the wall connecting between the top and bottom surfaces of the gate dielectric layer. "taper" may be "taper" of a portion of the sidewall, or "taper" of the entire sidewall. The "tapering" may be a step-wise reduction, for example an abrupt change in the distance of the sidewall from the drain at a certain height from the passivation layer. It may also be a continuous decrease, e.g. the farther away from the passivation layer the closer the sidewall is to the drain.
The gate dielectric layer with the breakdown voltage enhancement structure is arranged below the gate, so that the problem of electric field intensity distribution distortion can be solved, an extremely high electric field peak value is avoided to a certain extent near a drain electrode, and the breakdown voltage of the field effect transistor is improved. However, in the actual etching process, whether dry etching or wet etching is adopted, there is a large uncontrollable in terms of etching area and etching uniformity, and therefore, a sidewall perpendicular to the passivation layer is inevitably formed. Although a gate field plate having such a shape can increase the breakdown voltage of the device, it also often becomes the dominant breakdown point, which limits further increase in the breakdown voltage of the field effect device. The inventors have found that the electric field strength at this vertical corner is significantly higher when the device is in operation, being the location in the device where breakdown is most likely.
In a preferred embodiment, the breakdown voltage enhancement structure has a variation in which the distance between the sidewall and the drain decreases continuously in a direction away from the passivation layer. It is understood that, in the breakdown voltage enhancement structure, all sidewalls may be provided with the sidewalls of the variation segment, a part of the sidewalls may be provided with the sidewalls of the variation segment, or there may be a plurality of stages of variation segments. I.e., the "continuous reduction" of some or all of the sidewalls described above.
Compared with certain jump-type changes, the side wall of the grid dielectric layer close to the drain electrode is further set to be continuously reduced, so that the electric field distortion when the grid dielectric layer is close to the drain electrode can be effectively eliminated, and the generation of vertical corners can be avoided or reduced as much as possible, so that the extremely high electric field strength at the corners is weakened, the breakdown of the device caused by the wooden barrel effect is avoided, and the breakdown voltage of the device is remarkably improved.
In one specific example, in the variation section, the manner of continuous decrease is linear decrease, and the amount of decrease in the distance of the side wall from the drain electrode is proportional to the distance from the passivation layer.
In other specific examples, the manner of continuously decreasing may be a curvilinear decrease in the telephone segment.
In one particular example, the breakdown voltage enhancement structure has a plurality of varying segments, with sidewalls of adjacent varying segments connected in a plane parallel to the passivation layer.
To facilitate an understanding of the fet of the present invention, reference is also made to fig. 1, which shows a more specific structure of the fet in one embodiment. In one particular example, the field effect transistor is a gallium nitride based field effect transistor.
The field effect transistor 10 includes a substrate 110, a buffer layer 120 disposed on the substrate 110, a channel layer 130 disposed on the buffer layer 120, and a barrier layer 140 disposed on the channel layer 130, and for convenience of understanding and presentation, the portions including the above layers are collectively referred to as an epitaxial layer. The above layers are or approximate to conventional fet structures, wherein the meaning of the layers is understood in accordance with the usual meaning in the art and will not be described in further detail herein.
A passivation layer 150 is disposed on the barrier layer 140. The passivation layer 150 mainly performs a passivation function, eliminates a surface state of the barrier layer 140, and improves stability and reliability of the device. In one specific example, the material of the passivation layer 150 may be silicon nitride or other material capable of performing a passivation function. Preferably, the material of the passivation layer 150 is silicon nitride.
A gate dielectric layer 160 is disposed on the passivation layer 150, a source electrode 180 and a drain electrode 190 are disposed on opposite sides of the gate dielectric layer 160, and a gate field plate is disposed in the gate dielectric layer 160 and, in this embodiment, is incorporated in the gate electrode 170. In the field effect transistor 10 shown in fig. 1, a window is opened in the gate dielectric layer 160 to expose the passivation layer 150. It will be appreciated that since the gate dielectric layer 160 necessarily spaces the gate electrode 170 from the drain electrode 190, there must be a barrier of the gate dielectric layer 160 between the exposed region of the passivation layer 150 and the drain electrode 190. The source electrode 180 and the source electrode 190 may be made of a metal material or a semiconductor material having a good conductivity.
The window is not a window with a side wall perpendicular to a passivation layer structure in a traditional field effect transistor, but is arranged as follows: in the direction from the exposed region of the passivation layer in the window to the drain electrode 190, the sidewall of the gate dielectric layer 160 near the drain electrode 190 is disposed as at least one variation section, and the distance between the sidewall in the variation section and the drain electrode 190 continuously decreases. In this case, "continuously decreasing" may be understood as "continuously decreasing" or "not abruptly decreasing", and in other specific examples, may be configured as discontinuously decreasing, that is, the distance is constant at a certain section, and the distance is abruptly changing at a certain section.
Referring to fig. 1, in this embodiment, the gate dielectric layer 160 is provided with two variation segments, i.e., a first variation segment 1601 and a second variation segment 1602; the first variation 1601 and the second variation 1602 are spaced by a flat 1603 parallel to the surface of the passivation layer 150.
As can be understood in conjunction with fig. 1, the sidewall of the first variation section 1601 is understood to be the slope where the first variation section 1601 is located, and the sidewall of the second variation section 1602 is understood to be the slope where the second variation section 1602 is located.
In the above-mentioned variation, the distance between the sidewall and the drain electrode may be linearly reduced or may be curvilinearly reduced. The linear decrease, i.e., the rate of distance decrease, remains constant so that the sidewall surface of the transition is a slope. The curve reduction, i.e. the distance reduction rate, is changed, so that the sidewall surface of the change section is a curved surface. In the curve increase, the distance decrease rate may be changed in a gradually increasing manner, or the distance decrease rate may be changed in a gradually decreasing manner. Preferably, the thickness of the gate dielectric layer 160 is increased in a linear manner.
In a specific example, in a direction from the exposed region of the passivation layer in the window to the source electrode 180, a variation section corresponding to the variation section near the source electrode 190 is disposed in the gate dielectric layer 160, as shown in fig. 1; the "corresponding variation section" does not mean that the two are symmetrical, but the distance between the sidewall on the source side and the source electrode and the distance between the sidewall on the drain electrode side and the drain electrode have similar changing trends and continuously decrease with distance from the passivation layer 150.
Since the thickness of the gate dielectric layer 160 gradually changes in the variation section, the line connecting the bottom end and the top end of the gate dielectric layer necessarily intersects with and is not perpendicular to the plane of the surface of the passivation layer 150. The non-vertical preparation is difficult to realize by the traditional etching process, and the side wall of the prepared window is usually vertical to the passivation layer. The invention can prepare the side wall of the window with a larger inclination angle. For example, in one specific example, the line connecting the bottom end and the top end makes an angle of ≦ 60 ° with the surface of passivation layer 150. Preferably, the angle between the line connecting the bottom end and the top end and the surface of the passivation layer 150 is less than or equal to 45 °. Further preferably, the angle between the connecting line of the bottom end and the top end and the surface of the passivation layer 150 is less than or equal to 30 °.
In one specific example, the material of passivation layer 150 is silicon nitride and has a thickness of
For example, the thickness of the passivation layer is
Or
Or ranges between the foregoing thicknesses.
The thickness of the gate dielectric layer 160 and the varying sections therein may be further designed in order to obtain a gate dielectric layer structure with better breakdown resistance. In one specific example, the height difference between the bottom end and the top end of a variation section is
This height difference is defined as the thickness of the varying section. Then, for example, the thickness of the region of the first variation 1601 is
Or
Or ranges between the foregoing thicknesses. As another example, of second variation section 1602Has a thickness of
Or
Or ranges between the foregoing thicknesses.
In one specific example, the material of the gate dielectric layer 160 is silicon dioxide, which has lattice defects in the silicon dioxide lattice, and in the variation section, the farther from the passivation layer, the more defects in the silicon dioxide lattice. The manner in which the silicon dioxide lattice defects are created may be ion implantation. The ion implantation treatment is to irradiate or bombard the surface of the material to be treated by adopting an ion source.
The gate dielectric layer 160 has an overall thickness of
For example, the gate dielectric layer 160 has an overall thickness of
Or
Or ranges between the foregoing thicknesses.
It is understood that the substrate 110, the buffer layer 120, the channel layer 130 and the barrier layer 140 are epitaxial layer structures of a conventional field effect transistor, and the materials, thicknesses and fabrication processes of the various layers can be selected by the skilled person as required without departing from the scope of the present invention. One common example of an epitaxial layer structure is provided below.
The material of the substrate 110 may be selected from substrates commonly used for gan-based fets, such as: silicon carbide, silicon or aluminum oxide.
The buffer layer 120 may be a buffer layer formed of a material including gallium nitride, and is a layer formed on the substrate 110, and functions to reduce the degree of mismatch of lattice constants of the channel layer 130 and the substrate 110, enhance the bonding force between the channel layer 130 and the substrate 110, and prevent stress concentration and/or cracks of the channel layer 130.
The channel layer 130 may be a channel layer formed of a material including gallium nitride; barrier layer 140 may be a barrier layer formed of a material including aluminum gallium nitride. The channel layer 130 and the barrier layer 140 serve to construct a two-dimensional electron gas, which is formed at an interface between the channel layer 130 and the barrier layer 140, within the channel layer 130.
It will be appreciated that the source electrode 180 is located above the barrier layer 140 and on one side of the gate field plate 160, and the drain electrode 190 is located above the barrier layer 140 and on the other side of the drain field plate 160.
Each layer included in the field effect transistor 10 having the gate field plate is only a general structure of the gallium nitride based field effect transistor, and in practical applications, specific layers may be appropriately increased or decreased as needed, which can be determined by a skilled person and is not described herein again.
The method for manufacturing the field effect transistor 10 with the gate field plate can refer to the manufacturing process shown in fig. 2.
S1, obtaining an epitaxial layer, wherein the epitaxial layer comprises a substrate, and a channel layer, a barrier layer and a passivation layer which are sequentially stacked on the substrate.
In a specific example, the method of obtaining a substrate in which a channel layer, a barrier layer, and a passivation layer are sequentially stacked may be self-fabrication, for example, fabricating the channel layer 130, the barrier layer 140, and the passivation layer 150 sequentially stacked on the substrate 110.
In a specific example, a step of preparing the channel layer 130 after preparing the buffer layer 120 on the substrate 110 is further included.
In a specific example, the buffer layer 120, the channel layer 130, the barrier layer 140, and the passivation layer 150 are prepared by a method selected from a vapor deposition method, which may be selected from a low pressure chemical vapor deposition or a metal organic compound chemical vapor deposition, or a sputtering method; the sputtering method can be selected from magnetron sputtering methods.
And S2, sequentially depositing a first gate dielectric material layer on the surface of the passivation layer of the substrate.
In one specific example, before depositing the first gate dielectric material layer 161, a step of cleaning the passivation layer is further included. In the step of cleaning the passivation layer, DHF, SC1 and SC2 may be selected in sequence for cleaning. The DHF is diluted hydrofluoric acid, the SC1 is a solution prepared from ammonia water, hydrogen peroxide and water, and the SC2 is a solution prepared from hydrochloric acid, hydrogen peroxide and water.
In one specific example, the first gate dielectric material layer 161 is deposited by a method selected from low pressure chemical vapor deposition or metal organic chemical vapor deposition.
And S3, forming a mask on the surface of the first gate dielectric material layer and carrying out wet etching.
In a specific example, before etching the first gate dielectric material layer 161, a step of removing a part of atoms in the crystal lattice of the first gate dielectric material layer 161 to generate crystal lattice defects is further included, and the closer to the surface of the first gate dielectric material layer 161 away from the passivation layer 150, the more crystal lattice defects are.
The lattice defects may be created by ion implantation, or may also be referred to as ion bombardment, of the first layer of gate dielectric material 161. Preferably, the ion implantation is performed by bombarding a surface of the first dielectric material layer 161 away from the passivation layer 150 with an ion beam. The angle of bombardment may be oblique bombardment or vertical bombardment, preferably the angle of bombardment is vertical bombardment.
By adopting the ion implantation treatment, the surface of the first gate dielectric material layer 161 can be bombarded by high-energy particles, and the surface of the first gate dielectric material layer 161 can be bombarded by the high-energy particles, so that part of atoms of crystal lattices in the first gate dielectric material layer 161 can be bombarded out, and the first gate dielectric material layer 161 with a large number of crystal lattice defects can be obtained. Also, it is understood that ion bombardment also has the following features: the high energy particle beam first contacts the atoms in the lattice of the first gate dielectric material layer 161 closer to the surface, so that the gate dielectric material closer to the surface is looser and the gate dielectric material further away from the side surface is denser.
Other ways of generating lattice defects that can achieve similar effects are not departing from the technical idea of the present invention.
At the lattice defect, the etch rate of the wet etch will increase. And. Because the density of the lattice defects in the first gate dielectric material layer 161 close to the surface is higher, and the density of the lattice defects far away from the surface is lower, the first gate dielectric material layer 161 close to the surface is easier to be etched, and the etching speed is higher; the part far away from the surface is more difficult to etch, and the etching speed is lower; meanwhile, wet etching may simultaneously etch in a lateral direction to some extent. Therefore, the material near the surface of the first gate dielectric material layer 161 is etched laterally more, and the material far from the surface of the first gate dielectric material layer 161 is etched laterally less, i.e. a variation section in which the thickness of the gate dielectric layer is continuously increased is formed.
In one particular example, the ion source used for ion implantation has an element selected from one or more of boron, phosphorous, arsenic and argon. For example, the ion source used for ion implantation is composed of argon.
In one specific example, the ion implantation dose is 10 12 ～10 15 Per cm 2 . The ion implantation dose represents the number of ions implanted per unit area. The larger the ion implantation dose is, the more lattice defects are in the first gate dielectric material layer 161 after ion implantation.
In a specific example, the energy of the ion implantation is 40keV to 150keV, and the larger the energy of the ion implantation, the more lattice defects are in the first gate dielectric material layer 161 after the ion implantation, and the deeper the implantation depth is. It can be understood that controlling the depth and dosage properly can affect the number of defects in different portions of the first gate dielectric material layer 161, and thus control the shape of the resulting window.
In one specific example, the material of the gate dielectric layer is silicon dioxide.
In one particular example, the etchant used for wet etching is an etchant containing hydrofluoric acid. For example, buffered silicon oxide etch solutions. The buffered silicon oxide etching solution is an oxide layer etching agent commonly used in the field, and is prepared by ammonium fluoride with the mass concentration of about 40% and hydrofluoric acid with the mass concentration of about 49% according to a certain volume ratio, and more specifically, the volume ratio of the ammonium fluoride solution to the hydrofluoric acid is 6. Alternatively, the etchant may be selected from other hydrofluoric acid containing etchants suitable for etching silicon oxide.
After this step of processing, the gate dielectric layer 160 can be formed with a variation section in which the variation trend of the thickness of the variation section, i.e., linear variation or curvilinear variation, can be controlled by controlling the etching condition and the ion implantation condition. For ease of illustration, the linear variation is shown in FIG. 2.
And S4, depositing a second gate dielectric material layer on the surface of the first gate dielectric material layer.
In one specific example, the material of the second gate dielectric material layer 162 is also silicon dioxide. The second gate dielectric material layer 162 is deposited by a method selected from low pressure chemical vapor deposition or metal organic compound chemical vapor deposition. Referring to fig. 2, since the surface of the first gate dielectric material layer 161 has been etched to form a window with a variation section, the surface of the second gate dielectric material layer 162 deposited subsequently also has a thickness variation trend similar to the variation section.
And S5, forming a mask and carrying out wet etching.
In one specific example, the sub-mask also covers a part of the area not covered by the mask in the previous preparation process. To etch further to a smaller window than the previous etch.
In one specific example, the second gate dielectric material layer 162 is also treated with ion implantation before forming the mask.
In one specific example, the etchant used for the wet etching is an etchant containing hydrofluoric acid. For example, buffered silicon oxide etch solutions. The buffered silicon oxide etching solution is an oxide layer etching agent commonly used in the field, and is prepared by ammonium fluoride with the mass concentration of about 40% and hydrofluoric acid with the mass concentration of about 49% according to a certain volume ratio, and more specifically, the volume ratio of the ammonium fluoride solution to the hydrofluoric acid is 6. Alternatively, the etchant may be selected from other hydrofluoric acid containing etchants suitable for etching silicon oxide.
Then, the first gate dielectric material layer 161 and the second gate dielectric material layer 162 together form the gate dielectric layer 160, and the gaps formed in the gate dielectric layer 160 after the processing in the steps S3 to S5 together form the window therein.
Preferably, the gate dielectric layer 160 has an overall thickness of
For example, the gate dielectric layer 160 has an overall thickness of
Or
Or ranges between the foregoing thicknesses.
After this step, a second variation segment can be formed in the second gate dielectric material layer 162. It is understood that, in some specific examples, the first variation section and the second variation section can be connected into one variation section by adjusting the preparation processes of the steps, without departing from the technical solution of the present invention.
It is understood that in other embodiments, the gate dielectric layer with more variation segments may be prepared, and only the gate dielectric material layer needs to be repeatedly deposited and etched according to the manufacturing manner similar to that shown in the above steps S3 to S5.
In the above manufacturing process, the source electrode, the gate electrode and the drain electrode are usually prepared by deposition. The gate may be directly deposited on the window region of the gate dielectric layer, and the gate is disposed in contact with the buffer layer 150.
The source electrode may be disposed on the passivation layer 150 on one side of the gate field plate 160. The drain electrode can be disposed on the passivation layer 150 on the other side of the gate field plate 160. Some etching may be performed on the two side edges of the gate field plate 160 during the source and drain preparation, which can be implemented by those skilled in the art as required, and need not be described herein.
In the field effect transistor, the gate dielectric layer is arranged to comprise the change section, and the thickness of the gate dielectric layer in the change section is continuously increased, so that the gate dielectric layer does not have a step-shaped sharp corner any more, the extremely high electric field intensity at the corner is weakened, and the breakdown of a device caused by the wooden barrel effect is avoided. Furthermore, compared with the gate dielectric layer with a stepped or multi-stage stepped structure, the gate dielectric layer with continuously increased thickness can more effectively eliminate electric field distortion, thereby remarkably improving the breakdown voltage of the device.
Meanwhile, the preparation method for preparing the field effect transistor can adopt a mode of carrying out etching after ion implantation, and different etching rates are generated by increasing lattice defects in a material of a gate dielectric layer so as to prepare the field effect transistor with a required structure more simply and conveniently, and has the advantages of simplicity, convenience, practicability and controllability.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. The preparation method of the field effect transistor is characterized by comprising the following steps of:
preparing an epitaxial layer, wherein the epitaxial layer comprises a substrate, and a channel layer, a barrier layer and a passivation layer which are sequentially stacked on the substrate, preparing a gate dielectric layer on the passivation layer, and respectively preparing a source electrode and a drain electrode on two sides of the gate dielectric layer;
the preparation of the gate dielectric layer comprises the following preparation steps: depositing a gate dielectric material, wherein the gate dielectric material is silicon dioxide, performing ion implantation on the gate dielectric material, selecting an argon element as an element of an ion source for the ion implantation, wherein the energy of the ion implantation is 40keV-150keV, forming a mask on the surface of the gate dielectric material, etching the gate dielectric material by a wet method to form a window which exposes part of the passivation layer, forming a breakdown voltage enhancement structure on the side wall of the window close to the drain electrode, and gradually reducing the distance between the side wall and the drain electrode in the direction away from the passivation layer in the breakdown voltage enhancement structure;
repeating the preparation steps for a plurality of times, wherein the mask in the later preparation step also covers the partial area which is not covered by the mask in the previous preparation process so as to form a gate dielectric layer with a plurality of change sections, and in the change sections, the distance between the side wall and the drain electrode is continuously reduced along the direction far away from the passivation layer.
2. The method of claim 1, wherein the ion implantation dose is 10 12 ~10 15 Per cm 2 。
3. The method for manufacturing a field effect transistor according to any one of claims 1 to 2, wherein an etchant used for the wet etching is an etchant containing hydrofluoric acid.
4. The method for manufacturing the field effect transistor according to any one of claims 1 to 2, wherein the gate dielectric layer is deposited by a method selected from low pressure chemical vapor deposition or metal organic compound vapor deposition.
5. The method for manufacturing the field effect transistor according to any one of claims 1 to 2, wherein the thickness of the gate dielectric layer is 1000A-5000A.
6. The method for manufacturing the field effect transistor according to any one of claims 1 to 2, wherein an included angle between a connecting line between the bottom end and the top end of the variable segment and the surface of the passivation layer is less than or equal to 60 °.
7. The method for manufacturing a field effect transistor according to any one of claims 1 to 2, wherein in the variation section, the distance between the side wall and the drain is linearly reduced.
8. The method for manufacturing a field effect transistor according to any one of claims 1 to 2, wherein the passivation layer is made of silicon nitride.
9. The method of manufacturing a field effect transistor according to any one of claims 1 to 2, wherein the thickness of the passivation layer is 200A-800A.
10. Use of the field effect transistor prepared by the method of any one of claims 1 to 9 in the preparation of an integrated circuit.
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