CN111949242A - Metastable state true random number generator based on FPGA - Google Patents
Metastable state true random number generator based on FPGA Download PDFInfo
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- CN111949242A CN111949242A CN202010843022.XA CN202010843022A CN111949242A CN 111949242 A CN111949242 A CN 111949242A CN 202010843022 A CN202010843022 A CN 202010843022A CN 111949242 A CN111949242 A CN 111949242A
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- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
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Abstract
The invention provides a metastable state true random number generator based on FPGA, which consists of 2 high-frequency loop oscillators, an equivalent establishing time delay unit, an anti-metastable state diffusion unit and a post-processing unit, wherein the high-frequency loop oscillator comprises 3 phase inverters, the equivalent establishing time delay unit comprises a D divider, an XOR gate and a delay unit, the XOR gate and the delay unit are connected to an input end by a D trigger output end through a feedback structure, the anti-metastable state diffusion unit comprises 2D triggers which are cascaded in front and back, the post-processing unit comprises 2D triggers, 2 AND gates and a lookup table, and the true random number is rectified by an edge detection method, the metastable state true random number generator has the advantages of convenient realization, wide transportability, high speed of generating the true random number and capability of generating a high-speed random number sequence, the method can be widely applied to the fields of key encryption algorithm, side channel attack defense, random event simulation test and the like.
Description
(I) technical field
The invention relates to a true random number generator, in particular to a metastable state true random number generator based on an FPGA (field programmable gate array), which can be used in the fields of key encryption algorithm, side channel attack defense, random event simulation test and the like and belongs to the field of electronic circuits.
(II) background of the invention
With the continuous development of computer networks and communication technologies, information security becomes more and more important, and encryption technology has also developed as the core of information security technology. The random number acts as a key in a symmetric or asymmetric cryptographic algorithm and, where necessary, as a random padding bit or a random mask, so to speak, the security of the cryptographic protocol depends entirely on the quality of the random number. Most of intelligent chips contain a random number generator inside, the random number generator is divided into a true random number generator and a pseudo random number generator, for a pseudo random number generator, the safety of the pseudo random number generator depends on the expected guess number of seed output and the complexity of an output function, the two factors are influenced by the size of attack calculation amount, and after a period of trial and error, the calculation amount for cracking the next random number can be reduced. As attacker's efforts continue to increase, encryption methods using pseudorandom number generators may become more vulnerable. The true random number generator generates a true random number having unpredictability as long as the data bit stream has a sufficient entropy value, and thus the encryption algorithm using the true random number has reliability.
The existing true random number generator can be mainly realized by an analog circuit and a digital circuit, the true random number generator realized by the analog circuit is mainly characterized in that the thermal noise of a resistor is amplified by an amplifier and then compared with a comparator to output a square wave, the method is relatively complex in design, high in power consumption and poor in robustness, and the inherent bias of a measuring device can be inevitably introduced in the acquisition process of the thermal noise, the true random number generator is realized by an oscillation sampling method in the digital circuit at present, and the specific realization method mainly comprises two steps: the first is to sample the fast oscillator with a slow oscillator, whose phase jitter causes uncertainty in the sampling instant, thus making the sequence random. The disadvantage is that the generated sequence has a large correlation, and if the standard deviation of the jitter of the sampling clock is larger than the period of the high-speed clock, the adjacent two samples can be considered to have no correlation, but the generation rate of the random number is seriously affected. The second one is that two coupled oscillation ring devices with the same period are used for sampling mutually, the shortest time for a data signal to keep stable before the rising edge of a clock signal is called as the setup time, and in an ideal state, a transition period that the output signal of the other oscillation ring is unstable can be collected at the sampling time point of a D trigger, so that the setup time is not met in the sampling process, and a metastable state phenomenon is caused. Based on the static timing analysis method, it is known that "metastability" occurs when the clock period plus the clock skew equals the sum of the register delay, the routing delay, and the setup time. It is generally considered that register delay and setup time are inherent properties of devices which cannot be changed, and the traditional method of generating "metastable state" almost entirely spreads around control trace delay, which causes great difficulty in controlling trace delay due to very short setup time, in the order of nanoseconds or even sub-nanoseconds.
The noise in the circuit is random, but certain deviation or correlation may be introduced in the quantization process, which affects the statistical properties of the true random number, so that the generated true random number is subjected to post-processing. The most widely used post-processing method is von neumann de-skew method, which is based on the principle that two bits of the sequence are acquired each time, and if the two bits are the same "0" or "1", the sequence is removed. The von Neumann deviation correction method has a good effect on the processing of the offset sequence, but the random number generation rate is reduced to one fourth of the original rate.
To solve the above problems, an FPGA-based metastable true random number generator is proposed herein. Compared with the prior art, the invention replaces the function of the D trigger by the equivalent establishing time delay unit, on one hand, other inherent biases influencing an entropy source are not introduced, the entropy value of a true random number is ensured, on the other hand, the establishing time of the D trigger is prolonged in a phase change manner, so that the whole generating device is easier to enter a metastable state, and the difficulty of realization is reduced. In addition, the post-processing module of the invention also provides a novel edge detection deviation correcting method on the basis of the Von Neumann deviation correcting method, and the speed of the edge detection deviation correcting method is doubled compared with the Von Neumann deviation correcting method.
Disclosure of the invention
The invention aims to provide the FPGA-based metastable-state true random number generator which has a simple and compact structure, occupies less hardware resources and has high true random number generating rate.
The purpose of the invention is realized as follows:
a metastable state true random number generator based on FPGA comprises a high-frequency loop oscillator 1, a high-frequency loop oscillator 2, an equivalent establishing time prolonging unit 3, a metastable state diffusion preventing unit 4 and a post-processing unit 5. The output end of the high-frequency loop oscillator 1 is connected with the data input end of the equivalent setup time extension unit 3, the output end of the high-frequency loop oscillator 2 is connected with the clock input end of the equivalent setup time extension unit 3, the output end of the equivalent setup time extension unit 3 is connected with the data input end of the metastable state diffusion preventing unit 4, the output end of the high-frequency loop oscillator 2 is connected with the clock input end of the metastable state diffusion preventing unit 4, the output end of the metastable state diffusion preventing unit 4 is connected with the data input end of the post-processing unit 5, and the output end of the high-frequency loop oscillator 2 is connected with the clock input end of the post-processing unit 5.
The high-frequency loop oscillator 1 and the high-frequency loop oscillator 2 comprise 3 phase inverters and 1 buffer, the output end of the 1 st phase inverter is connected with the output end of the 2 nd phase inverter, the output end of the 2 nd phase inverter is connected with the output end of the 3 rd phase inverter, and the output end of the 3 rd phase inverter, the input end of the 1 st phase inverter and the buffer are connected.
The equivalent establishing time prolonging unit 3 comprises 1D trigger, 1 exclusive-OR gate and 1 FPGA delay unit LCELL; in the equivalent setup time extension unit, the output terminal of the D flip-flop is connected to the output terminal of the high-frequency loop oscillator 1 and the input terminal of the xor gate, the output terminal of the xor gate is connected to the input terminal of the LCELL, and the output terminal of the LCELL is connected to the data input terminal of the D flip-flop. The circuit utilizes the property of an exclusive-OR gate to prolong the data stabilization time of the input end of the D flip-flop under the condition of not changing data.
The anti-metastable state diffusion unit 4 comprises 2D triggers; in the said anti-metastable state diffusion unit, the input end of the 1 st D flip-flop is connected with the output of the said equivalent establishing time prolonging unit, and the input end of the 2 nd D flip-flop is connected with the input end of the 1 st D flip-flop. The circuit can effectively reduce the 'metastable state' diffusion phenomenon by more than 99 percent.
The post-processing unit 5 comprises 1D trigger, 2 AND gates and 1 two-input lookup table; in the post-processing unit, the input end of a D trigger is connected with the output end of the metastable state diffusion preventing unit, the input end of the D trigger is connected with 1 input end of a 1 st AND gate, the output end of the D trigger is connected with 1 input end of a 1 st AND gate through a NOT gate, the input end of the D trigger is connected with 1 input end of a 2 nd AND gate through a NOT gate, the output end of the D trigger is connected with 1 input end of a 2 nd AND gate, and the output end of the 1 st AND gate, the output end of the 2 nd AND gate and the input end of the lookup table are connected.
Compared with the prior art, the invention has the following advantages:
1. the high frequency loop oscillator is used as an entropy source of the true random number generator, and the rate of data generation is higher than that of the traditional low frequency loop oscillator.
2. The true random number generator has a simple circuit structure, saves internal hardware resources of the FPGA, can be transplanted on different platforms, and has universal applicability.
3. The equivalent establishing time in the sampling process of the true random number generator is longer, and the requirement of establishing and maintaining time is easier to meet, so that the condition of generating the metastable state is looser, and the requirement on layout and wiring is lower than that of the traditional oscillation sampling method.
4. The true random number generator of the invention uses an edge detection method to replace an adjacent 2-bit data comparison method of a traditional von Neumann deviation corrector in a post-processing stage, so that the generation rate of the true random number is doubled compared with that of the traditional method.
(IV) description of the drawings
FIG. 1 is a schematic diagram of a prior art true random number generator.
FIG. 2 is a schematic diagram of the structure of a true random number generator of the present invention
FIG. 3 is a schematic diagram of the high frequency loop oscillator of the true random number generator of the present invention
FIG. 4 is a schematic diagram of an equivalent setup time delay unit of the true random number generator of the present invention
FIG. 5 is a schematic diagram of the structure of the anti-metastable diffusion unit of the true random number generator of the present invention
FIG. 6 is a schematic diagram of the structure of the post-processing unit of the true random number generator of the present invention
(V) detailed description of the preferred embodiments
The invention is further illustrated below with reference to specific examples.
Fig. 2 is a schematic structural diagram of a true random number generator implemented on an Altera Cyclone IV FPGA according to the present invention, which includes 2 high-frequency loop oscillators, an equivalent setup time extension unit, a metastable state diffusion prevention unit, and a post-processing unit. The output end of the 1 st high-frequency loop oscillator is connected with the data input end of the equivalent establishment time prolonging unit, the output end of the 2 nd high-frequency loop oscillator is connected with the clock input ends of the equivalent establishment time prolonging unit, the metastable state diffusion preventing unit and the post-processing unit, the output end of the equivalent establishment time prolonging unit is connected with the data input end of the metastable state diffusion preventing unit, and the output end of the metastable state diffusion preventing unit is connected with the data input end of the post-processing unit.
Fig. 3 shows a high frequency loop oscillator according to the present invention, which includes 3 inverters and 1 buffer, wherein the output terminal of the 1 st inverter is connected to the output terminal of the 2 nd inverter, the output terminal of the 2 nd inverter is connected to the output terminal of the 3 rd inverter, and the output terminal of the 3 rd inverter, the input terminal of the 1 st inverter are connected to the buffer.
Fig. 4 is an equivalent setup time delay unit in the present invention, which includes 1D flip-flop, 1 xor gate, and 1 FPGA delay unit LCELL. The output end of the D flip-flop is connected with the output end of the high-frequency loop oscillator 1 and the input end of the exclusive-or gate, the output end of the exclusive-or gate is connected with the input end of the LCELL, and the output end of the LCELL is connected with the data input end of the D flip-flop. LCELL is implemented through FPGA primitives.
FIG. 5 shows a meta-stable diffusion protection unit of the present invention, which includes 2D flip-flops. The input end of the 1 st D trigger is connected with the output end of the equivalent establishing time prolonging unit, and the input end of the 2 nd D trigger is connected with the input end of the 1 st D trigger.
Fig. 6 is a diagram of a post-processing unit in the present invention, which includes 1D flip-flop, 2 and gates, and 1 two-input lookup table. The input end of the D trigger is connected with the output end of the metastable state diffusion preventing unit, the input end of the D trigger is connected with 1 input end of the 1 st AND gate, the output end of the D trigger is connected with 1 input end of the 1 st AND gate through the NOT gate, the input end of the D trigger is connected with 1 input end of the 2 nd AND gate through the NOT gate, the output end of the D trigger is connected with 1 input end of the 2 nd AND gate, and the output end of the 1 st AND gate, the output end of the 2 nd AND gate and the input end of the lookup table are connected.
Claims (5)
1. An FPGA-based metastable true random number generator. The device is characterized by comprising a high-frequency loop oscillator 1, a high-frequency loop oscillator 2, an equivalent establishing time prolonging unit 3, a metastable state diffusion preventing unit 4 and a post-processing unit 5. The output end of the high-frequency loop oscillator 1 is connected with the data input end of the equivalent setup time extension unit 3, the output end of the high-frequency loop oscillator 2 is connected with the clock input end of the equivalent setup time extension unit 3, the output end of the equivalent setup time extension unit 3 is connected with the data input end of the metastable state diffusion preventing unit 4, the output end of the high-frequency loop oscillator 2 is connected with the clock input end of the metastable state diffusion preventing unit 4, the output end of the metastable state diffusion preventing unit 4 is connected with the data input end of the post-processing unit 5, and the output end of the high-frequency loop oscillator 2 is connected with the clock input end of the post-processing unit 5.
2. The FPGA-based metastable true random number generator of claim 1, wherein said high frequency loop oscillator 1 and said high frequency loop oscillator 2 comprise 3 inverters and 1 buffer, an output of a 1 st inverter is connected to an output of a 2 nd inverter, an output of a 2 nd inverter is connected to an output of a 3 rd inverter, and an output of a 3 rd inverter, an input of a 1 st inverter and a buffer are connected.
3. The FPGA-based metastable true random number generator of claim 1, characterized in that said equivalent setup time prolongation unit 3 comprises 1D flip-flop, 1 xor gate and 1 FPGA delay element LCELL; in the equivalent setup time extension unit, the output terminal of the D flip-flop is connected to the output terminal of the high-frequency loop oscillator 1 and the input terminal of the xor gate, the output terminal of the xor gate is connected to the input terminal of the LCELL, and the output terminal of the LCELL is connected to the data input terminal of the D flip-flop.
4. The FPGA-based metastable true random number generator of claim 1, characterized in that said anti-metastable diffusion unit 4 comprises 2D flip-flops; in the said anti-metastable state diffusion unit, the input end of the 1 st D flip-flop is connected with the output of the said equivalent establishing time prolonging unit, and the input end of the 2 nd D flip-flop is connected with the input end of the 1 st D flip-flop.
5. The FPGA-based metastable true random number generator of claim 1. The post-processing unit 5 comprises 1D trigger, 2 AND gates and 1 two-input lookup table; in the post-processing unit, the input end of a D trigger is connected with the output end of the metastable state diffusion preventing unit, the input end of the D trigger is connected with 1 input end of a 1 st AND gate, the output end of the D trigger is connected with 1 input end of a 1 st AND gate through a NOT gate, the input end of the D trigger is connected with 1 input end of a 2 nd AND gate through a NOT gate, the output end of the D trigger is connected with 1 input end of a 2 nd AND gate, and the output end of the 1 st AND gate, the output end of the 2 nd AND gate and the input end of the lookup table are connected.
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