CN111934962A - Method and system for receiving adaptive 429 data receiving rate based on FPGA - Google Patents
Method and system for receiving adaptive 429 data receiving rate based on FPGA Download PDFInfo
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- CN111934962A CN111934962A CN202010601396.0A CN202010601396A CN111934962A CN 111934962 A CN111934962 A CN 111934962A CN 202010601396 A CN202010601396 A CN 202010601396A CN 111934962 A CN111934962 A CN 111934962A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/4013—Management of data rate on the bus
- H04L12/40136—Nodes adapting their rate to the physical link properties
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40267—Bus for use in transportation systems
- H04L2012/4028—Bus for use in transportation systems the transportation system being an aircraft
Abstract
The invention provides a receiving method of self-adaptive 429 data receiving rate based on FPGA, comprising the following steps: s1, performing burr filtering on the received 429+ end data and-end data; s2, timing is started when data with high level at the + end and the-end and only one end is high, the received data are buffered, the timing is ended when the + end or the-end jumps, and the buffering is ended at the same time, so that the data received within a timing t1 and a timing t1 time period are obtained; s3, starting timing when the + end or the-end of the data receiving jumps from high level to low level, and stopping timing when the + end or the-end jumps from low level to high level to obtain timing t 2; s4, adding the timing t1 and the timing t2 to obtain the time t3 required for receiving the one-bit 429 data; s5, extracting data with the length of t3 from the cached data to obtain one-bit 429 data; s6, repeating the steps S1-S532 times to obtain a complete 429 data. The invention can ensure that the 429 data transmission rate of the transmitting equipment changes and can carry out correct receiving in a self-adaptive manner.
Description
Technical Field
The invention relates to the field of communication, in particular to a method and a system for receiving adaptive 429 data receiving rate based on an FPGA (field programmable gate array).
Background
The ARINC429 bus protocol was proposed and approved by the american aviation electronics engineering committee (AEC) in 7 months 1977. The protocol standards specify data information transmission requirements between avionics equipment and related systems. The ARINC429 bus is simple in structure, stable in performance, strong in anti-interference performance and high in reliability. The method adopts a bipolar zero-returning tri-state code modulation mode, the bit rate of the high-speed working speed is 100Kb/s (see figure 1, each bit of data lasts 10us), the bit rate of the low-speed working speed is 12.5Kb/s (12 Kb/s-14.5 Kb/s) (see figure 2, each bit of data lasts 80us), and the error range of the bit rate of the selected content is within 1 percent.
ARINC429 transmits in an asynchronous manner and the basic unit is a word, each consisting of 32 bits. The bit synchronization information is carried in the bipolar return to zero code signal waveform, the word synchronization is based on a zero level time interval of at least 4 bits during transmission, and the start of the first bit to be transmitted immediately following the word interval is the start of the new word (see fig. 3).
The reception rate of the current 429 receiving device is matched in advance and fixed according to the 429 transmitting rate (100Kb/s or 12.5Kb/s) of the transmitting device. There are mainly the following problems:
1) the sending rate of the sending device is not standard; the transmitting rate of the transmitting device is not standard (the standard transmitting rate is 100Kb/s or 12.5Kb/s), which may cause received 429 data errors;
2) aging of the crystal oscillator: as the service time is prolonged, crystal oscillator aging or clock drift exists in the sending device, but the receiving rate of the receiving device is fixed, which can cause received 429 data errors;
3) debugging is troublesome: when the sending rate of the sending device changes, the conventional method is to modify the relevant program of the receiving rate of the receiving device after the oscilloscope measures the sending rate of the current sending device, and the modification is slow and the efficiency is low.
Disclosure of Invention
Aiming at the defects of the method introduced in the prior art and aiming at adapting to equipment with different rates to achieve the purpose of adaptive receiving, the invention provides a receiving method and a receiving system of adaptive 429 data receiving rate based on FPGA, which accurately and quickly judge a plurality of 429 transmitting rates sent by different equipment by utilizing high-precision data sampling of FPGA, so that the 429 receiving rate is automatically and adaptively matched with the transmitting rate to correctly receive 429 data.
The technical scheme adopted by the invention is as follows: an FPGA-based adaptive 429 data receiving rate receiving method comprises the following steps:
s1, performing burr filtering on the received 429+ end data and-end data;
s2, timing is started when data with high level at the + end and the-end of the data receiving end only have high level at one end, the received data are buffered, the timing is ended when the + end or the-end jumps, and the buffering is ended at the same time, so that the data received within a timing t1 and a timing t1 time period are obtained;
s3, starting timing when the + end or the-end of the data receiving jumps from high level to low level, and stopping timing when the + end or the-end jumps from low level to high level to obtain timing t 2;
s4, adding the timing t1 and the timing t2 to obtain the time t3 required for receiving one complete 429 data;
s5, extracting data with the length of t3 from the cached received data to obtain one-bit 429 data;
s6, repeating the steps S1-S532 times to obtain a complete 429 data.
Further, in step S4, if the difference between the first timing and the second timing is too large, the current data is discarded and the process proceeds to step S1.
The invention also provides a receiving system of self-adaptive 429 data receiving rate based on FPGA, comprising:
the buffer module is used for buffering the data received by the data receiving + end and the data receiving-end;
the first timing module starts timing when data with high level at one end of the data receiving + end and the data receiving-end and only one end of the data receiving + end and the data receiving-end are high, and finishes timing when the + end or the data receiving-end jump to obtain timing t 1;
the first timing module jumps from high level to low level at the data receiving + end or-end to start timing until the + end or-end jumps from low level to high level to stop timing, and timing t2 is obtained;
the time calculation module is used for summing the timing t1 and the timing t2 to obtain t 3;
and the data bit extraction module receives the summation result t3 of the time calculation module, extracts data with the length of t3 from the buffer module according to the summation result, and finishes the extraction of data with one bit 429.
Further, the receiving system further includes a filtering module, configured to filter the received data to remove the glitch.
Further, the receiving system also comprises a data output module, and after the data bit extraction module extracts data for 32 times, the receiving system completes the output of 429 data.
Further, the buffer length of the buffer module is the longest buffer space required for receiving the 1-bit 429 data.
Further, the system is designed by adopting a VHDL/Verilog hardware language.
Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows:
1) the adaptability is strong: receiving nonstandard rate of 8 Kbps-150 Kbps;
2) the performance parameters are stable: the FPGA digital mode is adopted for realization, and the environment influence is small during operation;
3) the debugging is simple: when the external rate changes, the receiving program is modified after the rate is not required to be tested by the testing equipment;
4) the integration and the transplantation are convenient: the design is carried out by adopting a VHDL/Verilog hardware language without any IP core.
Drawings
Fig. 1 is a diagram illustrating data of the first 4 bits of a receiving end when a 429 data receiving rate is high speed (100 Kbps).
Fig. 2 is a diagram showing the data of the first 4 bits at the receiving end when the 429 data receiving rate is high speed (12.5 Kbps).
Fig. 3 is a schematic diagram of a transmitting end continuously transmitting two 429 data.
Fig. 4 is a schematic block diagram of the receiving system of the present invention.
Fig. 5 is a flow chart of a method for receiving adaptive 429 data receiving rate in accordance with the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
The invention mainly solves the following problems:
1) and (3) stabilizing: because of the full digital design, the system is less influenced by the environment during operation and is more stable and reliable;
2) the debugging is simple: extra test equipment is not needed to test the receiving rate;
3) the integration and the transplantation are convenient: designed entirely by the VHDL/Verilog hardware language and without any IP core
The specific scheme is as follows:
as shown in fig. 5, a receiving method for self-adapting 429 data receiving rate based on FPGA includes the following steps:
s1, performing burr filtering on the received 429+ end data and-end data;
s2, timing is started when data with high level at the + end and the-end of the data receiving end only have high level at one end, the received data are buffered, the timing is ended when the + end or the-end jumps, and the buffering is ended at the same time, so that the data received within a timing t1 and a timing t1 time period are obtained;
s3, starting timing when the + end or the-end of the data receiving jumps from high level to low level, and stopping timing when the + end or the-end jumps from low level to high level to obtain timing t 2;
s4, adding the timing t1 and the timing t2 to obtain the time t3 required for receiving one complete 429 data;
s5, extracting data with the length of t3 from the cached received data to obtain one-bit 429 data;
s6, repeating the steps S1-S532 times to obtain a complete 429 data.
Specifically, in step S4, if the difference between the first timer and the second timer is too large, the current data is discarded and the process proceeds to step S1.
As shown in fig. 4, the present invention further provides an FPGA-based adaptive 429 data receiving rate receiving system, which includes:
the buffer module is used for buffering the data received by the data receiving + end and the data receiving-end;
the first timing module starts timing when data with high level at one end of the data receiving + end and the data receiving-end and only one end of the data receiving + end and the data receiving-end are high, and finishes timing when the + end or the data receiving-end jump to obtain timing t 1;
the first timing module jumps from high level to low level at the data receiving + end or-end to start timing until the + end or-end jumps from low level to high level to stop timing, and timing t2 is obtained;
the time calculation module is used for summing the timing t1 and the timing t2 to obtain t 3;
and the data bit extraction module receives the summation result t3 of the time calculation module, extracts data with the length of t3 from the buffer module according to the summation result, and finishes the extraction of data with one bit 429.
The receiving system also comprises a data output module which finishes outputting 429 data after the data bit extraction module extracts data for 32 times.
In a preferred embodiment, the receiving system further comprises a filtering module for performing spur filtering on the received data.
In a preferred embodiment, the buffer length of the buffer module is the longest buffer space required for receiving 1-bit 429 data.
In a preferred embodiment, the system is designed in the VHDL/Verilog hardware language.
The invention provides a receiving method and a system for automatically realizing multi-rate 429 data by using FPGA universal resources, which are characterized in that the + end and the-end of the received data are counted and relatively checked by utilizing the bipolar return-to-zero transmission characteristic of ARINC429 data, so that the problem that additional test equipment is needed to test the sending rate when the sending 429 rate of the sending equipment is changed and then the program of the receiving equipment is modified is solved, and the debugging and modifying time is shortened.
The invention is not limited to the foregoing embodiments. The invention extends to any novel feature or any novel combination of features disclosed in this specification and any novel method or process steps or any novel combination of features disclosed. Those skilled in the art to which the invention pertains will appreciate that insubstantial changes or modifications can be made without departing from the spirit of the invention as defined by the appended claims.
All of the features disclosed in this specification, or all of the steps in any method or process so disclosed, may be combined in any combination, except combinations of features and/or steps that are mutually exclusive.
Any feature disclosed in this specification may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.
Claims (7)
1. An FPGA-based adaptive 429 data receiving rate receiving method is characterized by comprising the following steps:
s1, performing burr filtering on the received 429+ end data and-end data;
s2, timing is started when data with high level at the + end and the-end of the data receiving end only have high level at one end, the received data are buffered, the timing is ended when the + end or the-end jumps, and the buffering is ended at the same time, so that the data received within a timing t1 and a timing t1 time period are obtained;
s3, starting timing when the + end or the-end of the data receiving jumps from high level to low level, and stopping timing when the + end or the-end jumps from low level to high level to obtain timing t 2;
s4, adding the timing t1 and the timing t2 to obtain the time t3 required for receiving one complete 429 data;
s5, extracting data with the length of t3 from the cached received data to obtain one-bit 429 data;
s6, repeating the steps S1-S532 times to obtain a complete 429 data.
2. The receiving method of adaptive 429 data receiving rate based on FPGA according to claim 1, wherein in step S4, if the difference between the timing one and the timing two is too large, the current data is discarded and the step S1 is proceeded.
3. An FPGA-based adaptive 429 data receiving rate receiving system is characterized by comprising:
the buffer module is used for buffering the data received by the data receiving + end and the data receiving-end;
the first timing module starts timing when data with high level at one end of the data receiving + end and the data receiving-end and only one end of the data receiving + end and the data receiving-end are high, and finishes timing when the + end or the data receiving-end jump to obtain timing t 1;
the first timing module jumps from high level to low level at the data receiving + end or-end to start timing until the + end or-end jumps from low level to high level to stop timing, and timing t2 is obtained;
the time calculation module is used for summing the timing t1 and the timing t2 to obtain t 3;
and the data bit extraction module receives the summation result t3 of the time calculation module, extracts data with the length of t3 from the buffer module according to the summation result, and finishes the extraction of data with one bit 429.
4. The FPGA-based adaptive 429 data receiving rate receiving system of claim 3 further comprising a filtering module for filtering the glitches of the received data.
5. The FPGA-based adaptive 429 data receiving rate receiving system as claimed in claim 4, further comprising a data output module for outputting 429 data after the data bit extraction module extracts 32 times.
6. The FPGA-based adaptive 429 data receiving rate receiving system of claim 5, wherein the buffer length of the buffer module is the longest buffer space required for receiving 1-bit 429 data.
7. The FPGA-based adaptive 429 data receiving rate receiving system as claimed in claim 3, wherein the system is designed in VHDL/Verilog hardware language.
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Citations (6)
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| US4773040A (en) * | 1984-01-30 | 1988-09-20 | Fanuc Ltd. | Data transmission method and apparatus therefor |
| CN104202040A (en) * | 2014-09-04 | 2014-12-10 | 南京矽力杰半导体技术有限公司 | Detecting circuit and method for bit level |
| CN105680947A (en) * | 2015-12-29 | 2016-06-15 | 暨南大学 | Serial data receiving method capable of filtering burrs |
| CN108573157A (en) * | 2017-03-09 | 2018-09-25 | 李明 | A kind of data interactive method and system |
| CN109752999A (en) * | 2019-01-02 | 2019-05-14 | 中国船舶重工集团公司第七0七研究所 | A kind of ARINC429 bus communication based on FPGA |
| CN111052690A (en) * | 2017-10-26 | 2020-04-21 | 欧姆龙株式会社 | Data acquisition method and data acquisition device |
-
2020
- 2020-06-29 CN CN202010601396.0A patent/CN111934962B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4773040A (en) * | 1984-01-30 | 1988-09-20 | Fanuc Ltd. | Data transmission method and apparatus therefor |
| CN104202040A (en) * | 2014-09-04 | 2014-12-10 | 南京矽力杰半导体技术有限公司 | Detecting circuit and method for bit level |
| CN105680947A (en) * | 2015-12-29 | 2016-06-15 | 暨南大学 | Serial data receiving method capable of filtering burrs |
| CN108573157A (en) * | 2017-03-09 | 2018-09-25 | 李明 | A kind of data interactive method and system |
| CN111052690A (en) * | 2017-10-26 | 2020-04-21 | 欧姆龙株式会社 | Data acquisition method and data acquisition device |
| CN109752999A (en) * | 2019-01-02 | 2019-05-14 | 中国船舶重工集团公司第七0七研究所 | A kind of ARINC429 bus communication based on FPGA |
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