CN111933699A - Preparation method and preparation system of semiconductor structure - Google Patents
Preparation method and preparation system of semiconductor structure Download PDFInfo
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- CN111933699A CN111933699A CN202011005773.0A CN202011005773A CN111933699A CN 111933699 A CN111933699 A CN 111933699A CN 202011005773 A CN202011005773 A CN 202011005773A CN 111933699 A CN111933699 A CN 111933699A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The invention discloses a preparation method of a semiconductor structure and a preparation system thereof, wherein the preparation method comprises the steps of providing a semiconductor substrate with a first area and a second area; forming a gate insulating material layer on the semiconductor substrate, wherein the gate insulating material layer comprises a first gate insulating material layer and a second gate insulating material layer which respectively cover the surfaces of the first region and the second region; forming a patterned photoresist layer on the gate insulating material layer, wherein the patterned photoresist layer covers the second gate insulating material layer and exposes the first gate insulating material layer; wet etching to remove at least part of the first gate insulating material layer, wherein the rest of the first gate insulating material layer is used as a first gate insulating layer; and during wet etching, etching and thinning the second gate insulating material layer after the etching solution penetrates the patterned photoresist layer so as to form a second gate insulating layer on the surface of the second region. The preparation method can simplify the existing double-gate manufacturing process and reduce the production cost.
Description
Technical Field
The invention belongs to the technical field of semiconductor preparation, and particularly relates to a preparation method and a preparation system of a semiconductor structure.
Background
In a semiconductor Gate process, a common method of a Dual Gate (Dual Gate) process is to deposit a Gate oxide layer, cover the Gate oxide layer region that does not need to be etched with a photoresist, etch the Gate oxide layer region that is not covered with the photoresist with a hydrofluoric acid Diluent (DHF), and finally remove the photoresist.
As semiconductor processes are more miniaturized, the thickness of the gate oxide layer is thinner, and when the gate oxide layer is deposited, the gate oxide layer is too thick, and at this time, the deposited gate oxide layer with too thick thickness needs to be etched and removed, and then the deposition process of the gate oxide layer is performed again to form the gate oxide layer with a suitable thickness.
In addition, in the conventional dual gate process, because the thicknesses of the gate oxide layers required by the low-voltage region and the medium-voltage region are different, the preparation process generally comprises primary surface cleaning, gate oxide layer deposition, photolithography, etching to remove the gate oxide layer in the low-voltage region, photoresist removal, secondary surface cleaning and gate oxide layer deposition in the low-voltage region in sequence, and thus, the process is complex and the cost is high.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method and a system for fabricating a semiconductor structure, which are used to solve the technical problems of complex dual gate process and high cost in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first region and a second region;
forming a gate insulating material layer on the semiconductor substrate, wherein the gate insulating material layer comprises a first gate insulating material layer and a second gate insulating material layer which respectively cover the surfaces of the first region and the second region;
forming a patterned photoresist layer on the gate insulating material layer, wherein the patterned photoresist layer covers the second gate insulating material layer and exposes the first gate insulating material layer;
wet etching to remove at least part of the thickness of the first gate insulating material layer, wherein the rest thickness of the first gate insulating material layer is used as a first gate insulating layer;
and etching and thinning the second gate insulating material layer after etching liquid penetrates through the patterned photoresist layer during wet etching so as to form a second gate insulating layer on the surface of the second region, wherein the etching rate of the first gate insulating material layer is greater than that of the second gate insulating material layer during the wet etching.
In an alternative embodiment, the first region comprises a low pressure region and the second region comprises a medium pressure region.
In an alternative embodiment, the material of the gate insulating material layer includes an oxide layer; the etching solution comprises hydrofluoric acid diluent or hydrofluoric acid buffer solution.
In an optional embodiment, the etching solution is a diluted hydrofluoric acid solution, wherein a molar ratio of hydrofluoric acid to deionized water in the diluted hydrofluoric acid solution is between 1:150 and 1: 250.
In an alternative embodiment, in the step of forming the layer of gate insulating material on the semiconductor substrate, the gate insulating layer has a thickness between 40 angstroms and 150 angstroms.
In an alternative embodiment, the etch rate of the first layer of gate insulating material is greater than the etch rate of the second layer of gate insulating material during the wet etch.
In an alternative embodiment, the method of forming the first gate insulating layer includes completely removing the first gate insulating material layer to expose the semiconductor substrate of the first region, and depositing an insulating material on the exposed semiconductor substrate to form the first gate insulating layer.
In an optional embodiment, an etching rate of the first gate insulating material layer is between 0.15 angstroms/second and 0.25 angstroms/second during the wet etching process.
In an alternative embodiment, the etching rate of the second gate insulating material layer is between 0.020 and 0.034 angstroms/second in the wet etching process.
In an optional embodiment, in the step of forming the patterned photoresist layer on the gate insulating material layer, a thickness of the patterned photoresist layer is between 1.8 micrometers and 2.6 micrometers.
To achieve the above and other related objects, the present invention also provides a semiconductor structure fabrication system for implementing the fabrication method of any one of the above, the fabrication system comprising:
the deposition unit is used for forming a gate insulating material layer on a semiconductor substrate, the semiconductor substrate is provided with a first area and a second area, and the gate insulating material layer comprises a first gate insulating material layer and a second gate insulating material layer which respectively cover the surfaces of the first area and the second area;
a photoetching unit for forming a patterned photoresist layer on the gate insulating material layer, wherein the patterned photoresist layer covers the second gate insulating material layer and exposes the first gate insulating material layer;
and the etching unit is used for removing at least part of the first gate insulating material layer with the thickness by wet etching, and taking the first gate insulating material layer with the residual thickness as a first gate insulating layer, wherein during the wet etching, etching liquid penetrates the patterned photoresist layer and then etches and thins the second gate insulating material layer so as to form a second gate insulating layer on the surface of the second region, and in the wet etching process, the etching rate of the first gate insulating material layer is greater than that of the second gate insulating material layer.
In one embodiment of the present invention, when the gate insulating material layer (e.g., silicon dioxide layer) on the low-pressure region exposed by the patterned photoresist layer is removed by etching at a higher etching rate, the etching solution penetrates the patterned photoresist layer and then etches the gate insulating material layer on the medium-pressure region under the patterned photoresist layer at a lower etching rate to form a medium-pressure gate insulating layer on the medium-pressure region, which not only can avoid the problems of silicon substrate loss (Si loss), extra etching (processes) of the gate insulating structure, and personnel operation risk, etc. caused by the need of removing the thicker gate insulating material layer when the gate insulating material layer is thicker, but also can simplify the existing dual-gate process and reduce the production cost;
in another embodiment of the present invention, when the partial thickness of the gate insulating material layer (e.g., silicon dioxide layer) on the low-voltage region exposed by the patterned photoresist layer is removed by etching at a higher etching rate, the etching solution penetrates the patterned photoresist layer and then etches the gate insulating material layer on the medium-voltage region under the patterned photoresist layer at a lower etching rate, so as to form the low-voltage gate insulating layer and the medium-voltage gate insulating layer on the low-voltage region and the medium-voltage region simultaneously, thereby further simplifying the conventional dual-gate process and reducing the production cost.
Of course, not all of the advantages described above need to be achieved at the same time by any one product embodying the present invention.
Drawings
Fig. 1 is a schematic diagram illustrating an exemplary dual gate process after forming a thicker gate oxide layer on a silicon substrate.
Fig. 2 is a schematic diagram illustrating an exemplary dual gate process after removing a thicker gate oxide layer on the silicon substrate.
Fig. 3 is a schematic diagram illustrating an exemplary dual gate process after forming a gate oxide layer of suitable thickness on a silicon substrate.
Fig. 4 is a schematic diagram illustrating an exemplary dual gate process after forming a photoresist layer on the gate oxide layer with a suitable thickness.
Fig. 5 is a schematic diagram illustrating an exemplary dual gate process after removing a gate oxide layer on a first region based on the photoresist layer etching to form a medium voltage gate oxide layer on a second region.
Fig. 6 is a schematic diagram illustrating an exemplary dual gate process after forming a low voltage gate oxide layer over the first region.
FIG. 7 is a flow chart illustrating a method for fabricating a semiconductor structure according to the present invention.
Fig. 8 is a schematic structural view illustrating a gate insulating material layer formed on a semiconductor substrate in the method for fabricating a semiconductor structure according to the present invention.
Fig. 9 is a schematic structural view after a patterned photoresist layer is formed on the gate insulating material layer in the method for fabricating a semiconductor structure according to the present invention.
Fig. 10 is a schematic structural view illustrating a structure of the semiconductor structure after the gate insulating material layer on the first region is removed by etching based on the patterned photoresist layer to form a second gate insulating layer on the second region according to the method for fabricating a semiconductor structure of the present invention.
Fig. 11 is a schematic structural view illustrating a method for fabricating a semiconductor structure according to the present invention, in which the gate insulating layer covered by the patterned photoresist layer is etched by using the principle of penetration.
Fig. 12 is a schematic structural view illustrating a first gate insulating layer formed on the first region in the method for fabricating a semiconductor structure according to the present invention.
FIG. 13 is a block diagram of a semiconductor structure fabrication system according to the present invention.
Element numbers:
10-semiconductor structure preparation system, 11-deposition unit, 12-photolithography unit, 13-etching unit, 101-silicon substrate, 102 a-thicker gate oxide layer, 102 b-suitable gate oxide layer, 103-photoresist layer, 104-medium voltage gate oxide layer, 105-low voltage gate oxide layer, 201-semiconductor substrate, 202-gate insulating material layer, 202 a-first gate insulating material layer, 202 b-second gate insulating material layer, 203-patterned photoresist layer, 204-second gate insulating layer, 205-first gate insulating layer, 206-etching solution.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In a semiconductor Gate process, a Dual Gate (Dual Gate) process is used, and the process flow includes the following steps:
step one, as shown in fig. 3, providing a silicon substrate 101, wherein the silicon substrate 101 has a low-pressure region (a first region in fig. 3) and a medium-pressure region (a second region in fig. 3);
step two, as shown in fig. 4, cleaning the surface of the silicon substrate 101, and depositing a gate oxide material layer 102b with a suitable thickness on the silicon substrate 101, where the gate oxide material layer 102b with a suitable thickness covers the first region and the second region of the silicon substrate 101;
step three, as shown in fig. 5, covering the gate oxide layer 102b with a proper thickness in the medium-voltage region, which does not need to be etched, with the photoresist layer 103, then etching the gate oxide layer 102b with a proper thickness in the low-voltage region, which does not cover the photoresist layer 103, with hydrofluoric acid (DHF), and finally removing the photoresist layer 103 to form a medium-voltage gate oxide layer 104 in the medium-voltage region;
step four, as shown in fig. 6, the structure surface after the photoresist layer 103 is removed is cleaned, and a low-voltage gate oxide layer 105 is formed on the low-voltage region, where the thickness of the low-voltage gate oxide layer 105 is smaller than that of the medium-voltage gate oxide layer 104.
It should be noted that, as the semiconductor process is more miniaturized, the thickness of the gate oxide layer is thinner, as shown in fig. 1, when the gate oxide layer is formed, the gate oxide layer is too thick, at this time, the deposited gate oxide layer 102a with a thicker thickness needs to be etched and removed, and then the process from the first step to the fourth step is performed again to form the gate oxide layer 102b with a suitable thickness, which not only is the process complicated, but also may cause problems such as silicon substrate loss (Si loss), extra etching (process) of the shallow trench isolation STI (which is made of silicon oxide), and personnel operation risk during the process of removing the gate oxide layer 102a with a thicker thickness. In addition, the method for forming the low voltage gate oxide layer 105 and the medium voltage gate oxide layer 104 in the low voltage region and the medium voltage region of the silicon substrate 101 is not only complex in process but also high in cost.
Based on this, the present invention provides a method for manufacturing a semiconductor structure, so as to solve the problems of complex dual gate process and high cost, wherein fig. 7 shows a flow chart of the method for manufacturing a semiconductor structure of the present invention, and fig. 8 to 12 show corresponding diagrams of each step in the method for manufacturing a semiconductor structure of the present invention.
The technical solutions of the method and the system for manufacturing the semiconductor structure according to the present invention will be described in detail below with reference to fig. 7 to 12.
As shown in fig. 7, the present embodiment provides a method for manufacturing a semiconductor structure, which includes the following steps:
step S10, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first region and a second region;
step S20, forming a gate insulating material layer on the semiconductor substrate, where the gate insulating material layer includes a first gate insulating material layer and a second gate insulating material layer covering the surfaces of the first region and the second region, respectively;
step S30, forming a patterned photoresist layer on the gate insulating material layer, the patterned photoresist layer covering the second gate insulating material layer and exposing the first gate insulating material layer;
step S40, removing at least a part of the first gate insulating material layer by wet etching, and using the remaining first gate insulating material layer as a first gate insulating layer, wherein, during the wet etching, the second gate insulating material layer is etched and thinned after the etching solution penetrates the patterned photoresist layer, so as to form a second gate insulating layer on the surface of the second region.
As shown in fig. 8, in step S10, a semiconductor substrate 201 is provided, and the material of the semiconductor substrate 201 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, and the semiconductor substrate 201 further includes a multilayer structure or the like of these semiconductors, or silicon-on-insulator (SOI), stacked-on-insulator silicon (SSOI), stacked-on-insulator silicon germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, the semiconductor substrate 201 may be, for example, a silicon substrate.
It should be noted that, in this embodiment, for example, a shallow trench isolation structure STI (not shown) may be formed in the semiconductor substrate 201, the shallow trench isolation structure STI may be used to electrically isolate a P-type well region (not shown) and an N-type well region (not shown) formed in the semiconductor substrate 201, and a material of the shallow trench isolation structure STI may be, for example, silicon dioxide.
It should be noted that, in this embodiment, the Semiconductor substrate 201 has a first region and a second region, the first region may be, for example, a low-voltage region LV configured to form a low-voltage active device, such as a low-voltage Complementary Metal Oxide Semiconductor (CMOS), and the second region may be, for example, a medium-voltage region MV configured to form a medium-voltage active device, such as a medium-voltage Complementary Metal Oxide Semiconductor (CMOS). It is understood that the first region and the second region may also be two regions in which insulating dielectric layers with different thicknesses are formed later, for example, in an embodiment, the first region may also be a medium voltage region MV, and the second region is a high voltage region HV; in another embodiment, the first region may also be a low pressure region LV and the second region is a high pressure region HV.
As shown in fig. 8, in step S20, a gate insulating material layer 202 is formed on the semiconductor substrate 201, wherein the gate insulating material layer 202 includes a first gate insulating material layer 202a and a second gate insulating material layer 202b covering the surfaces of the first region and the second region, respectively. Specifically, a step of cleaning the surface of the semiconductor substrate 201 first is performed to remove impurity particles or other contaminants on the surface of the semiconductor substrate 201; a silicon dioxide Layer (but other suitable insulating materials may also be used) is then deposited on the cleaned surface of the semiconductor substrate 201 as the gate insulating material Layer 202, and the gate insulating material Layer 202 may be formed by using a process including, but not limited to, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process. As an example, the thickness of the gate insulating material layer 202 is between 40 angstroms and 150 angstroms, such as 40 angstroms, 70 angstroms, 120 angstroms or 150 angstroms, and it is understood that the thickness of the gate insulating material layer 202 can be flexibly selected according to the requirement.
As shown in fig. 9, in step S30, a patterned photoresist layer 203 is formed on the gate insulating material layer 202, wherein the patterned photoresist layer 203 covers the second gate insulating material layer 202b and exposes the first gate insulating material layer 202a, and the step S30 may further include glue coating, pre-baking, alignment exposure, developing, and hardening (also referred to as post-baking).
(1) Gluing: that is, a photoresist film having a uniform thickness, a strong adhesion, and no defects is formed on the gate insulating material layer 202. First, in order to enhance the adhesion between the photoresist film and the gate insulating material layer 202, the gate insulating material layer 202 may be surface-modified with an adhesion enhancer, such as Hexamethyldisilazane (HMDS), Trimethylsilyldiethylamine (TMSDEA), etc., and an HMDS base film may be formed on the gate insulating material layer 202 by, for example, soaking, spraying, or Chemical Vapor Deposition (CVD), etc., and the HMDS base film may make the surface of the gate insulating material layer 202 hydrophobic from water molecules, and at the same time, the HMDS base film may enhance the adhesion of the gate insulating material layer 202 to the photoresist film. Subsequently, a photoresist film is prepared by spin coating using a spin coater (Spinner), and the thickness of the photoresist film is controlled by controlling parameters such as the amount of applied glue, the rotation speed, the amount of dropped glue, and the rotation time, and the photoresist may be, for example, krypton fluoride photoresist (KRF photoresist) model TDUR-P902 available from TOK tokyo chemical industries, japan. It should be noted that other suitable photoresists may be used as long as a photoresist layer of a suitable thickness formed using the photoresist is permeable to the etchant.
(2) Pre-baking: the photoresist film after spin coating still has a certain content of solvent, and the solvent can be volatilized and removed as much as possible through baking at a higher temperature, so that the adhesion and uniformity of the photoresist are improved, and the content of the solvent in the photoresist film can be reduced to about 5% after pre-baking. By way of example, when using a TDUR-P902 photoresist, the temperature of the pre-bake may be, for example, 110 ℃ to 120 ℃, such as 115 ℃, and the time of the pre-bake may be, for example, 50s to 70s, such as 60 s.
(3) Alignment exposure: for example, a molecular excited laser source (eximer laser) can be used to illuminate the photoresist film, where photoreaction occurs and the illuminated and non-illuminated portions thus create a solubility difference. When using a TDUR-P902 photoresist, the molecular excited state laser source may be, for example, a KRF molecular excited state laser source.
(4) And (3) developing: the product to be exposed and developed is immersed in a developing solution, and at this time, the exposed region of the positive photoresist and the unexposed region of the negative photoresist are dissolved in the developing solution, so as to obtain the patterned photoresist layer 203, where the patterned photoresist layer 203 has an opening exposing the first gate insulating material layer 202a, that is, the patterned photoresist layer 203 covers the second gate insulating material layer 202b and exposes the first gate insulating material layer 202 a.
(5) Hardening (postbaking): the developed product requires a high temperature treatment process, called a hard coating (post-baking), in order to evaporate the remaining solvent to harden the patterned photoresist layer 203 and further enhance the adhesion of the patterned photoresist layer 203 to the gate insulating material layer 202. By way of example, when using a TDUR-P902 photoresist, the temperature of the hardening (post-baking) may be, for example, 110 ℃ to 120 ℃, such as 110 ℃, and the time of hardening may be, for example, 50s to 70s, such as 60 s. As an example, the thickness of the finally formed patterned photoresist layer 203 is between 1.8 microns and 2.6 microns, such as 1.8 microns, 2.2 microns or 2.6 microns, it is understood that the thickness of the gate insulating material layer 202 can be flexibly selected according to the etching rate requirement.
In step S40, the first gate insulating material layer 202a is removed by wet etching, and the remaining thickness of the first gate insulating material layer 202a is used as the first gate insulating layer 205, wherein during the wet etching, the second gate insulating material layer 202b is etched to be thinner after the etching solution penetrates the patterned photoresist layer 203, so as to form the second gate insulating layer 204 on the surface of the second region. Specifically, step S40 may have two different embodiments according to whether the first gate insulating material layer 202a is completely etched, fig. 10 shows a structural diagram after wet etching completely removes the first gate insulating material layer 202a in the first embodiment, and fig. 12 shows a structural diagram after wet etching to remove a partial thickness of the first gate insulating material layer 202a to form the first gate insulating layer 205 on the first region in the second embodiment.
As shown in fig. 9 to 11, in the first embodiment, the first gate insulating material layer 202a in the first region is wet-etched by using the patterned photoresist layer 203 as a mask, the material of the first insulating material layer is silicon dioxide, so that a diluted hydrofluoric acid DHF (or a buffered hydrofluoric acid solution can be used as well) is used as an etching solution 206 for etching, during the etching process, the first gate insulating material layer 202a in the first region is completely removed to expose the surface of the first region, and during the etching process of the first gate insulating material layer 202a, the etching solution 206 penetrates through the patterned photoresist layer 203 and then etches the second gate insulating material layer 202b in the second region (see fig. 11). During the etching process, the etching solution 206 directly contacts with the first gate insulating material layer 202a to etch the first gate insulating material layer 202a, and the etching solution 206 penetrates through the patterned photoresist layer 203 and then contacts with the second gate insulating material layer 202b to etch the second gate insulating material layer 202b, so that the amount of the etching solution 206 applied to the surface of the first gate insulating material layer 202a is much larger than the amount of the etching solution 206 applied to the surface of the second gate insulating material layer 202b, which makes the etching rate of the first gate insulating material layer 202a much larger than that of the second gate insulating material layer 202b, so that after the first gate insulating material layer 202a is completely removed by etching, the second gate insulating material layer 202b still has a thicker thickness, and the second gate insulating material layer 202b with the remaining thickness is used as the second gate insulating layer 204 (when the second region is covered by the second region) In the medium voltage region, the second gate insulating layer 204 may be referred to as a medium voltage gate insulating layer); after the second gate insulating layer 204 is formed, a first gate insulating layer 205 may be further formed on the exposed first region (when the first region is a low voltage region, the first gate insulating layer 205 may be referred to as a low voltage gate insulating layer), and a thickness of the first gate insulating layer 205 is smaller than a thickness of the second gate insulating layer 204, so as to finally form the semiconductor structure shown in fig. 12. Illustratively, the molar ratio of hydrofluoric acid to deionized water in the hydrofluoric acid diluent is between 1:150 and 1:250, such as 1: 200; the etching rate of the first gate insulating material layer 202a on the surface of the first region is between 0.15A/s and 0.25A/s, such as 0.2A/s; the second gate insulating material layer 202b on the second region surface has an etching rate of 0.020 to 0.034 angstroms/second, such as 0.027 angstroms/second. It should be noted that, in this embodiment, since the etching rate of the second gate insulating material layer 202b is very low, the thickness of the second gate insulating layer 204 can be better controlled as required, so as to avoid the problems of silicon substrate loss (Si loss), extra etching (processes) of the gate insulating structure, and personnel operation risk, which are caused by the need to remove the thicker gate insulating material layer 202 when the gate insulating material layer 202 is thicker, and simplify the conventional dual-gate process, thereby reducing the production cost.
As shown in fig. 9, 11 and 12, in another embodiment, the first gate insulating material layer 202a in the first region is wet-etched by using the patterned photoresist layer 203 as a mask, the first gate insulating material layer 202a is made of silicon dioxide, so a diluted hydrofluoric acid DHF (or buffered hydrofluoric acid) can be used as an etching solution, during the etching, only a part of the thickness of the first gate insulating material layer 202a is removed, during the etching of the first gate insulating material layer 202a, after the etching solution 206 penetrates the patterned photoresist layer 203, the second gate insulating material layer 202b in the second region is etched and thinned (see fig. 11) to remove a part of the thickness of the first gate insulating material layer 202a, and the remaining thickness of the first gate insulating material layer 202a is used as a first gate insulating layer 205 (when the first region is a low-pressure region, the first gate insulating layer 205 may be referred to as a low voltage gate insulating layer), and the remaining thickness of the second gate insulating material layer 202b serves as the second gate insulating layer 204 (when the second region is a medium voltage region, the second gate insulating layer 204 may be referred to as a medium voltage gate insulating layer). In the etching process, the etching solution 206 directly contacts with the first gate insulating material layer 202a to etch the first gate insulating material layer 202a, and the etching solution 206 penetrates the patterned photoresist layer 203 and then contacts with the second gate insulating material layer 202b to etch the second gate insulating material layer 202b, so that the amount of the etching solution 206 applied to the surface of the first gate insulating material layer 202a is much larger than the amount of the etching solution 206 applied to the surface of the second gate insulating material layer 202b, which makes the etching rate of the first gate insulating material layer 202a much larger than that of the second gate insulating material layer 202b, so that the etching loss of the first gate insulating material layer 202a during the etching process is much larger than that of the second gate insulating material layer 202b, i.e., the thickness of the first gate insulating layer 205 is smaller than the thickness of the second gate insulating layer 204, to finally form the semiconductor structure shown in fig. 12. Illustratively, the molar ratio of hydrofluoric acid to deionized water in the hydrofluoric acid diluent is between 1:150 and 1:250, such as 1: 200; the etching rate of the first gate insulating material layer 202a on the surface of the first region is between 0.15A/s and 0.25A/s, such as 0.2A/s; the second gate insulating material layer 202b on the second region surface has an etching rate of 0.020 to 0.034 angstroms/second, such as 0.027 angstroms/second. It should be noted that, in this embodiment, a portion of the thickness of the first gate insulating material layer 202a (e.g., silicon dioxide layer) on the low-pressure region exposed by the patterned photoresist layer 203 is removed by etching at a higher etching rate, and the second gate insulating material layer 202b on the second region below the patterned photoresist layer 203 is etched at a lower etching rate by using the penetration property of the specific photoresist, so as to simultaneously form the first gate insulating layer and the second gate insulating layer on the first region and the second region. Compared with the first embodiment, the embodiment can further reduce the process steps of the double-gate process, thereby reducing the production cost.
It should be noted that the method for manufacturing a semiconductor structure of this embodiment may also be applied to etching other films, and only needs to select a suitable etching solution according to the material of the film and select the thickness of the photoresist layer with a suitable thickness based on the consideration of the etching rate.
It should be noted that the semiconductor structure of the present embodiment can be applied to various integrated circuits, such as memory circuits, for example, random access memories, dynamic random access memories, synchronous random access memories, static random access memories, or read only memories. The integrated circuit may also be a logic device such as a programmable logic array, an application specific integrated circuit, a combinational logic integrated circuit, a radio frequency circuit, or any other circuit device. The integrated circuit can also be used in, for example, consumer electronic products such as personal computers, portable computers, game machines, cellular phones, personal digital assistants, video cameras, digital cameras, cellular phones, and various other electronic products.
As shown in fig. 13, the embodiment of the present invention also provides a semiconductor structure manufacturing system 10, which includes a deposition unit 11, a photolithography unit 12, and an etching unit 13.
Specifically, the deposition unit 11 is configured to form a gate insulating material layer 202 on a semiconductor substrate 201, where the semiconductor substrate 201 has a first region and a second region, and the gate insulating material layer 202 includes a first gate insulating material layer 202a and a second gate insulating material layer 202b covering surfaces of the first region and the second region, respectively, and the execution process of the gate insulating material layer 202 is detailed in steps S10 and S20, which are not described herein again.
The photolithography unit 12 is configured to form a patterned photoresist layer 203 on the gate insulating material layer 202, wherein the patterned photoresist layer 203 covers the second gate insulating material layer 202b and exposes the first gate insulating material layer 202a, and the execution process thereof is detailed in step S30, which is not described herein again.
The etching unit 13 is configured to remove, by wet etching, at least a portion of the first gate insulating material layer 202a with a thickness, and the first gate insulating material layer 202a with a remaining thickness is used as a first gate insulating layer 205, where, during the wet etching, an etching solution penetrates the patterned photoresist layer 203 and then etches and thins the second gate insulating material layer 202b, so as to form a second gate insulating layer 204 on the surface of the second region, and the execution process of the etching unit is detailed in step S40 above, which is not described herein again.
It should be noted that, when the etching unit 13 completely removes the first gate insulating material layer 202a, the deposition unit 11 is further configured to form a first gate insulating layer 205 on the first area of the semiconductor substrate 201, which is exposed again, after etching.
In summary, in one embodiment of the present invention, when the gate insulating material layer (e.g. silicon dioxide layer) on the low-pressure region exposed by the patterned photoresist layer is removed by etching at a higher etching rate, the etching solution penetrates the patterned photoresist layer and then etches the gate insulating material layer on the medium-pressure region under the patterned photoresist layer at a lower etching rate to form the medium-pressure gate insulating layer on the medium-pressure region, which not only can avoid the problems of silicon substrate loss (Si loss), extra etching (processes) of the gate insulating structure, and personnel operation risk caused by the need to remove the thicker gate insulating material layer when the gate insulating material layer is thicker, but also can simplify the conventional dual-gate process and reduce the production cost; in another embodiment of the present invention, when the partial thickness of the gate insulating material layer (e.g., silicon dioxide layer) on the low-voltage region exposed by the patterned photoresist layer is removed by etching at a higher etching rate, the etching solution penetrates the patterned photoresist layer and then etches the gate insulating material layer on the medium-voltage region under the patterned photoresist layer at a lower etching rate, so as to form the low-voltage gate insulating layer and the medium-voltage gate insulating layer on the low-voltage region and the medium-voltage region simultaneously, thereby further simplifying the conventional dual-gate process and reducing the production cost. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
In the description herein, numerous specific details are provided, such as examples of components and/or methods, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Reference throughout this specification to "one embodiment", "an embodiment", or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, respective appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It is to be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the present invention.
It will also be appreciated that one or more of the elements shown in the figures can also be implemented in a more separated or integrated manner, or even removed for inoperability in some circumstances or provided for usefulness in accordance with a particular application.
Additionally, any reference arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise expressly specified. Further, as used herein, the term "or" is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.
The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The systems and methods have been described herein in general terms as the details aid in understanding the invention. Furthermore, various specific details have been given to provide a general understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Thus, although the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Accordingly, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.
Claims (10)
1. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first region and a second region;
forming a gate insulating material layer on the semiconductor substrate, wherein the gate insulating material layer comprises a first gate insulating material layer and a second gate insulating material layer which respectively cover the surfaces of the first region and the second region;
forming a patterned photoresist layer on the gate insulating material layer, wherein the patterned photoresist layer covers the second gate insulating material layer and exposes the first gate insulating material layer;
wet etching to remove at least part of the thickness of the first gate insulating material layer, wherein the rest thickness of the first gate insulating material layer is used as a first gate insulating layer;
and etching and thinning the second gate insulating material layer after etching liquid penetrates through the patterned photoresist layer during wet etching so as to form a second gate insulating layer on the surface of the second region, wherein the etching rate of the first gate insulating material layer is greater than that of the second gate insulating material layer during the wet etching.
2. The method of claim 1, wherein the first region comprises a low pressure region and the second region comprises a medium pressure region.
3. The method of claim 1, wherein the material of the gate insulating material layer comprises an oxide layer; the etching solution comprises hydrofluoric acid diluent or hydrofluoric acid buffer solution.
4. The method according to claim 3, wherein the etching solution is a diluted hydrofluoric acid solution, and a molar ratio of hydrofluoric acid to deionized water in the diluted hydrofluoric acid solution is between 1:150 and 1: 250.
5. The method of claim 1, wherein in the step of forming the layer of gate insulating material on the semiconductor substrate, the layer of gate insulating material has a thickness between 40 angstroms and 150 angstroms.
6. The method of claim 1, wherein forming the first gate insulating layer comprises completely removing the first gate insulating material layer to expose the semiconductor substrate in the first region, and depositing an insulating material on the exposed semiconductor substrate to form the first gate insulating layer.
7. The method of claim 6, wherein an etching rate of the first gate insulating material layer is between 0.15A/s and 0.25A/s during the wet etching.
8. The method as claimed in claim 6, wherein an etching rate of the second gate insulating material layer is 0.020A/s to 0.034A/s in the wet etching process.
9. The method as claimed in any one of claims 1 to 8, wherein in the step of forming the patterned photoresist layer on the gate insulating material layer, the thickness of the patterned photoresist layer is between 1.8 microns and 2.6 microns.
10. A semiconductor structure fabrication system for implementing the fabrication method of any one of claims 1-9, the fabrication system comprising:
the deposition unit is used for forming a gate insulating material layer on a semiconductor substrate, the semiconductor substrate is provided with a first area and a second area, and the gate insulating material layer comprises a first gate insulating material layer and a second gate insulating material layer which respectively cover the surfaces of the first area and the second area;
a photoetching unit for forming a patterned photoresist layer on the gate insulating material layer, wherein the patterned photoresist layer covers the second gate insulating material layer and exposes the first gate insulating material layer;
and the etching unit is used for removing at least part of the first gate insulating material layer with the thickness by wet etching, and taking the first gate insulating material layer with the residual thickness as a first gate insulating layer, wherein during the wet etching, etching liquid penetrates the patterned photoresist layer and then etches and thins the second gate insulating material layer so as to form a second gate insulating layer on the surface of the second region, and in the wet etching process, the etching rate of the first gate insulating material layer is greater than that of the second gate insulating material layer.
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| JPH11121433A (en) * | 1997-10-20 | 1999-04-30 | Nec Corp | Manufacture of semiconductor device |
| US5918133A (en) * | 1997-12-18 | 1999-06-29 | Advanced Micro Devices | Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof |
| JP2004087566A (en) * | 2002-08-23 | 2004-03-18 | Sony Corp | Manufacturing method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11121433A (en) * | 1997-10-20 | 1999-04-30 | Nec Corp | Manufacture of semiconductor device |
| US5918133A (en) * | 1997-12-18 | 1999-06-29 | Advanced Micro Devices | Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof |
| JP2004087566A (en) * | 2002-08-23 | 2004-03-18 | Sony Corp | Manufacturing method of semiconductor device |
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Effective date of registration: 20240325 Address after: 230000 No. 88, xifeihe Road, Hefei comprehensive free trade zone, Xinzhan District, Hefei City, Anhui Province Patentee after: Nexchip Semiconductor Corporation Country or region after: China Address before: No.18-h1105, Yinchun Road, science and technology R & D base, Maigaoqiao entrepreneurship Park, Qixia District, Nanjing, Jiangsu Province, 210000 Patentee before: Nanjing crystal drive integrated circuit Co.,Ltd. Country or region before: China |