CN111933084B - Gate drive circuit, array substrate, display device and drive method - Google Patents

Gate drive circuit, array substrate, display device and drive method Download PDF

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Publication number
CN111933084B
CN111933084B CN202010908126.4A CN202010908126A CN111933084B CN 111933084 B CN111933084 B CN 111933084B CN 202010908126 A CN202010908126 A CN 202010908126A CN 111933084 B CN111933084 B CN 111933084B
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China
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signal
unit
driving
transistor
pull
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CN111933084A (en
Inventor
华刚
邓立广
王冬
王哲
王敏
李少波
龚猛
胡锦堂
樊鹏凯
唐亮珍
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The invention discloses a grid driving circuit, an array substrate, a display device and a driving method, wherein the grid driving circuit comprises a plurality of cascaded shift register units, and each shift register unit comprises: the first driving unit outputs a first driving signal according to a first control signal, a first power signal and a first clock signal, and the first driving signal is input into a first driving unit of a next-stage shift register unit; the second driving unit outputs a second driving signal according to a second control signal, the first driving signal and a second clock signal, the second control signal comprises a row selection signal, and the second driving signal is input into a second driving unit of the next-stage shift register unit; and a first cut-off unit outputting a cut-off signal to the first driving unit and/or outputting a cut-off signal to the second driving unit according to an inputted third control signal. According to the embodiment provided by the invention, through the matching of the second driving unit and the cut-off unit, the independent scanning of the designated area can be realized.

Description

Gate drive circuit, array substrate, display device and drive method
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit, an array substrate, a display device and a driving method.
Background
In the display application scenario, there is a special requirement, such as the information display of LCD or AMOled, when the screen is locked, and some kind of information needs to be checked or some kind of information is received for reminding, the system will trigger the whole screen to light and wake up, especially the LCD display is driven by liquid crystal, although the writing signal can be controlled by IC to perform the blackening process on the non-sensitive area, the actual behavior is still to open each row of switches row by row and write in the black signal picture, and this operation will certainly cause unnecessary power consumption waste.
Another important application scenario: the name, specification and the like of a general description commodity can never be changed by applying a merchant super price tag of the electronic paper, the electronic paper has the characteristic that the electronic paper can be stored for a long time by writing once, the problem that the electronic paper can trigger refreshing once when updating information such as price and the like can not be avoided, and particularly, a picture of one pixel driven by the electronic paper needs multi-frame signal writing for adjustment. In view of the above problems, the problem can be avoided and power consumption can be further reduced by using area scanning, but at present, the problem is discovered and emphasized because Gate Driver on Array (GOA) of the electronic paper Array substrate is already in a pre-research stage, and therefore development of a GOA driving circuit performing the function becomes a major breakthrough in next development of electronic paper.
At present, a certain area Gate can be opened line by line through the independent TCON control of an IC, but it is still difficult to realize area scanning for the design requirement of low cost of using a shift register as a narrow frame in the narrow frame design field.
Disclosure of Invention
In order to solve at least one of the above problems, a first aspect of the present invention provides a gate driving circuit applied to a display device, the display device including a plurality of rows of sub-pixels, the gate driving circuit including a plurality of cascaded shift register units, each shift register unit including a first driving unit, a second driving unit and a first cut-off unit, each second driving unit being connected to a row selection signal line, wherein
A first driving unit configured to output a first driving signal according to an input first control signal, a first power signal and a first clock signal, the first driving signal being input to a first driving unit of a next stage shift register unit;
a second driving unit configured to determine whether to output a second driving signal according to an input second control signal and the first driving signal, and output the second driving signal in response to a second clock signal, the second control signal including a row selection signal transmitted by a row selection signal line, the second driving signal being used to provide a gate signal to a sub-pixel row of the display device corresponding to the shift register unit, the second driving signal being input to a second driving unit of a next-stage shift register unit;
and a first cutoff unit configured to output a cutoff signal to the first driving unit to stop outputting the first driving signal according to the input third control signal, and/or configured to output a cutoff signal to the second driving unit to stop outputting the second driving signal according to the input third control signal.
In some alternative embodiments, the second driving unit includes: an output selection unit, a second pull-up unit and a set unit, wherein
The output selection unit is configured to judge whether to select to output the second driving signal according to the input second control signal and the first driving signal, and if so, the output selection unit controls the potential of a second pull-up node, wherein the second pull-up node is a connection node of the output selection unit, the second pull-up unit and the setting unit;
a second pull-up unit configured to output a second driving signal from a second signal output terminal according to a second clock signal under control of a potential of a second pull-up node;
and a setting unit configured to set a potential of the second pull-up node and the second driving signal by a second power signal according to the second driving signal of the next stage shift register unit.
In some optional embodiments, the output selection unit includes a first selection transistor and a second selection transistor, wherein a first pole of the first selection transistor is connected to the first driving signal, a second pole of the first selection transistor is connected to the second pull-up node, a control pole of the first selection transistor is connected to the selection signal line to connect to the row selection signal, a first pole of the second selection transistor is connected to the first driving signal, a second pole of the second selection transistor is connected to the second pull-up node, and a control pole of the second selection transistor is connected to the second driving signal of the shift register unit of the previous stage;
the second pull-up unit comprises a second control transistor and a second storage capacitor; the first pole of the second control transistor is connected to the second clock signal, the second pole of the second control transistor is connected to the second signal output end to output a second driving signal, the control pole of the second control transistor is connected to the second pull-up node, the first end of the second storage capacitor is connected to the second pull-up node, and the second end of the second storage capacitor is connected to the second signal output end.
In some optional embodiments, the setting unit includes a first setting transistor and a second setting transistor, where a first pole of the first setting transistor is connected to the second pull-up node, a second pole is connected to the second power signal, and a control pole is connected to the second driving signal of the next stage of shift register unit; and a first pole of the second setting transistor is connected with the second signal output end, a second pole of the second setting transistor is connected with a second power supply signal, and a control pole of the second setting transistor is connected with a second driving signal of the next-stage shift register unit.
In some optional embodiments, the first driving unit includes an input unit, a first pull-up unit, a pull-down control unit, a pull-down unit, a reset unit, and a noise reduction unit, wherein,
the input unit is configured to control the potential of a first pull-up node according to an input first control signal and a first power supply signal, wherein the first pull-up node is a connection node among the input unit, the first pull-up unit and the pull-down unit;
the first pull-up unit is configured to output a first driving signal from the first signal output terminal according to a first clock signal under control of a potential of a first pull-up node;
the pull-down control unit is configured to control a potential of a pull-down node according to a pull-down control signal, the pull-down node being a connection node between the pull-down control unit and the pull-down unit;
the pull-down unit is configured to pull down a potential of the pull-down node by a second power supply signal under control of a potential of the first pull-up node;
the reset unit is configured to reset the first pull-up node by a reset power signal under control of a reset signal;
the noise reduction unit is configured to pull down the potentials of the first pull-up node and the first signal output terminal by the second power supply signal under control of the potential of the pull-down node.
In some optional embodiments, the input unit includes a first transistor, a first pole of the first transistor is connected to the first power signal, a second pole of the first transistor is connected to the first pull-up node, and a control pole of the first transistor is connected to the first control signal;
the first pull-up unit comprises a first control transistor and a first storage capacitor, wherein a first pole of the first control transistor is connected to a first clock signal, a second pole of the first control transistor is connected with a first signal output end to output a first driving signal, a control pole of the first control transistor is connected with a first pull-up node, a first end of the first storage capacitor is connected with the first pull-up node, and a second end of the first storage capacitor is connected with a first signal output end;
the pull-down control unit comprises a fifth transistor and a ninth transistor, wherein a first pole and a control pole of the ninth transistor are both connected with a pull-down control signal, a second pole of the ninth transistor is connected with the pull-down unit, a first pole of the fifth transistor is connected with a first pole of the ninth transistor, the second pole of the fifth transistor is connected with a pull-down node, and the control pole of the ninth transistor is connected with a second pole of the ninth transistor;
the pull-down unit comprises a sixth transistor and an eighth transistor, wherein the first pole of the sixth transistor is connected with the pull-down node, the second pole of the sixth transistor is connected with the second power supply signal, the control pole of the sixth transistor is connected with the first pull-up node, the first pole of the eighth transistor is connected with the second pole of the ninth transistor, the second pole of the eighth transistor is connected with the second power supply signal, and the control pole of the eighth transistor is connected with the first pull-up node;
the reset unit comprises a second transistor, wherein the first pole of the second transistor is connected with the first pull-up node, the second pole of the second transistor is connected with a reset power supply signal, and the control pole of the second transistor is connected with the reset signal;
the noise reduction unit comprises a tenth transistor and an eleventh transistor, wherein a first pole of the tenth transistor is connected with the first pull-up node, a second pole of the tenth transistor is connected with the second power supply signal, a control pole of the tenth transistor is connected with the pull-down node, a first pole of the eleventh transistor is connected with the first signal output end, a second pole of the eleventh transistor is connected with the second power supply signal, and the control pole of the eleventh transistor is connected with the pull-down node.
In some optional embodiments, the first cut-off unit includes a first cut-off transistor, a first pole of the first cut-off transistor is connected to the first pull-up node, a second pole of the first cut-off transistor is connected to the second power signal, and a control pole of the first cut-off transistor is connected to the third control signal; and/or the first cut-off unit comprises a second cut-off transistor, the first pole of the second cut-off transistor is connected with the second pull-up node, the second pole is connected with the second power supply signal, and the control pole is connected with the third control signal.
In some optional embodiments, the gate driving circuit further includes a second cut-off unit including a third cut-off transistor, a first pole of the third cut-off transistor is connected to the first signal output terminal, a second pole of the third cut-off transistor is connected to the second power signal, and a control pole of the third cut-off transistor is connected to the fourth control signal; and/or the power supply comprises a fourth cut-off transistor, wherein the first pole of the fourth cut-off transistor is connected with the second signal output end, the second pole of the fourth cut-off transistor is connected with the second power supply signal, and the control pole of the fourth cut-off transistor is connected with the fourth control signal.
A second aspect of the present application provides an array substrate comprising the gate driving circuit as in the first aspect.
A third aspect of the present application provides a display device comprising the array substrate as in the second aspect.
A fourth aspect of the present application provides a driving method using the gate driving circuit as in the first aspect, including: the first driving unit of the shift register unit outputs a first driving signal according to the input first control signal, the first power signal and the first clock signal, and the first driving signal is input into the first driving unit of the next-stage shift register unit; the second driving unit of the shift register unit judges whether to output a second driving signal according to an input second control signal and the first driving signal and outputs the second driving signal in response to a second clock signal, the second control signal comprises a row selection signal transmitted by a row selection signal line connected with the second driving unit of each stage of shift register unit of the gate driving circuit, the second driving signal is used for providing a gate signal for a sub-pixel row of the display device corresponding to the shift register unit, and the second driving signal is input into the second driving unit of the next stage of shift register unit; the first cut-off unit of the shift register unit outputs a cut-off signal to the first driving unit according to the input third control signal to stop outputting the first driving signal, and/or outputs a cut-off signal to the second driving unit according to the input third control signal to stop outputting the second driving signal.
In some alternative embodiments, the second driving unit includes: the output selection unit, the second pull-up unit and the setting unit, the second driving unit of the shift register unit determining whether to output the second driving signal according to the input second control signal and the first driving signal, and outputting the second driving signal in response to the second clock signal further includes: the output selection unit judges whether to select to output the second drive signal according to the input second control signal and the first drive signal, if so, the output selection unit controls the potential of a second pull-up node, and the second pull-up node is a connection node of the output selection unit, the second pull-up unit and the setting unit; the second pull-up unit outputs a second driving signal from a second signal output end according to a second clock signal under the control of the potential of a second pull-up node; the setting unit sets the potential of the second pull-up node and the second driving signal through a second power signal according to the second driving signal of the next-stage shift register unit.
The invention has the following beneficial effects:
aiming at the existing problems, the invention sets a grid drive circuit, an array substrate, a display device and a drive method, and the second drive unit is additionally arranged on each stage of shift register unit, so that scanning is started from a specified line based on the combined action of the output of the first drive unit and a row selection signal input by a second drive control signal under the clock synchronization, and the ending line of the scanning is determined by the cut-off unit, thereby realizing the independent scanning control of a certain area, reducing the power loss of repeated full-screen scanning, simultaneously being capable of flexibly switching between the specified area scanning mode and the full-screen scanning mode, further realizing the low cost of a narrow frame and having wide application prospect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a gate driving circuit in the prior art.
Fig. 2 is a schematic structural block diagram of one shift register unit in a gate driving circuit according to an embodiment of the present application.
Fig. 3 is a schematic circuit diagram of one shift register unit in a gate driving circuit according to an embodiment of the present application.
Fig. 4 is a schematic block diagram of a gate drive circuit according to an embodiment of the present application.
Fig. 5 is a schematic timing diagram of key signals in a gate driving circuit according to an embodiment of the present application, wherein the scanning mode is a row-by-row scanning starting from a first row.
Fig. 6 is a schematic timing diagram of key signals in a gate driving circuit according to an embodiment of the present application, wherein the scanning mode is a progressive scanning starting from the second row.
Detailed Description
In order to more clearly illustrate the present invention, the present invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The references herein to "on … …", "formed on … …" and "disposed on … …" may mean that one layer is formed or disposed directly on another layer, or that one layer is formed or disposed indirectly on another layer, i.e., there are additional layers between the two layers. As used herein, unless otherwise noted, the term "in the same layer" means that two layers, components, members, elements or portions may be formed by the same patterning process, and the two layers, components, members, elements or portions are generally formed of the same material. Herein, unless otherwise specified, the expression "patterning process" generally includes the steps of coating of photoresist, exposure, development, etching, stripping of photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, or the like using one mask plate.
The transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, there is no difference between the source and the drain. In the embodiment of the present invention, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, the N-type transistors are used for explanation, when the N-type transistors are used, the first electrode is the drain electrode of the N-type transistor, the second electrode is the source electrode of the N-type transistor, when the gate electrode inputs a high level, the source electrode and the drain electrode are conducted, and when the gate electrode inputs a low level, the source electrode and the drain electrode are conducted. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without inventive effort and, thus, are within the scope of the embodiments of the present invention.
Before describing the embodiments of the present application, a conventional gate driving circuit in the related art will be explained first.
As shown in fig. 1, which shows a circuit schematic diagram of a shift register circuit of a single stage of a gate driving circuit in the related art. As can be seen from the figure, the pull-up unit formed by the transistor M3 and the capacitor C1 can store the charge signal VDS, and when the INPUT is active, the level of the clock signal CLK is given to the output terminal for output, so that the shift register unit under the control of the clock signal CLK is formed. When cascade connection is carried out, the OUTPUT signal OUTPUT of each stage is used as the INPUT of the next stage, and the OUTPUT signal OUTPUT of each stage drives the grid of the pixel corresponding to the shift register circuit of the stage to form the grid driving circuit. However, referring to fig. 1, in the gate driving circuit in the prior art, since the clock signal CLK in each stage is directly used as the driving signal of the gate, that is, the output of the pull-up unit directly outputs the driving gate, individual scanning of any row in the pixel array cannot be achieved, and only the row-by-row scanning can be started from the first row. Therefore, when the display panel only needs to have a partial area for writing signals or updating the display, the display panel still needs to be scanned in a full screen mode, power consumption is large, and unnecessary waste is caused.
The embodiment of the application provides a gate driving circuit, which is applied to a display device, wherein the display device comprises a plurality of rows of sub-pixels, the gate driving circuit comprises a plurality of cascaded shift register units, each shift register unit comprises a first driving unit, a second driving unit and a first cut-off unit, and each second driving unit is connected with a row selection signal line, wherein
A first driving unit configured to output a first driving signal according to the input first control signal, the first power signal and the first clock signal, the first driving signal being input to a first driving unit of a shift register unit of a next stage;
a second driving unit configured to determine whether to output a second driving signal according to an input second control signal and the first driving signal, and output the second driving signal in response to a second clock signal, the second control signal including a row selection signal transmitted by a row selection signal line, the second driving signal being used to provide a gate signal to a sub-pixel row of the display device corresponding to the shift register unit, the second driving signal being input to a second driving unit of a next stage of the shift register unit;
and a first cut-off unit configured to output a cut-off signal to the first driving unit to stop outputting the first driving signal according to the input third control signal, and/or configured to output a cut-off signal to the second driving unit to stop outputting the second driving signal according to the input third control signal.
In the embodiment, the second driving unit is additionally arranged on each stage of shift register unit, so that scanning is started from the designated line based on the combined action of the output of the first driving unit and the row selection signal input by the second driving control signal under the clock synchronization, and the ending line of the scanning is determined by the cut-off unit, thereby realizing the single scanning control of a certain area, reducing the power loss of repeated full-screen scanning, simultaneously flexibly switching between the designated area scanning mode and the full-screen scanning mode, further realizing the narrow-frame low-cost, and having wide application prospect.
In a specific embodiment, referring to fig. 2 to 4, fig. 4 shows a schematic block diagram of a gate driving circuit of the present application, fig. 2 is a schematic block diagram of a shift register unit of a cascade of shift register units in the gate driving circuit, and fig. 3 is a schematic circuit diagram of a shift register unit of a stage, where n is a positive integer. It will be understood by those skilled in the art that, for reasons of space and convenience of description, only the cascade of four-level shift register units is shown in fig. 4, but the present application is not limited thereto, and the specific number of cascades in practical applications depends on the number of rows of sub-pixels of the display device to be driven.
As shown in fig. 2 and 4, each stage of the shift register unit includes a first driving unit, a second driving unit, and a first cut-off unit. The first driving unit receives the first control signal IN1, the first power signal VDS, and the first clock signal CLK1, outputs a first driving signal Gn (where n denotes an nth stage IN the cascaded shift register units, and n is a positive integer) according to the input signals, and further inputs the first driving signal Gn to a first driving unit of a next stage as a first control signal IN1 of the next stage. The second driving unit receives a second control signal IN2, the first driving signal Gn and a second clock signal CLK2, wherein the second control signal IN2 comprises a row selection signal STVX and a second driving signal output by a previous stage of shift register unitGn. In this embodiment, the second driving unit of each stage is connected to the row selection signal line to receive the row selection signal STVX. The second driving unit judges whether to output the second driving signal Gn or not according to the input second control signal IN2 and the first driving signal GnGnAnd outputs a second driving signal driven by the second clock signal CLK2GnThe second drive signalGnFor providing gate signals to the sub-pixel rows of the display device, each stage of the shift register unit corresponds to one sub-pixel row, and the second drive signalGnAnd also as the gating signal of the next row, the signal is input to the second driving unit of the shift register unit of the next stage. Thereby realizing line scanning of the designated area in response to the driving of the second control signal by the first driving unit and the second driving unit; meanwhile, the determination of the last line of the designated area is achieved by the first cutoff unit. Specifically, the first cut-off unit outputs the cut-off signal VGL to the first driving unit to stop outputting the first driving signal Gn according to the input third control signal STV0, and optionally, may also output the cut-off signal VGL to the second driving unit to stop outputting the second driving signal Gn according to the input third control signal STV0GnOptionally, it may also be responsive to a third control signalThe signal STV0 simultaneously outputs the cutoff signal VGL to the first driving unit and the second driving unit through the first cutoff unit to stop outputting the second driving signalGn. In the embodiment, by additionally providing the second driving unit, the start row of the designated scanning area can be selected in response to the row selection signal, the first driving signal Gn, and the second clock signal CLK2, and the row selection signal is output at a time corresponding to the start row in one frame, so that the corresponding shift register unit starts scanning on a row requiring signal input or update, and in addition, the output of the shift register unit is stopped by the first stopping unit provided in each stage of shift register unit, thereby realizing scanning control of a row in any area by matching the start scanning and the stop scanning.
It should be noted that in this application, the clock signal switched into the first driving unit is referred to as a first clock signal CLK1, and the clock signal switched into the second driving unit is referred to as a second clock signal CLK2. In cascade connection, the shift register units of each stage are accessed by using clock signals CLKA and CLKB as first clock signals CLK1 and CLK2 alternately.
In a specific example, as shown in fig. 2, the first driving unit includes an input unit, a first pull-up unit, a pull-down control unit, a pull-down unit, a reset unit, and a noise reduction unit.
The input unit controls the potential of a first pull-up node PU1 according to an input first control signal IN1 and a first power signal VDS, where the first pull-up node PU1 is a connection node between the input unit, the first pull-up unit, and the pull-down unit. The first pull-up unit outputs the first drive signal Gn from the first signal output terminal according to the first clock signal CLK1 under the control of the potential of the first pull-up node PU1. The pull-down control unit controls the potential of a pull-down node PD, which is a connection node between the pull-down control unit and the pull-down unit, according to a pull-down control signal GCH. The pull-down unit is configured to pull down the potential of the pull-down node PD by the second power signal VGL under the control of the potential of the first pull-up node PU1. The Reset unit is configured to Reset the first pull-up node PU1 by a Reset power signal VSD under the control of a Reset signal Reset. The noise reduction unit is configured to pull down the potentials of the first pull-up node PU1 and the first signal output terminal by the second power signal VGL under the control of the potential of the pull-down node PD.
Further specifically, as shown IN fig. 3, the input unit includes a first transistor M1, a drain of the first transistor M1 is connected to the first power signal VDS, a source of the first transistor M1 is connected to the first pull-up node PU1, and a control electrode of the first transistor M1 is connected to the first control signal IN1.
IN this embodiment, as shown IN fig. 5, when the first control signal IN1 of the first stage shift register unit is the active signal STV, the first transistor M1 is turned on, and the potential of the first pull-up node PU1 is pulled up to VDS according to the first power signal VDS input by the drain.
Further specifically, as shown in fig. 3, the first pull-up unit includes a first control transistor M3 and a first storage capacitor C1, wherein a drain of the first control transistor M3 is connected to the first clock signal CLK1, a source thereof is connected to the first signal output terminal to output the first driving signal Gn, a control electrode thereof is connected to the first pull-up node PU1, a first terminal of the first storage capacitor C1 is connected to the first pull-up node PU1, and a second terminal thereof is connected to the first signal output terminal.
In the present embodiment, as shown in fig. 5, when the first pull-up node PU1 is pulled up to VDS to charge the first storage capacitor C1, and the first control signal STV is turned to be inactive, the first pull-up node PU1 still keeps the current potential, and in response to the first clock signal CLK1, the first control transistor M3 is turned on to output the high level input by the first clock signal CLK1 as the first driving signal G1.
Further specifically, as shown in fig. 3, the pull-down control unit includes a fifth transistor M5 and a ninth transistor M9, wherein a drain and a control electrode of the ninth transistor M9 are both connected to the pull-down control signal GCH, a source electrode is connected to the pull-down unit, a drain electrode of the fifth transistor M5 is connected to the drain electrode of the ninth transistor M9, a source electrode is connected to the pull-down node PD, and a control electrode is connected to the source electrode of the ninth transistor M9.
In the present embodiment, the pull-down control unit controls the potential of the pull-down node PD in response to the pull-down control signal GCH, and when the pull-down control signal GCH is a high level signal, the ninth transistor M9 is turned on, and further the fifth transistor M5 is turned on, and the potential of the pull-down node PD is pulled up by the high level of the pull-down control signal GCH.
Further specifically, as shown in fig. 3, the pull-down unit includes a sixth transistor M6 and an eighth transistor M8, wherein a drain of the sixth transistor M6 is connected to the pull-down node PD, a source thereof is connected to the second power signal VGL, a control electrode thereof is connected to the first pull-up node PU1, a drain of the eighth transistor M8 is connected to a source thereof which is connected to the second power signal VGL, and a control electrode thereof is connected to the first pull-up node PU1.
In this embodiment, when the first pull-up node PU1 is at a high potential, the pull-down unit turns on the sixth transistor M6 and the eighth transistor M8 under the control of the potential of the first pull-up node PU1, and pulls down the potential of the pull-down node PD to VGL according to the second power signal VGL.
Further specifically, as shown in fig. 3, the Reset unit includes a second transistor M2 having a drain connected to the first pull-up node PU1, a source connected to a Reset power signal VSD, and a control electrode connected to the Reset signal Reset, and it will be understood by those skilled in the art that the Reset power signal VSD is a low level signal.
In the present embodiment, in response to the high level of the Reset signal Reset, the second transistor M2 is turned on, and the potential of the pull-up node PU1 is pulled down by the Reset power supply signal VSD, thereby realizing the Reset of the pull-up node PU1.
Further specifically, as shown in fig. 3, the noise reduction unit includes a tenth transistor M10 and an eleventh transistor M11, wherein a drain of the tenth transistor M10 is connected to the first pull-up node PU1, a source thereof is connected to the second power signal VGL, a control electrode thereof is connected to the pull-down node PD, a drain of the eleventh transistor M11 is connected to the first signal output terminal, a source thereof is connected to the second power signal VGL, and a control electrode thereof is connected to the pull-down node PD.
In the present embodiment, in response to the high potential of the pull-down node PU1, the tenth transistor M10 and the eleventh transistor M11 are turned on, the potential of the pull-up node PU1 is pulled down to VGL according to the second power signal VGL, and the potential of the first driving signal is pulled down to VGL according to the second power signal VGL.
As shown in fig. 2, the second drive unit packThe output selection unit, the second pull-up unit and the setting unit are included. Wherein the output selection unit determines whether to select the output of the second drive signal based on the input second control signal IN2 and the first drive signal GnGnAnd if the output is positive, the potential of a second pull-up node PU2 is controlled, and the second pull-up node PU2 is a connecting node of the output selection unit, the second pull-up unit and the setting unit. The second pull-up unit outputs a second driving signal from the second signal output terminal according to a second clock signal CLK2 under the control of the potential of the second pull-up node PU2Gn. The setting unit is used for shifting the second drive signal of the register unit according to the next stageGn+1Setting the potential of the second pull-up node PU2 and the second driving signal by the second power signal VGLGn。
Further specifically, as shown in fig. 3, the output selection unit includes a first selection transistor M13 and a second selection transistor M14, a drain of the first selection transistor M13 is connected to the first driving signal Gn, a source thereof is connected to the second pull-up node PU2, and a control electrode thereof is connected to the selection signal line to be connected to the row selection signal STVX. The drain of the second selection transistor M14 is connected to the first driving signal Gn, the source is connected to the second pull-up node PU2, and the control electrode is connected to the second driving signal of the previous stage shift register unitGn-1。
Specifically, when n =1, that is, the current shift register unit is the first stage of the cascade shift register unit in the gate driving circuit, the first driving signal Gn represents an initial signalG0。
The first selection transistor M13 and the second selection transistor M14 have common-terminal drains and sources, which constitute an or gate; meanwhile, the drain of the first selection transistor M13 is connected to the first driving signal Gn, and the drain of the second selection transistor M14 is connected to the first driving signal Gn, that is, the first selection transistor M13 and the output terminal of the first driving unit form an and gate, and the second selection transistor M14 and the output terminal of the first driving unit also form an and gate. That is, the output terminal of the first driving unit is high while any one of the first and second selection transistors M13 and M14 is turned on, and the output of the output selection unit is high. Accordingly, the control electrode of the second selection transistor M14 input by the second driving unit of the shift register unit of the first stage is connected to the low-level initial signal because of the or gate relationship.
Further specifically, as shown in fig. 3, the second pull-up unit includes a second control transistor M12 and a second storage capacitor C2, a drain of the second control transistor M12 is connected to the second clock signal CLK2, and a source thereof is connected to the second signal output terminal to output the second driving signalGnThe control electrode is connected with the second pull-up node PU2, the first end of the second storage capacitor C2 is connected with the second pull-up node PU2, and the second end is connected with the second signal output end.
Through the above connection manner, the second control transistor M12 and the second storage capacitor C2 form a bootstrap circuit, when the first end of the second storage capacitor C2 is high, the second storage capacitor C2 is charged, along with the charging of the capacitor, the potential difference between the control electrode and the source electrode of the second control transistor M12 increases, and when the potential difference increases to enable the second control transistor M12 to be turned on, the bootstrap circuit generates bootstrap, and outputs the second clock signal CLK2 connected to the drain electrode of the second control transistor M12 as an output signal to output the second driving signalGn。
In the present embodiment, as shown in fig. 5, the first clock signal CKL1 and the second clock signal CLK2 are coupled into each stage in the manner shown in fig. 4. The analysis is started with a period in which the first drive unit makes the first drive signal G1 high based on the control of the first control signal STV.
For the first stage shift register unit, the first clock signal CLK1 is the signal CLKA, the second clock signal CLK2 is the signal CLKB, when the first driving signal G1 output by the first driving unit is high, the initial signal accessed by the second selection transistor M14 is low and not conducted at this time, but the row selection signal STVX accessed by the first selection transistor M13 is high, and the first selection transistor M13 is conducted under the control of the row selection signal STVX. That is, the second control signal IN2 is active, the second storage capacitor C2 IN the second pull-up unit is charged according to the first driving signal G1, when the second clock signal CLK2 becomes active at a high level, the second storage capacitor C2 is charged enough to bootstrap the second pull-up unit, that is, the second control transistor M12 is turned on, and the second driving unit responds to the input second clock signal CLK2High level output second driving signalG1. The present embodiment selects scanning from the first row by the second control signal including the row selection signal STVX.
At the same time, the second driving signal of the first stage shift register unitG1The high interval, for the second stage shift register unit, the second driving signal of the first stage shift register unit is switched on because the control electrode of the second selection transistor M14G1The second selection transistor M14 is turned on to determine the output of the second driving signalG2And the first driving signal G2 of the second-stage shift register unit which is at the high level at this time is connected into the second storage capacitor C2 of the second pull-up unit for pre-charging. That is, the second control signal IN2 is asserted, IN response to the signal CLKA, which is the second clock signal CLK2 connected to the second driving unit of the second stage shift register unit, becoming high, the second storage capacitor C2 is charged enough to bootstrap the second pull-up unit, that is, the second control transistor M12 is turned on, the second driving unit outputs the second driving signalG2Is high. Continuous scan output can therefore be achieved by this embodiment.
Further specifically, as shown in fig. 3, in order to simplify the circuit, the setting unit is provided to include a first setting transistor M15 and a second setting transistor M16. The drain of the first set transistor M15 is connected to the second pull-up node PU2, the source is connected to the second power signal CLK2, and the control electrode is connected to the second driving signal of the next stage of shift register unitGn+1(ii) a The drain of the second set transistor M16 is connected to the second signal output terminal, the source is connected to the second power signal VGL, and the control electrode is connected to the second driving signal of the next stage of shift register unitGn+ 1。
In this embodiment, the second driving signal passes through the shift register unit of the next stageGn+1For the second drive signal of the current stageGnPerforming reverse setting, i.e. the next stage of shift register unit outputs the second drive signalGn+1The second drive signal of the current stageGnSet low to realize line-by-line closing in the scanning process. It should be understood by those skilled in the art that the second driving according to the shift register unit of the next stage is realized by the simplified set unit only in the embodimentThe setting of the potential of the second pull-up node and the second driving signal by the dynamic signal is described in the present application, which is not specifically limited in the present application. Those skilled in the art should select an appropriate setting manner according to the actual application requirement to realize the function of the gate driving circuit as a design rule, and details are not described herein.
In an alternative embodiment, as shown in fig. 3, the first cut-off unit includes a first cut-off transistor M4, a drain of the first cut-off transistor M4 is connected to the first pull-up node PU1, a source thereof is connected to the second power signal VGL, and a control thereof is connected to the third control signal STV0.
In this embodiment, when the third control signal STV0 is active at a high level, the first cut-off transistor M4 is turned on, and the potential of the first pull-up node PU1 is set by the second power signal VGL, so as to cut off the first driving unit to output the first driving signal, thereby stopping the scanning of the shift register unit.
In another alternative embodiment, as shown in fig. 3, the first cut-off unit includes a second cut-off transistor M17, a drain of which is connected to the second pull-up node PU2, a source of which is connected to the second power signal VGL, and a control electrode of which is connected to the third control signal STV0.
In this embodiment, when the third control signal STV0 is active at a high level, the second cut-off transistor M17 is turned on, and the second power signal VGL sets the potential of the second pull-up node PU2, so as to cut off the second driving unit to output the second driving signal, thereby stopping the scanning of the shift register unit.
In this embodiment, the first cut-off unit may include only the first cut-off transistor M4 or the second cut-off transistor M17, or may include both the first cut-off transistor M4 and the second cut-off transistor M17, so as to stop outputting the second driving signal, that is, stop the last line scan of the designated area by the first cut-off unit.
It should be noted that, as will be understood by those skilled in the art, when both M4 and M17 are used simultaneously, not only the certainty of stopping the selection of a specific region can be improved, but also the reliability of the gate driving circuit can be protected, and when the entire-screen scanning mode is switched to the region scanning mode, or the region scanning mode is switched to the entire-screen scanning mode, the screen is cleared, that is, when the scanning mode is changed, the screen is cleared through M4 and M17 to avoid the display device from having residual display, so as to effectively improve the display effect and the user experience.
In an optional embodiment, the gate driving circuit further includes a second cut-off unit, which includes a third cut-off transistor M7, a drain of the third cut-off transistor M7 is connected to the first signal output terminal, a source is connected to the second power signal VGL, and a control electrode is connected to the fourth control signal GCL.
In another optional embodiment, the gate driving circuit further includes a second cut-off unit, which includes a fourth cut-off transistor M18, a drain of the fourth cut-off transistor M18 is connected to the second signal output terminal, a source is connected to the second power signal VGL, and a control electrode is connected to the fourth control signal CGL.
Similar to the previous embodiment, the second turning-off unit may include only the third turning-off transistor M7 or the fourth turning-off transistor M18, or may include both the third turning-off transistor M7 and the fourth turning-off transistor M18, for the purpose of stopping outputting the second driving signal, that is, stopping the last line scan of the designated area by the first turning-off unit.
The structure and function of the embodiment of the present application will be further described with reference to the timing diagrams of the two scanning modes shown in fig. 5 and 6. Fig. 5 is a schematic timing diagram of key signals in a gate driving circuit according to an embodiment of the present application, in which a scanning manner is a progressive scanning starting from a first row; fig. 6 is a schematic timing diagram of key signals in a gate driving circuit according to an embodiment of the present application, where the scanning mode is progressive scanning from the second row, and only the cascade of four stages of shift register units is shown in the diagram for simplicity of explanation. As can be seen from comparing fig. 5 and fig. 6, according to the gate driving circuit of the embodiment of the present application, when the shift register units of each stage are cascaded according to the method of the embodiment of the present application, under the control of the first control signal IN1, where the first control signal IN1 of the first stage is STV, the first driving unit is driven based on the first clock signal CLK1 (here, CLKA and CLKB that are alternately input as the first clock signal) to output the first driving signal, and the first driving signals G1, G2, G3, and G4 of the shift register units of each stage sequentially output the high level of the effective signal.
And differently, whether to output the second driving signal is determined IN response to a different second control signal IN2 input from the second driving unit.
Specifically, IN the progressive scanning mode starting from the first row as shown IN fig. 5, the second control signal IN2 of the first stage shift register unit is the row selection signal STVX, and the row selection signal STVX is an active high signal, and a pulse is delayed relative to the first control signal IN1 and input to the second driving unit, so that the second driving unit of the first stage shift register unit determines that the second driving unit outputs the second driving signal according to the input row selection signal STVX and the first driving signal G1 output by the first driving unit, and outputs the second driving signal IN response to the input second clock signal CLK2G2As shown in FIG. 5, the second driving signalG2And outputting a high level signal. Meanwhile, the second driving signal output by the first stage shift register unitG2The second control signal IN2 as the next stage shift register unit is input to the second driving unit to drive the next stage shift register unit to output the second driving signal.
Thus, when the progressive scanning is performed from the first row, as shown IN fig. 5, the gate driving circuit of the four-stage shift register unit sequentially outputs the second driving signal with a high level IN response to the first control signal IN1, the first clock signal CLK1, the second control signal IN2, and the second clock signal CLK2Gn(Here, it isG1ToG4) When the shift register units from the first stage to the fourth stage complete output, the scanning of the current frame is completed, the scanning is started from the first stage to the fourth stage line by line at the next frame moment, and the display of the display device from the first line is realized by the scanning from line to line in cycles.
It should be noted that, in this embodiment, the full-screen scanning may be performed from the first line, or the scanning may be performed on the designated area from the first line, for example, the last line of the designated area is selected by the first cutoff unit, which is not specifically limited in this embodiment.
Specifically, IN the progressive scanning mode starting from the second row as shown IN fig. 6, the first driving unit of the first stage shift register unit outputs the first driving signal, and the second driving unit does not output the second driving signal because no valid second control signal IN2 is input. The first driving unit of the second stage shift register unit outputs the first driving signal G2 IN response to the first driving signal G1 outputted from the first stage shift register unit inputted as the first control signal IN1 thereof, while the second driving unit of the second stage shift register unit outputs the second driving signal according to the second clock signal CLK2 inputted thereto, and the second driving unit of the second stage shift register unit judges that the second driving unit outputs the second driving signal according to the inputted row selection signal STVX and the first driving signal G1 outputted from the first driving unit thereof, and outputs the second driving signal IN response to the second clock signal CLK2 inputted theretoG2As shown in FIG. 6, the second driving signalG2And outputting a high level signal. At the same time, the second drive signal output by the second stage shift register unitG2The second control signal IN2 as the next stage shift register unit is input to the second driving unit to drive the next stage shift register unit to output the second driving signal.
Thus, the progressive scanning from the second row is realized, as shown IN fig. 6, the gate driving circuit of the four-stage shift register unit scans the designated area IN response to the first control signal IN1, the first clock signal CLK1, the second control signal IN2 and the second clock signal CLK2, because the second control signal IN2 is delayed from the first control signal IN1 by the scanning time length of two rows to input the row selection signal STVX, i.e., the second driving signal is selected and output from the second-stage shift register unit, as shown IN fig. 6, the first-stage to fourth-stage shift register units all output the first driving signal Gn (here, G1 to G4), and the first-stage to fourth-stage shift register units all output the second driving signal Gn from the second stageGn(Here, it isG2ToG4). When the shift register units from the second stage to the fourth stage complete the output, the scanning of the current frame is completed, and the scanning starts from the second stage at the next frame timeAnd scanning the designated area to the fourth stage, and repeatedly realizing the display of the designated area of the display device through the designated scanning.
In the embodiment, the second driving unit is additionally arranged on each stage of shift register unit, so that scanning is started from a specified line based on the combined action of the output of the first driving unit and the row selection signal input by the second driving control signal under clock synchronization, and the ending line of scanning is determined by the cut-off unit, so that the single scanning control of a certain area is realized, the power loss of repeated full-screen scanning is reduced, meanwhile, the mode can be flexibly switched between the specified area scanning mode and the full-screen scanning mode, the low cost of a narrow frame is further realized, and the method has wide application prospect.
A second aspect of the present application provides an array substrate including the gate driving circuit described in any of the embodiments of the present application.
In this embodiment, the second driving unit is additionally arranged in the gate driving circuit included in the array substrate, so that a specific line is selected to start scanning based on the combined action of the output of the first driving unit and the line selection signal input by the second driving control signal under clock synchronization, and independent scanning control over a certain area is realized through the cooperation with the cut-off unit, thereby reducing the encumbrance of repeated full-screen scanning, realizing flexible switching, reducing power consumption, realizing low cost, and having wide application prospects. The specific implementation manner of this embodiment is the same as that of the previous embodiment, and is not described herein again.
A third aspect of the present application provides a display device including the array substrate of the embodiment of the present application. It should be understood by those skilled in the art that, according to the present embodiment, if the display device is in the form of an LCD, the display device includes an array substrate and a color filter substrate, if the display device is in the form of an OLED, the display device includes an array substrate, charged particles, and a facing substrate, if the display device is an electronic paper.
In the embodiment, the second driving unit is additionally arranged in the gate driving circuit for driving the sub-pixels of the display device, so that a specific line is selected to start scanning based on the combined action of the output of the first driving unit and the line selection signal input by the second driving control signal under the clock synchronization, and the independent scanning control of a certain area is realized through the cooperation with the cut-off unit, thereby reducing the encumbrance of repeated full-screen scanning, realizing flexible switching, reducing power consumption, realizing low cost and having wide application prospect. The specific implementation manner of this embodiment is the same as that of the previous embodiment, and is not described herein again.
It should be noted that the gate driving circuit according to the embodiments of the present application can be applied to various display devices, and those skilled in the art should understand that any display device based on the operation mode of the gate driving circuit of the present application is within the scope of the present application.
A fourth aspect of the present application provides a driving method using the gate driving circuit of the embodiment of the present application, including:
the first driving unit of the shift register unit outputs a first driving signal according to the input first control signal, the first power signal and the first clock signal, and the first driving signal is input into the first driving unit of the next-stage shift register unit;
the second driving unit of the shift register unit judges whether to output a second driving signal according to an input second control signal and the first driving signal and outputs the second driving signal in response to a second clock signal, the second control signal comprises a row selection signal transmitted by a row selection signal line connected with the second driving unit of each stage of shift register unit of the gate driving circuit, the second driving signal is used for providing a gate signal for a sub-pixel row of the display device corresponding to the shift register unit, and the second driving signal is input into the second driving unit of the next stage of shift register unit;
the first cut-off unit of the shift register unit outputs a cut-off signal to the first driving unit according to the input third control signal to stop outputting the first driving signal, and/or outputs a cut-off signal to the second driving unit according to the input third control signal to stop outputting the second driving signal.
In this way, a specific row can be selected to start scanning in clock synchronization based on the combined action of the output of the first driving unit and the row selection signal input by the second driving control signal, and the individual scanning control of a certain region can be realized by the cooperation with the cutoff unit. The specific implementation manner of this embodiment is the same as that of the previous embodiment, and is not described herein again.
In an alternative embodiment, the second driving unit comprises: the output selection unit, the second pull-up unit and the setting unit, the second driving unit of the shift register unit determining whether to output the second driving signal according to the input second control signal and the first driving signal, and outputting the second driving signal in response to the second clock signal further includes: the output selection unit judges whether to select to output the second drive signal according to the input second control signal and the first drive signal, if so, the output selection unit controls the potential of a second pull-up node, and the second pull-up node is a connecting node of the output selection unit, the second pull-up unit and the setting unit; the second pull-up unit outputs a second driving signal from a second signal output end according to a second clock signal under the control of the potential of a second pull-up node; the setting unit sets the potential of the second pull-up node and the second driving signal through a second power signal according to the second driving signal of the next-stage shift register unit.
In this way, a specific row can be selected to start scanning in clock synchronization based on the combined action of the output of the first driving unit and the row selection signal input by the second driving control signal, and the individual scanning control of a certain region can be realized by the cooperation with the cutoff unit. The detailed implementation of this embodiment is the same as that of the previous embodiment, and is not described herein again.
Aiming at the existing problems, the invention provides a grid drive circuit, an array substrate, a display device and a drive method, wherein a second drive unit is additionally arranged on each stage of shift register unit, so that scanning is started from a specified line based on the combined action of the output of a first drive unit and a row selection signal input by a second drive control signal under the clock synchronization, and the ending line of the scanning is determined by a cut-off unit, thereby realizing the independent scanning control of a certain area, reducing the power loss of repeated full-screen scanning, simultaneously being capable of flexibly switching between the scanning mode of the specified area and the full-screen scanning mode, further realizing the low cost of a narrow frame and having wide application prospect.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims (12)

1. A grid driving circuit is applied to a display device, the display device comprises a plurality of rows of sub-pixels, and the grid driving circuit is characterized by comprising a plurality of cascaded shift register units, each shift register unit comprises a first driving unit, a second driving unit and a first cut-off unit, each second driving unit is connected with a row selection signal line, wherein the grid driving circuit comprises a plurality of cascaded shift register units, each shift register unit comprises a first driving unit, a second driving unit and a first cut-off unit, and each second driving unit is connected with the row selection signal line, and the grid driving circuit comprises a plurality of first driving units, a plurality of second driving units and a plurality of second cut-off units
The first driving unit is configured to output a first driving signal according to an input first control signal, a first power signal and a first clock signal, a first driving unit of a first-stage shift register unit of the plurality of cascaded shift register units receives an externally input frame start signal as the first control signal, and the first driving signal of a shift register unit other than a last-stage shift register unit of the plurality of cascaded shift register units is input to a first driving unit of a next-stage shift register unit and is used as the first control signal;
the second driving unit is configured to determine whether to output a second driving signal according to an input second control signal and a first driving signal, and output the second driving signal in response to a second clock signal, where the second control signal includes a row selection signal and a second control sub-signal transmitted by the row selection signal line, the second driving signal is used to provide a gate signal to a sub-pixel row of the display device corresponding to the shift register unit, a second driving unit of a first stage shift register unit of the plurality of cascaded shift register units receives an externally input power signal as the second control sub-signal, and the second driving signal of a shift register unit other than a last stage shift register unit of the plurality of cascaded shift register units is input to a second driving unit of a next stage shift register unit and is used as the second control sub-signal;
the first cutoff unit is configured to output a cutoff signal to the first driving unit to stop outputting the first driving signal according to an input third control signal, and/or configured to output a cutoff signal to the second driving unit to stop outputting the second driving signal according to an input third control signal.
2. A gate drive circuit as claimed in claim 1, wherein the second drive unit comprises: an output selection unit, a second pull-up unit and a set unit, wherein
The output selection unit is configured to judge whether to select to output a second driving signal according to an input second control signal and the first driving signal, and if so, control the potential of a second pull-up node, wherein the second pull-up node is a connection node of the output selection unit, the second pull-up unit and the setting unit;
the second pull-up unit configured to output a second driving signal from a second signal output terminal according to a second clock signal under control of a potential of the second pull-up node;
the setting unit of the second driving unit of the shift register unit other than the last stage shift register unit of the plurality of cascaded shift register units is configured to set the potential of the second pull-up node and the second driving signal through a second power supply signal according to the second driving signal of the next stage shift register unit; and the setting unit of the second driving unit of the last stage of the plurality of cascaded shift register units is configured to set the potential of the second pull-up node and the second driving signal according to an input signal.
3. A gate drive circuit according to claim 2,
the output selection unit includes a first selection transistor and a second selection transistor, wherein
A first pole of the first selection transistor is connected to the first driving signal, a second pole of the first selection transistor is connected to the second pull-up node, a control pole of the first selection transistor is connected to the selection signal line to be connected to a row selection signal,
a first pole of the second selection transistor is connected to the first driving signal, a second pole of the second selection transistor is connected to the second pull-up node, a control stage of the second selection transistor of the output selection unit of the second driving unit of the first-stage shift register units of the plurality of cascaded shift register units receives an externally input power signal, and a control stage of the second selection transistor of the output selection unit of the second driving unit of the shift register units other than the first-stage shift register units of the plurality of cascaded shift register units is connected to the second driving signal of the previous-stage shift register unit;
the second pull-up unit comprises a second control transistor and a second storage capacitor; wherein the content of the first and second substances,
a first pole of the second control transistor is connected to a second clock signal, a second pole of the second control transistor is connected to the second signal output end to output a second driving signal, a control pole of the second control transistor is connected to the second pull-up node,
and the first end of the second storage capacitor is connected with the second pull-up node, and the second end of the second storage capacitor is connected with the second signal output end.
4. The gate driving circuit according to claim 2, wherein the set cell comprises a first set transistor and a second set transistor; wherein the content of the first and second substances,
a first pole of the first setting transistor is connected with the second pull-up node, a second pole of the first setting transistor is connected with the second power supply signal, and a control pole of the first setting transistor is connected with a second driving signal of a next-stage shift register unit;
the first pole of the second set transistor is connected with the second signal output end, the second pole of the second set transistor is connected with the second power supply signal, the control pole of the second set transistor of the set unit of the second drive unit of the shift register unit except the last stage shift register unit of the plurality of cascaded shift register units is connected with the second drive signal of the next stage shift register unit, and the control pole of the second set transistor of the set unit of the second drive unit of the last stage shift register unit of the plurality of cascaded shift register units is connected with the input signal to realize the setting of the last stage second drive signal.
5. The gate driving circuit of claim 1, wherein the first driving unit comprises an input unit, a first pull-up unit, a pull-down control unit, a pull-down unit, a reset unit, and a noise reduction unit, wherein,
the input unit is configured to control a potential of a first pull-up node according to an input first control signal and a first power signal, wherein the first pull-up node is a connection node among the input unit, the first pull-up unit and the pull-down unit;
the first pull-up unit configured to output a first driving signal from a first signal output terminal according to a first clock signal under control of a potential of the first pull-up node;
the pull-down control unit is configured to control the potential of a pull-down node according to a pull-down control signal, wherein the pull-down node is a connection node between the pull-down control unit and the pull-down unit;
the pull-down unit configured to pull down a potential of the pull-down node by a second power supply signal under control of the potential of the first pull-up node;
the reset unit is configured to reset the first pull-up node by a reset power signal under the control of a reset signal;
the noise reduction unit is configured to pull down potentials of the first pull-up node and the first signal output terminal by a second power supply signal under control of a potential of the pull-down node.
6. A gate drive circuit as claimed in claim 5,
the input unit comprises a first transistor, a first electrode of the first transistor is connected to the first power supply signal, a second electrode of the first transistor is connected to the first pull-up node, and a control electrode of the first transistor is connected to the first control signal;
the first pull-up unit includes a first control transistor and a first storage capacitor, wherein,
a first electrode of the first control transistor is connected to the first clock signal, a second electrode of the first control transistor is connected to the first signal output end to output a first driving signal, a control electrode of the first control transistor is connected to the first pull-up node,
the first end of the first storage capacitor is connected with the first pull-up node, and the second end of the first storage capacitor is connected with the first signal output end;
the pull-down control unit includes a fifth transistor and a ninth transistor, wherein,
a first electrode and a control electrode of the ninth transistor are both connected to the pull-down control signal, a second electrode of the ninth transistor is connected to the pull-down unit,
a first pole of the fifth transistor is connected with a first pole of the ninth transistor, a second pole of the fifth transistor is connected with the pull-down node, and a control pole of the fifth transistor is connected with a second pole of the ninth transistor;
the pull-down unit includes a sixth transistor and an eighth transistor, wherein,
a first pole of the sixth transistor is connected with the pull-down node, a second pole of the sixth transistor is connected with the second power supply signal, a control pole of the sixth transistor is connected with the first pull-up node,
a first pole of the eighth transistor is connected with a second pole of the ninth transistor, the second pole of the eighth transistor is connected with the second power supply signal, and a control pole of the eighth transistor is connected with the first pull-up node;
the reset unit comprises a second transistor, wherein a first pole of the second transistor is connected with the first pull-up node, a second pole of the second transistor is connected with the reset power supply signal, and a control pole of the second transistor is connected with the reset signal;
the noise reduction unit includes tenth and eleventh transistors, wherein,
a first pole of the tenth transistor is connected to the first pull-up node, a second pole of the tenth transistor is connected to the second power signal, a control pole of the tenth transistor is connected to the pull-down node,
a first pole of the eleventh transistor is connected to the first signal output end, a second pole of the eleventh transistor is connected to the second power signal, and a control pole of the eleventh transistor is connected to the pull-down node.
7. A gate drive circuit as claimed in claim 1,
the first cut-off unit comprises a first cut-off transistor, wherein a first pole of the first cut-off transistor is connected with a first pull-up node, a second pole of the first cut-off transistor is connected with a second power supply signal, and a control pole of the first cut-off transistor is connected with a third control signal;
and/or
The first cut-off unit comprises a second cut-off transistor, a first pole of the second cut-off transistor is connected with the second pull-up node, a second pole of the second cut-off transistor is connected with the second power supply signal, and a control pole of the second cut-off transistor is connected with the third control signal.
8. The gate driving circuit of claim 1, further comprising a second cut-off unit,
the first pole of the third cut-off transistor is connected with the first signal output end, the second pole of the third cut-off transistor is connected with the second power supply signal, and the control pole of the third cut-off transistor is connected with the fourth control signal;
and/or
The first pole of the fourth cut-off transistor is connected with the second signal output end, the second pole of the fourth cut-off transistor is connected with the second power supply signal, and the control pole of the fourth cut-off transistor is connected with the fourth control signal.
9. An array substrate comprising the gate driver circuit of any one of claims 1 to 8.
10. A display device comprising the array substrate according to claim 9.
11. A driving method using the gate driving circuit according to any one of claims 1 to 8, comprising:
a first driving unit of the shift register units outputs a first driving signal according to an input first control signal, a first power signal and a first clock signal, a first driving unit of a first-stage shift register unit of the plurality of cascaded shift register units receives an externally input frame start signal as the first control signal, and the first driving signal of a shift register unit other than a last-stage shift register unit of the plurality of cascaded shift register units is input to a first driving unit of a next-stage shift register unit and serves as the first control signal;
the second driving unit of the shift register unit judges whether to output a second driving signal according to an input second control signal and a first driving signal, and outputs the second driving signal in response to a second clock signal, the second control signal includes a row selection signal and a second control sub-signal transmitted by a row selection signal line connected with the second driving unit of each stage of shift register unit of the gate driving circuit, the second driving signal is used for providing a gate signal to a sub-pixel row of the display device corresponding to the shift register unit, the second driving unit of the first stage of shift register units of the plurality of cascaded shift register units receives an externally input power signal as the second control sub-signal, and the second driving signal of the shift register unit other than the last stage of shift register units of the plurality of cascaded shift register units is input to the second driving unit of the next stage of shift register unit and is used as the second control sub-signal;
the first cut-off unit of the shift register unit outputs a cut-off signal to the first driving unit according to an input third control signal to stop outputting the first driving signal, and/or outputs a cut-off signal to the second driving unit according to an input third control signal to stop outputting the second driving signal.
12. The driving method according to claim 11, wherein the second driving unit includes: the output selection unit, the second pull-up unit and the setting unit, the second driving unit of the shift register unit determining whether to output the second driving signal according to the input second control signal and the first driving signal, and outputting the second driving signal in response to the second clock signal further includes:
the output selection unit judges whether to select to output a second driving signal according to an input second control signal and a first driving signal, if so, the output selection unit controls the potential of a second pull-up node, and the second pull-up node is a connecting node of the output selection unit, the second pull-up unit and the setting unit;
the second pull-up unit outputs a second driving signal from a second signal output end according to a second clock signal under the control of the potential of the second pull-up node;
and the setting unit of the second driving unit of the last stage shift register unit of the plurality of cascaded shift register units sets the potential of the second pull-up node and the second driving signal according to the second driving signal of the next stage shift register unit through a second power supply signal, and sets the potential of the second pull-up node and the second driving signal according to the input signal.
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