CN111931451A - Transmit-receive TR (transmitter-receiver) component design method based on low temperature co-fired ceramic LTCC (Low temperature Co-fired ceramic) - Google Patents

Transmit-receive TR (transmitter-receiver) component design method based on low temperature co-fired ceramic LTCC (Low temperature Co-fired ceramic) Download PDF

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CN111931451A
CN111931451A CN202010804229.6A CN202010804229A CN111931451A CN 111931451 A CN111931451 A CN 111931451A CN 202010804229 A CN202010804229 A CN 202010804229A CN 111931451 A CN111931451 A CN 111931451A
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董刚
孟令东
朱樟明
杨银堂
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Abstract

The invention discloses a design method of a transmitting and receiving TR component based on low temperature co-fired ceramic LTCC (Low temperature Co-fired ceramic), which mainly solves the problems of low performance and large volume of the existing TR component. The scheme is as follows: determining the chip type and the substrate material of the TR component device according to the link indexes; the TR component is divided into a microwave circuit, a digital circuit and a power circuit; drawing a circuit layout on a substrate, simulating in ADS software, and extracting S parameters; generating a 3D layout in HFSS software and simulating the 3D layout; adjusting the moving layout according to the simulation result to obtain the size of the 3D layout; and determining the size of the cavity according to the size of the 3D layout, the shrinkage rate error rate of the substrate and the process requirement, and simulating to enable the resonant frequency and the higher harmonic frequency of the cavity to be higher than and far away from the working frequency of the component. The invention improves the receiving link gain and the transmitting link output power of the TR component, reduces the noise coefficient and the volume, realizes the digital-analog integration, and can be used for a phased array radar and a microwave system.

Description

Transmit-receive TR (transmitter-receiver) component design method based on low temperature co-fired ceramic LTCC (Low temperature Co-fired ceramic)
Technical Field
The invention belongs to the technical field of microwaves, and particularly relates to a design method of a transmitting-receiving TR component, which can be used for a phased array radar and a microwave system.
Background
With the development of electronic information theory technology, the performance required by radar weaponry and electronic countermeasures is continuously developing towards miniaturization and integration.
The T/R component is a core module forming a modern active phased array radar and has great influence on the performance of the radar. The rapid development of modern active phased array technology requires that the size of the transceiver module be reduced as much as possible.
The transceiver TR component is equivalent to a tuner of a common radar, and comprises a transmitting power amplifier, a low-noise amplifier, a phase shifter, a beam control circuit and other functional circuits. The TR component is required to be high in integration level, good in consistency, small in size and light in weight, and can adapt to different working platforms and environments. At present, the quantity of high-frequency-band transmitting and receiving TR components on the domestic market is small, the structure of the existing product is complex, the size is large, the integration level is low, and the transmitting and receiving TR radio frequency channel is lack of effective amplitude phase modulation.
The fifty-five research institute of electrical science is also engaged in more research works of three-dimensional assembly technology, and the research institute makes great progress on microwave assembly TR components realized based on multilayer substrate technology. However, the three-dimensional assembly designed by the technology still has the problems of large volume and insufficient integration level.
In 2015, a Ka-band T/R component was realized by a printed circuit board and a multilayer substrate wiring technology used by Middleto. The assembly has sixteen channels, each including a 6-bit digitally controlled phase-shift attenuator. The phase shift precision of the phase shifter can be controlled within 5 degrees, but the small signal gain of the component is only 25dB, the output saturation power is only 25dBm, and the final volume size is 60x 80x 4.8mm 3. It has the disadvantages of low small signal gain, low output saturation power and large size.
In 2017, a Ku waveband 8-channel TR component was developed by the fifty-fifth research institute of the electronic technology group corporation of China. The maximum output power of the module transmitting circuit is only 34.5dBm, the receiving gain is only 19dB, and the noise coefficient is 3.5 dB. The module dimensions were 60mm by 80mm by 4.8 mm. It has the disadvantages of low maximum output power and receiving gain of the transmitting circuit, large noise coefficient and large volume.
Disclosure of Invention
The invention aims to provide a design method of a transmitting and receiving TR component based on low temperature co-fired ceramic LTCC (Low temperature Co-fired ceramic), so as to improve the receiving gain and the maximum output power of a transmitting circuit of the TR component, reduce the noise coefficient and volume of the TR component and realize a digital-analog integrated structure.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
1. a method for designing a transmitting-receiving TR component based on a low temperature co-fired ceramic (LTCC), wherein the transmitting-receiving TR component comprises a transmitting link and a receiving link, and is characterized by comprising the following steps:
(1) inputting different voltages to each level of devices of the link to obtain different output voltages;
(2) gain G of each device is obtained according to input and output voltage of each stageiAnd calculating the link gain G according to the gain of each device:
G＝G1+G2+…+Gi+…+Gn，
wherein G isiIs the gain of the ith device of the link, i is from 1 to n, and n is the total number of devices of the link;
(3) calculating the noise factor F of each device according to the input and output signal-to-noise ratios of each deviceiAnd calculating the noise factor F of the link according to the gain Gi and the noise factor Fi of each device:
Figure BDA0002628512830000021
wherein FiIs the noise factor of the ith stage device of the link;
Figure BDA0002628512830000022
representing i device gain multiplications;
(4) according to the parameter thermodynamic temperature T0Bandwidth B of the TR componentnLowest signal-to-noise (S) of the TR-component0/N0)minBoltzmann constant k, noise coefficient NF 10lgF, sensitivity S of TR module is calculated:
S＝kT0BnNF(S0/N0)min；
(5) selecting a wave control chip and a serial-parallel conversion chip according to the link gain G, the noise factor F and the sensitivity S;
(6) the method comprises the following steps of selecting a 15-layer ceramic material substrate, and dividing the whole TR component into a microwave circuit, a digital circuit and a power circuit on the 15-layer ceramic material substrate, wherein:
the first layer is a surface microstrip line circuit layer, the second layer to the fourth layer are a radio frequency circuit and element placing layer, the fifth layer is a middle microwave large-area grounding layer, the sixth layer and the seventh layer are receiving channel power supply wiring layers, the eighth layer and the ninth layer are transmitting channel power supply wiring layers, the tenth layer is an insulating layer,
the eleventh layer, the twelfth layer and the thirteenth layer are digital circuit wiring layers of the wave control chip, the fourteenth layer is a serial-parallel conversion chip digital circuit wiring layer, and the fifteenth layer is an insulating layer;
(7) drawing a TR component circuit layout corresponding to each layer of substrate on each layer of substrate according to the layering result, and simulating by using Advanced Design System (ADS);
(8) importing the layout generated in the step (7) into three-dimensional high-frequency electromagnetic field simulation software HFSS, generating a 3D layout according to the stacking relation of 15 layers of substrates, setting a wave port, a lumped port and an impedance boundary, and repeatedly adjusting the layout according to a simulation result to enable the simulation result of the advanced design system software ADS to be consistent with the simulation result of the three-dimensional high-frequency electromagnetic field simulation software HFSS, so as to obtain the final 3D layout size of the TR component;
(9) determining the size of a cavity for packaging the TR component according to the 3D layout size of the TR component, the error rate and the process requirement in substrate processing and the requirement that a fillet is required to be manufactured at the joint of the inner wall of the cavity and the substrate;
(10) determining the resonant wavelength lambda of the cavity according to the cavity size of the TR component0：
Figure BDA0002628512830000031
Wherein a, b and c are respectively the length, width and height of the inner wall of the cavity of the TR component, and m, n and p are respectively the number of half-standing waves distributed in the directions a, b and c of the electromagnetic field;
(11) establishing a cavity model of a TR component in three-dimensional high-frequency electromagnetic field simulation software HFSS according to a resonance wavelength lambda0And simulating the cavity model of the TR component to obtain the lowest resonant frequency of the cavity of the TR component, and ensuring that the resonant frequency of the cavity is higher than and far away from the working frequency of the TR component, so that the TR component can normally work.
Compared with the prior art, the invention has the following advantages:
1) in the invention, the TR component is divided into 15 layers, and a chip with the function of optimizing the TR component is selected according to the calculation of the link gain G, the noise factor F and the sensitivity S, so that the noise coefficient of the TR component is reduced, and the maximum output power and the receiving gain of a transmitting path of the TR component are improved;
2) the invention reduces the volume of the whole TR component by selecting the small-volume wave control chip, the series-parallel conversion chip and the 15 layers of base plates for stacking;
3) the invention ensures the reliability of data by using the simulation result of advanced design system software ADS and the HFSS to jointly simulate.
Drawings
FIG. 1 is a flow chart of an implementation of the present invention;
fig. 2 is a structure diagram of a 15-layer stacked LTCC substrate according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Of course, the described embodiments are only some, and not all, of the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the implementation steps of this example are as follows:
step 1, calculating a link gain G, a noise factor F and a sensitivity S, and selecting a chip according to G, F and S.
The TR module includes a transmit chain and a receive chain, wherein:
the transmitting chain is formed by sequentially connecting a single-pole three-throw switch at the input end, a first-stage power amplifier, a digital phase shifter, a directional coupler, a second-stage power amplifier, a digital attenuator, a final-stage power amplifier and a single-pole two-throw switch at a near antenna end;
the receiving link is formed by sequentially connecting a single-pole double-throw switch close to the input end of the antenna, an amplitude limiter, a first-stage low-noise amplifier, a digital phase shifter, a second-stage low-noise amplifier, a digital attenuator, a final-stage low-noise amplifier and a single-pole double-throw switch at the far end of the antenna.
1.1) calculating the link gain G of a transmitting link and a receiving link:
inputting different voltages to each stage of devices of the link to obtain different output voltages, and calculating the gain G of each device according to the input and output voltages of each stageiAnd calculating the link gain G according to the gain of each device:
G＝G1+G2+…+Gi+…+Gn，
wherein G isiIs the gain of the ith device of the link, i is from 1 to n, and n is the total number of devices of the link;
in the transmitting chain of the embodiment, the single-pole three-throw switch G at the input end1Is-3 dB, the first stage power amplifier G224dB, digital phase shifter G3Is-9.5 dB, directional coupler G4Is-0.5 dB, and the second stage power amplifier G5Is 18dB, digital attenuator G6At-2.6 dB, the final power amplifier G720dB, single pole double throw switch G8Is-0.8 dB, and the gain G of the transmitting link is 45.6 dB;
in the receiving chain of this example, the single-pole double-throw switch G is close to the input end of the antenna1Is-0.8 dB, limiter G2Is-0.6 dB, the first stage low noise amplifier G327dB, digital phase shifter G4Is-9.5 dB, and is a second stage low noise amplifierG521dB, digital attenuator G6Is-4 dB, and the final stage is a low noise amplifier G717dB, single-pole double-throw switch G at far end of antenna8Is-3 dB, the gain G of the receiving link is 47.1 dB;
1.2) calculating the noise factor F of the receiving chain:
calculating the noise factor F of each device according to the input and output signal-to-noise ratios of each deviceiAnd calculating the noise factor F of the link according to the gain Gi and the noise factor Fi of each device:
Figure BDA0002628512830000051
wherein FiIs the noise factor of the ith stage device of the link;
Figure BDA0002628512830000052
representing i device gain multiplications;
this noise factor is mainly determined by the noise factors of the previous stages of the receiving link:
if the gain of the first-stage amplifier is more than or equal to 20dB, the noise factor is equal to the noise factor before the first-stage amplifier, and the noise factor after the noise factor is ignored;
if the gain of the first-stage amplifier is less than 20dB, the noise factor is determined by the noise factors of all devices in the receiving link;
in the receiving chain of this example, the first stage amplifier gain G327dB, the noise factor of the link is equal to that before the first stage amplifier, and the noise factor NF is 10lgF and is 2.1 dB;
1.3) calculating the sensitivity S of the receiving link:
bandwidth B of TR module according to parameter thermodynamic temperature T0 ═ 290KnMinimum signal-to-noise ratio (S) of TR module at 500MHz0/N0)minBoltzmann constant k 1.38 x 10-23J/K, and noise figure NF, calculate the sensitivity of the TR module S:
S＝kT0BnNF(S0/N0)min，
the lowest signal-to-noise ratio for the TR module in this example is: (S)0/N0)min-20dB, noise figure is: NF is 2.1dB, and the sensitivity S of the receiving link is calculated to be-84 dB;
1.4) selecting chips:
and selecting devices in the link according to the calculation of the link gain G, the noise factor F and the sensitivity S.
In this example according to the device gain GiA digitally controlled attenuator NC1397C-618PD with a gain of-2.6 dB in the transmit chain and a gain of-4 dB in the receive chain is selected, and a digitally controlled phase shifter NC1278C-618PD with a gain of-9.5 dB in the transmit receive chain is selected. Since the phase shifters and the attenuators in the link are controlled by the wave control chip and the serial-to-parallel conversion chip respectively, the small-sized wave control chip NC20415 and the serial-to-parallel conversion chip NC2016-1C matched with the numerical control attenuators NC1397C-618PD and the numerical control phase shifters NC1278C-618PD can be selected according to the selected numerical control attenuators NC1397C-618PD, the numerical control phase shifters NC1278C-618PD and the sizes of the chips.
And 2, selecting a substrate material and dividing the TR component circuit.
2.1) selecting a substrate material:
the substrate material is selected according to the tangent loss angle value tan of the substrate material, the relative dielectric constant and the thickness of each layer of ceramic material after low-temperature sintering.
In this example, a Ferro-A6M type ceramic material having a tangent loss angle tan of 0.0015, a relative dielectric constant of 5.9 and a thickness of 0.1mm per layer after low-temperature sintering was selected.
2.2) dividing TR component circuits:
2.2.1) according to the functions of transmitting and receiving signals of the TR components, the control of the TR components from the outside and the power supply requirements of the TR components, dividing the whole TR component into three types of circuits including a microwave circuit, a digital circuit and a power circuit on a low-temperature co-fired ceramic LTCC substrate with 15 layers, wherein the first layer to the fifth layer are microwave circuit layers, the sixth layer to the ninth layer are power circuit layers, and the eleventh layer to the fourteenth layer are digital circuit layers;
2.2.2) finely divide three circuit layers:
referring to fig. 2, the specific implementation of this step is as follows:
the microwave circuit of the first layer is used as a device connecting line layer and connected by a microstrip line;
taking microwave circuits from a second layer to a fourth layer as a link device placing layer, and dividing a receiving link and a transmitting link;
the microwave circuit of the fifth layer is used as a large-area metal grounding layer;
taking the power supply circuits of the sixth layer and the seventh layer as receiving link power supply wiring layers;
taking the power supply circuits of the eighth layer and the ninth layer as transmission link power supply wiring layers;
taking the tenth layer as an insulating layer;
taking the digital circuits of the eleventh layer to the thirteenth layer as wiring layers of the wave control chip;
taking the digital circuit of the fourteenth layer as a wiring layer of the serial-parallel conversion chip;
the fifteenth layer is used as an insulating layer.
And 3, drawing a TR component circuit layout on the substrate, simulating the circuit layout, extracting S parameters of the circuit layout, and adjusting the circuit board diagram.
3.1) drawing a TR assembly circuit layout on a substrate:
according to the layering result of the step 2, a TR component circuit layout corresponding to each layer of substrate is drawn on each layer of substrate, and in the design of the TR component circuit layout, in order to improve the transmission performance of a radio frequency line and reduce insertion loss, radio frequency grounding is added on two sides of a high-frequency microstrip circuit; in order to ensure that the output channel does not generate self-excitation, the distance between the driving stage power amplifier and the final stage power amplifier is adjusted;
3.2) generating a principle primitive device for the microwave part layout in the advanced design system software ADS, adding the existing device parameter SNP file, simulating, and extracting the S parameter of the circuit layout;
3.3) carrying out joint simulation on the S parameter and the chip S2P parameter model:
in the embodiment, joint simulation is performed on an S parameter obtained in a circuit simulation environment of advanced design system software ADS and a chip S2P parameter model provided by the Chinese electronic technology group thirteen, and the circuit layout is adjusted according to a simulation result.
And 4, simulating the 3D layout of the TR component in the three-dimensional high-frequency electromagnetic field simulation software HFSS to obtain the size of the 3D layout.
4.1) generating a 3D layout of a TR component in three-dimensional high-frequency electromagnetic field simulation software HFSS:
and (3) introducing the layout generated in the step (3) into three-dimensional high-frequency electromagnetic field simulation software HFSS, designing vertical interconnection through holes with copper filled conductors on a 15-layer substrate according to the heat dissipation of the substrate, the power supply of the TR component and the internal circuit relation of the TR component, and connecting the vertical interconnection through holes to form a whole, wherein the whole is the 3D layout of the TR component.
4.2) simulating a 3D layout in three-dimensional high-frequency electromagnetic field simulation software HFSS to obtain the size of the 3D layout:
in the three-dimensional high-frequency electromagnetic field simulation software HFSS, a wave port, a lumped port and an impedance boundary are arranged on the 3D layout for simulation, and the layout is repeatedly adjusted according to a simulation result, so that the simulation result of the three-dimensional high-frequency electromagnetic field simulation software HFSS is consistent with the simulation result of the advanced design system software ADS, and the final 3D layout size of the TR component is obtained.
And 5, determining the size of the cavity of the packaging TR component.
Calculating the length a, the width b and the height c of the packaging cavity:
a＝v1+v1*w+(3φ/4)*(1+u),
b＝v2+v2*w+(3φ/4)*(1+u),
c＝v3+v3*w+(3φ/4)*(1+u),
wherein v1, v2 and v3 are the length, width and height of the 3D layout, w is a process error, phi is a fillet diameter, and u is an error in fillet processing.
And 6, simulating a cavity for packaging the TR component.
6.1) determining the resonant wavelength lambda of the cavity according to the cavity size of the package TR component0：
Figure BDA0002628512830000081
Wherein λ0Is the wavelength; m, n and p are the number of half standing waves distributed in the directions a, b and c of the electromagnetic field respectively;
6.2) simulating a cavity in three-dimensional high-frequency electromagnetic field simulation software HFSS:
establishing a cavity model of a TR component in three-dimensional high-frequency electromagnetic field simulation software HFSS, placing an isolation grounding metal column at a sensitive position of a cavity in order to change the resonant frequency of the cavity and reduce the field intensity in the cavity, manufacturing the cavity by adopting a good conductor, ensuring that the wall thickness of the cavity does not influence the resonant frequency in the cavity, only simulating the cavity during simulation, and simulating according to the resonant wavelength lambda0And simulating the cavity model of the TR component to obtain the lowest resonant frequency of the cavity of the TR component, and ensuring that the resonant frequency of the cavity is higher than and far away from the working frequency of the TR component, so that the TR component can normally work.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can substitute or change the technical solution of the present invention and the inventive concept within the technical scope of the present invention.

Claims (8)

1. A method for designing a transmitting-receiving TR component based on a low temperature co-fired ceramic (LTCC), wherein the transmitting-receiving TR component comprises a transmitting link and a receiving link, and is characterized by comprising the following steps:
(1) inputting different voltages to each level of devices of the link to obtain different output voltages;
(2) gain G of each device is obtained according to input and output voltage of each stageiAnd calculating the link gain G according to the gain of each device:
G＝G1+G2+…+Gi+…+Gn，
wherein G isiIs the gain of the ith device of the link, i is from 1 to n, and n is the total number of devices of the link;
(3) calculating the noise factor F of each device according to the input and output signal-to-noise ratios of each deviceiAnd calculating the noise factor F of the link according to the gain Gi and the noise factor Fi of each device:
Figure FDA0002628512820000011
wherein FiIs the noise factor of the ith stage device of the link;
Figure FDA0002628512820000012
representing i device gain multiplications;
(4) according to the parameter thermodynamic temperature T0Bandwidth B of the TR componentnLowest signal-to-noise (S) of the TR-component0/N0)minBoltzmann constant k, noise coefficient NF 10lgF, sensitivity S of TR module is calculated:
S＝kT0BnNF(S0/N0)min；
(5) selecting a wave control chip and a serial-parallel conversion chip according to the link gain G, the noise factor F and the sensitivity S;
(6) the method comprises the following steps of selecting a 15-layer ceramic material substrate, and dividing the whole TR component into a microwave circuit, a digital circuit and a power circuit on the 15-layer ceramic material substrate, wherein:
the first layer is a surface microstrip line circuit layer, the second layer to the fourth layer are a radio frequency circuit and a component placing layer,
the fifth layer is an intermediate microwave large-area grounding layer, the sixth layer and the seventh layer are receiving channel power supply wiring layers,
the eighth layer and the ninth layer are transmission channel power supply wiring layers, the tenth layer is an insulating layer,
the eleventh layer, the twelfth layer and the thirteenth layer are digital circuit wiring layers of the wave control chip,
the fourteenth layer is a serial-parallel conversion chip digital circuit wiring layer, and the fifteenth layer is an insulating layer;
(7) drawing a TR component circuit layout corresponding to each layer of substrate on each layer of substrate according to the layering result, and simulating by using Advanced Design System (ADS);
(8) importing the layout generated in the step (7) into three-dimensional high-frequency electromagnetic field simulation software HFSS, generating a 3D layout according to the stacking relation of 15 layers of substrates, setting a wave port, a lumped port and an impedance boundary, and repeatedly adjusting the layout according to a simulation result to enable the simulation result of the advanced design system software ADS to be consistent with the simulation result of the three-dimensional high-frequency electromagnetic field simulation software HFSS, so as to obtain the final 3D layout size of the TR component;
(9) determining the size of a cavity for packaging the TR component according to the 3D layout size of the TR component, the error rate and the process requirement in substrate processing and the requirement that a fillet is required to be manufactured at the joint of the inner wall of the cavity and the substrate;
(10) determining the resonant wavelength lambda of the cavity according to the cavity size of the TR component0：
Figure FDA0002628512820000021
Wherein a, b and c are respectively the length, width and height of the inner wall of the cavity of the TR component, and m, n and p are respectively the number of half-standing waves distributed in the directions a, b and c of the electromagnetic field;
(11) establishing a cavity model of a TR component in three-dimensional high-frequency electromagnetic field simulation software HFSS according to a resonance wavelength lambda0And simulating the cavity model of the TR component to obtain the lowest resonant frequency of the cavity of the TR component, and ensuring that the resonant frequency of the cavity is higher than and far away from the working frequency of the TR component, so that the TR component can normally work.
2. The method of claim 1, wherein the noise factor F of each device in (3) is determinediThe formula is as follows:
Figure FDA0002628512820000022
wherein Sin and Sout are input and output signal power of the device respectively, and Nin and Nout are input and output noise power of the device respectively.
3. The method of claim 1, wherein the selected wave control chip in (5) is a NC20415C wave control chip with an operating frequency of 10MHz and containing 24-bit serial-to-parallel conversion.
4. The method of claim 1, wherein the serial-to-parallel conversion chip selected in (5) is an NC2016-1C serial-to-parallel conversion chip having an operating frequency of 30MHz and input and output with the same phase.
5. The method according to claim 1, wherein the ceramic material selected in (6) is Ferro-A6M type ceramic material with a tangent loss tan of 0.0015, a relative dielectric constant of 5.9, and a thickness of 0.1mm per layer of ceramic material after low temperature sintering.
6. The method of claim 1, wherein the stacking of the 15-layer substrates in (8) is performed by designing vertical interconnection vias filled with copper as a conductor in each layer of the substrates, and connecting the vertical interconnection vias in the substrates in a stacked relationship to make them integral.
7. The method according to claim 1, wherein the error rate at the time of processing the substrate in (9) is 0.5% at the maximum.
8. The method of claim 1, wherein the requirement of forming a fillet at the junction of the inner wall of the chamber and the substrate in (9) means that the process error rate is 2.5% for a fillet diameter of φ.
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