CN111918007A - CMOS image sensor, pixel unit and control method thereof - Google Patents
CMOS image sensor, pixel unit and control method thereof Download PDFInfo
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Abstract
The embodiment of the invention provides a CMOS image sensor, a pixel unit and a control method thereof, wherein the pixel unit comprises a first global exposure structure suitable for outputting a first frame of analog signals and a second global exposure structure suitable for outputting a second frame of analog signals, and the second global exposure structure comprises a second photoelectric conversion element, a second transmission transistor, a second reset transistor, a third storage node, a third-level source follower, a second isolation transistor, a fourth storage node, a fourth-level source follower and a second row selection transistor; the second-stage source follower and the fourth-stage source follower are the same source follower, the first row selection transistor and the second row selection transistor are the same row selection transistor, and one of the first photoelectric conversion element and the second photoelectric conversion element has a larger light sensing area than the other photoelectric conversion element. The technical scheme of the embodiment of the invention expands the dynamic range of the pixel unit.
Description
Technical Field
The invention relates to the technical field of sensors, in particular to a CMOS image sensor, a pixel unit and a control method thereof.
Background
An image sensor is a semiconductor device that converts an optical signal into an electrical signal. Image sensors are classified into two major categories, Complementary Metal Oxide Semiconductor (CMOS) image sensors and Charge Coupled Device (CCD) image sensors. Since the CMOS image sensor has advantages of low power consumption, low cost, and easy integration of other devices, it has been widely used in still digital cameras, digital video cameras, medical imaging devices, vehicle imaging devices, and the like.
The dynamic range of an image sensor is an important index parameter of the image sensor. The dynamic range represents the range of the maximum intensity signal and the minimum intensity signal that the image sensor can detect in the same image at the same time. Generally expressed in dB, the formula is as follows:
wherein P ismaxIndicating the maximum detectable light intensity, PminIndicating a minimum intensity of light that can be detected. The dynamic range of a general image sensor is between 60-70dB, the dynamic range of human eyes is between 100-120dB, and a high dynamic range image sensor is very important for considering both dark details and bright details.
The Full Well Capacity (FWC) of an image sensor refers to the maximum number of electrons that a pixel can collect and hold. For a typical linear response image sensor, the maximum detectable intensity corresponds to the full well capacity and the minimum intensity corresponds to the number of image noise electrons, so the dynamic range can also be expressed in terms of the full well capacity/noise electrons. Generally, the larger the full well of the image sensor, the higher the dynamic range.
The pixel unit of the CMOS image sensor generally includes one photodiode and a plurality of transistors, and the global exposure structure of the pixel unit of the CMOS image sensor includes a 5-transistor (5T) type, an 8-transistor (8T) type, a 9-transistor (9T) type, and the like, according to the number of transistors included in the pixel unit of the CMOS image sensor.
As shown in fig. 1, a pixel unit of a 5T-type global exposure CMOS image sensor includes an Anti-Blooming transistor (Anti-Blooming), a transfer transistor TX, a reset transistor RST, a source follower transistor sf (source follower), a row selection transistor SEL, and 5 transistors in total, and further includes a photodiode ppd (pinned photodiode), and a storage node FD.
There are technical drawbacks to a pixel cell that includes a 5T global exposure structure. For example, the parasitic light sensation effect is large. The pixel unit of the 5T global exposure structure uses an FD point as a signal temporary storage node, the node is usually a PN junction, and metal is covered on the node to reduce parasitic light sensation effect. The node is close to PPD, if the area covered by metal is too large, the node can cover normal photosensitive PPD, so that the photosensitive effect of PPD is influenced; the pixel unit of the 5T global exposure structure reads the reset analog signal firstly and then reads the exposure analog signal, and the two times of sampling are not related sampling, so that the related double sampling cannot be realized, so that the reset noise cannot be eliminated by subtracting, and the noise of an output image is very large.
In order to overcome the technical drawbacks described above, the prior art provides a global exposure structure including two stages of source followers (i.e., a first stage source follower and a second stage source follower), the global exposure structure further including a photoelectric conversion element, a transfer transistor, a reset transistor, a storage node FD, a first capacitor, and a second capacitor. The global exposure structure can realize correlated double sampling, namely after the pixel unit is exposed, the reset level of the storage node FD is read out firstly, then the sampling level of the storage node FD is read out, after quantization, the reset quantized data and the sampling quantized data are subtracted, and reset noise generated by two times of sampling is correlated, so that the reset noise can be eliminated.
The global exposure structure having the two-stage source follower includes an 8T type global exposure structure (which has 8 transistors), a 9T type global exposure structure (which has 9 transistors), and the like.
As shown in fig. 2, the pixel unit of the 9T-type global exposure structure is composed of 9 transistors, including a transmission transistor TX, a reset transistor RST, a first-stage source follower transistor SF1, a second-stage source follower transistor SF2, an isolation transistor AMS, a discharge transistor Bias, switching transistors SWR and SWS, and a row selection transistor SEL, and further includes a photodiode PPD and two sampling capacitors Cr and Cs.
However, the pixel cells of the existing global exposure architecture do not have a high dynamic range.
Disclosure of Invention
The invention solves the technical problem of how to improve the dynamic range of the pixel unit of the global exposure structure. To solve the foregoing technical problem, an embodiment of the present invention provides a pixel unit of a CMOS image sensor, including a first global exposure structure adapted to output an analog signal of a first frame, including a first photoelectric conversion element, a first transmission transistor, a first reset transistor, a first storage node, a first stage source follower, a first isolation transistor, a second storage node, a second stage source follower, and a first row selection transistor, the pixel unit further including: a second global exposure structure adapted to be coupled to the first global exposure structure to output a second frame of analog signals, and including a first control transistor SW, a second photoelectric conversion element, a second transmission transistor, a second reset transistor, a third storage node, a third stage source follower, a second isolation transistor, a fourth storage node, a fourth stage source follower, a second row selection transistor, and a first control transistor, wherein a first terminal of the first control transistor is connected to the fourth storage node, and a second terminal of the first control transistor is connected to a gate of the fourth stage source follower; the second-stage source follower and the fourth-stage source follower are the same source follower, the first row selection transistor and the second row selection transistor are the same row selection transistor, and one of the first photoelectric conversion element and the second photoelectric conversion element has a larger light sensing area than the other photoelectric conversion element.
Optionally, one of the light sensing areas of the first photoelectric conversion element and the second photoelectric conversion element, which is larger than the light sensing area, is N times larger than one of the light sensing areas, which is smaller than the light sensing area, and N is an integer greater than or equal to 8.
Optionally, a control module is included, which is adapted to control the first control transistor to be turned on or off to control the first global exposure structure to output the first frame analog signal and the second global exposure structure to output the second frame analog signal.
Optionally, the first global exposure structure is a 9T-type global exposure structure, which further includes: the first photoelectric conversion element comprises a first control transistor, a third control transistor, a fourth control transistor, a first capacitor and a second capacitor, wherein the anode end of the first photoelectric conversion element is coupled with a first power line, and the cathode end of the first photoelectric conversion element is coupled with the first end of the first transmission transistor; the second end of the first transmission transistor is coupled with the second end of the first reset transistor; the first end of the first reset transistor is coupled with a second power line; the grid of the first stage source electrode follower is coupled with the first storage node, the first end is coupled with the second power line, and the second end is coupled with the first end of the first isolation transistor; the second end of the first isolation transistor is coupled with the second storage node; the second ends of the first capacitor and the second capacitor are coupled with a first power line; first ends of the second control transistor, the third control transistor and the fourth control transistor are coupled to a second storage node; the second end of the second control transistor is coupled with the first end of the first capacitor; the second end of the third control transistor is coupled to the first end of the second capacitor; the second end of the fourth control transistor is coupled with the first power line; the grid electrode of the second stage source electrode follower is coupled with the second storage node, and the first end of the second stage source electrode follower is coupled with the second power line; the second power line is a power line for providing working voltage for the pixel unit; the first end of the first row selection transistor is coupled to the second end of the second stage source follower, and the second end is coupled to the bit line of the pixel unit.
Optionally, the second global exposure structure is a 9T-type global exposure structure, which further includes: the anode end of the second photoelectric conversion element is coupled with the first power line, the cathode end of the second photoelectric conversion element is coupled with the first end of the second transmission transistor, the second end of the second transmission transistor is coupled with the second end of the second reset transistor, and the first end of the second reset transistor is coupled with the second power line; the grid electrode of the third-stage source electrode follower is coupled with the third storage node, the first end of the third-stage source electrode follower is coupled with the second power line, the second end of the third-stage source electrode follower is coupled with the first end of the second isolation transistor, and the second end of the second isolation transistor is coupled with the fourth storage node; second ends of the third capacitor and the fourth capacitor are coupled with a first power line, and first ends of the fifth control transistor, the sixth control transistor and the seventh control transistor are coupled with a fourth storage node; the second end of the fifth control transistor is coupled with the first end of the third capacitor; the second end of the sixth control transistor is coupled with the first end of the fourth capacitor; the second end of the seventh control transistor is coupled to the first power line; the first end of the second row selection transistor is coupled to the second end of the fourth-stage source follower, and the second end of the second row selection transistor is coupled to the bit line of the pixel unit.
Optionally, the pixel unit further comprises a quantization structure adapted to receive the first frame analog signal, quantize the first frame analog signal and obtain first frame quantized data based on the quantized first frame analog signal, receive the second frame analog signal, quantize the second frame analog signal and obtain second frame quantized data based on the quantized second frame analog signal, and add the first frame quantized data and the second frame quantized data to obtain final quantized data.
Optionally, the first frame analog signal includes a first frame reset analog signal and a first frame exposure analog signal, the second frame analog signal includes a second frame reset analog signal and a second frame exposure analog signal, and the quantization structure includes: a first quantization sub-module adapted to quantize the first frame reset analog signal to obtain first frame reset quantized data, quantize the first frame exposure analog signal to obtain first frame exposure quantized data, subtract the first frame reset quantized data and the first frame exposure quantized data to obtain first frame quantized data; a second quantization sub-module adapted to quantize the second frame reset analog signal to obtain second frame reset quantized data, quantize the second frame exposure analog signal to obtain second frame exposure quantized data, subtract the second frame reset quantized data and the second frame exposure quantized data to obtain second frame quantized data; a processing sub-module adapted to add the first frame quantized data and the second frame quantized data to obtain final quantized data.
The embodiment of the invention also provides a method for controlling the pixel unit, which comprises the following steps: setting a gate control signal of the first control transistor to a low level; setting gate control signals of the first reset transistor, the second reset transistor, the first transfer transistor, and the second transfer transistor to a high level to reset the first photoelectric conversion element and the second photoelectric conversion element; after gate control signals of the first reset transistor, the second reset transistor, the first transmission transistor and the second transmission transistor are set to be low level, the pixel unit starts to be exposed; after exposure is finished, setting the grid control signals of the first isolation transistor and the second isolation transistor to be high level, and setting the grid control signals of the fourth control transistor and the seventh control transistor to be high level; setting gate control signals of the first reset transistor and the second reset transistor to a high level to empty the first storage node and the third storage node; setting the gate control signals of the first reset transistor and the second reset transistor to be at a low level, and setting the gate control signals of the second control transistor and the fifth control transistor to be at a high level so as to charge the first capacitor and the third capacitor; setting gate control signals of the second control transistor and the fifth control transistor to a low level to store a reset analog signal of a first frame on the first capacitor and store a reset analog signal of a second frame on the third capacitor; setting gate control signals of the first transfer transistor and the second transfer transistor to a high level, transferring charges collected during exposure from the first photoelectric conversion element and the second photoelectric conversion element to the first storage node and the third storage node, respectively, and setting the gate control signals of the first transfer transistor and the second transfer transistor to a low level after the transfer is completed; and setting the grid control signals of the third control transistor and the sixth control transistor to be at a high level so as to charge the second capacitor and the fourth capacitor, and setting the grid control signals of the third control transistor and the sixth control transistor to be at a low level after the signals are established so as to store the exposure analog signals of the first frame on the second capacitor and store the exposure analog signals of the second frame on the fourth capacitor.
Optionally, setting gate control signals of the first isolation transistor, the second isolation transistor, the fourth control transistor and the seventh control transistor to be low level, and starting to enter a line-by-line reading stage; setting a gate control signal of a first row selection transistor to be at a high level, setting a gate control signal of a first control transistor to be at a low level, setting a gate control signal of a fourth control transistor to be at a high level, then setting the gate control signal to be at a low level again to clear a second storage node, then setting a gate control signal of a second control transistor to be at a high level, and transmitting a reset analog signal of a first frame of a first capacitor to a bit line by a second-stage source follower to sample the reset analog signal of the first frame, and then setting the gate control signal of the second control transistor to be at a low level; setting a gate control signal of the fourth control transistor to a high level and then to a low level again to clear the second storage node, then setting a gate control signal of the third control transistor to a high level, and the second stage source follower transmits an exposure analog signal of a first frame of the second capacitance to the bit line to sample the exposure analog signal of the first frame, and then sets the gate control signal of the third control transistor to a low level; setting a gate control signal of the first control transistor to a high level, setting a gate control signal of the seventh control transistor to a high level, then setting the gate control signal to a low level to clear the fourth storage node, then setting a gate control signal of the fifth control transistor to a high level, the second stage source follower passing a reset analog signal of a second frame of the third capacitance to the bit line to sample the reset analog signal of the second frame, then setting the gate control signal of the fifth control transistor to a low level; the gate control signal of the seventh control transistor is set to a high level and then set to a low level again to clear the fourth storage node, the gate control signal of the sixth control transistor is set to a high level, the second stage source follower passes the exposure analog signal of the second frame of the fourth capacitance to the bit line to sample the exposure analog signal of the second frame, and then the gate control signal of the sixth control transistor is set to a low level.
Alternatively, the first frame reset quantized data is obtained by quantizing the first frame reset analog signal, the first frame exposure quantized data is obtained by quantizing the first frame exposure analog signal, and the first frame exposure quantized data is obtained by subtracting the first frame reset quantized data and the first frame exposure quantized data; quantizing the second frame reset analog signal to obtain second frame reset quantized data, quantizing the second frame exposure analog signal to obtain second frame exposure quantized data, and subtracting the second frame reset quantized data from the second frame exposure quantized data to obtain second frame quantized data; the first frame quantized data and the second frame quantized data are added to obtain final quantized data.
The embodiment of the invention also provides a CMOS image sensor which comprises a row selection circuit, a column selection circuit and a pixel array, wherein the pixel array comprises a plurality of pixel units which are arranged in an array, and the pixel unit is any one of the pixel units.
Compared with the prior art, the technical scheme of the embodiment of the invention adds the second global exposure structure in the first global exposure structure of the existing two-stage source follower, and improves the dynamic range of the pixel unit of the image sensor.
Drawings
FIG. 1 is a schematic structural diagram of a pixel unit with a 5T-type global exposure structure in the prior art;
FIG. 2 is a schematic structural diagram of a pixel unit with a 9T-type global exposure structure in the prior art;
fig. 3 is a schematic structural diagram of a pixel unit of a CMOS image sensor according to an embodiment of the invention;
FIG. 4 is a schematic structural diagram of a pixel unit of a CMOS image sensor according to another embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a pixel unit having a 9T-type global exposure structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a method for controlling the pixel unit shown in FIG. 5 according to an embodiment of the present invention;
FIG. 7 is a timing diagram illustrating global operation and row-by-row readout of the pixel cells of FIG. 5 according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a CMOS image sensor according to an embodiment of the present invention.
Detailed Description
In an image sensor including an existing Global exposure structure, a dynamic range of a pixel unit is small, a high dynamic range is not provided, and the requirement of high dynamic range application under Global exposure (Global Shutter) cannot be met.
According to different exposure modes, existing CMOS sensors can be classified into line-by-line exposure CMOS sensors and global exposure CMOS sensors. Global exposure refers to all pixels in a frame of image, and exposure starts at one time and ends at another time. The global exposure can eliminate the defect of motion blur of line-by-line exposure because the starting point and the ending point of each line of exposure time are the same, and clear image output is realized. Both 5T and 9T belong to globally exposed CMOS sensors.
Pixel unit of existing global exposure structure
V＝Q/C (2)
Wherein V, Q and C are voltage, charge and capacitance parameters, respectively.
From the above formula, it can be known that, in the case of a constant charge amount, the smaller the capacitance, the larger the voltage fluctuation, that is, the higher the sensitivity. Therefore, in order to improve the photosensitivity, FD cannot be made large, which makes the Full Well Capacity (FWC) of the pixel small, resulting in a small dynamic range of the pixel cell.
The technical scheme of the invention utilizes the existing first global exposure structure with two-stage source followers and utilizes related double sampling to subtract two signals and eliminate reset noise. A second global exposure structure is added at the same time so that the charges of the first photoelectric conversion element and the second photoelectric conversion element can be collected at the same time. The charge collected by the first photoelectric conversion element can be a high-sensitivity frame corresponding to the details of the dark image through a first frame analog signal after photoelectric conversion; the charge collected by the second photoelectric conversion element may be a low-sensitivity frame corresponding to the details of the bright portion of the image by the second frame analog signal after photoelectric conversion. Thereby achieving the purpose of expanding the dynamic range.
In an embodiment of the present invention, the global exposure structure includes 7T type, 8T type, 9T type, and the like, and the global exposure structure of this type includes a reset capacitor, a sampling capacitor, a transistor for controlling the reset capacitor, a transistor for controlling the sampling capacitor, a first source follower, and a second source follower.
In the description of the present invention, components having the same name have the same or similar functions, positional relationships, and connection relationships; signals having the same or similar labels have the same or similar functions, transmitting means and receiving means.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 3 is a schematic structural diagram of a pixel unit of a CMOS image sensor according to an embodiment of the invention. The pixel unit 10 includes a first global exposure structure 100 having a two-stage source follower, and a second global exposure structure 200.
The first global exposure structure 100 includes a transistor adapted to output a first frame analog signal, which includes a first photoelectric conversion element PPD1, a first transfer transistor TX1, a first reset transistor RST1, a first storage node FD1, a first stage source follower SF1, a first isolation transistor AMS1, a second storage node SD1, a second stage source follower SF2, a first row selection transistor SEL1, and the like.
Specifically, the first frame analog signal includes a first frame reset analog signal and a first frame exposure analog signal; after the exposure of the pixel unit 10, the first frame reset analog signal of the first storage node FD1 is read out, and the first frame exposure analog signal of the first storage node FD1 is read out, wherein the noise of the separately sampled first frame reset analog signal and first frame exposure analog signal is correlated, i.e., correlated double sampling, and the two signals are subtracted in the quantization structure 300, so that the reset noise of the first frame analog signal can be eliminated.
The second global exposure structure 200 is adapted to be coupled to the first global exposure structure 100 to output a second frame analog signal, and includes a first control transistor SW, a second photoelectric conversion element PPD2, a second transmission transistor TX2, a second reset transistor RST2, a third storage node FD2, a third stage source follower SF3, a second isolation transistor AMS2, a fourth storage node SD2, a fourth stage source follower SF4, a second row selection transistor SEL 2; a first control transistor SW having a first terminal connected to the fourth storage node SD2 and a second terminal connected to the gate of the fourth-stage source follower; wherein the second-stage source follower SF2 and the fourth-stage source follower SF4 are the same source follower, the first row selection transistor SEL1 and the second row selection transistor SEL2 are the same row selection transistor, and one of the first photoelectric conversion element PPD1 and the second photoelectric conversion element PPD2 has a larger light sensing area than the other.
Specifically, the second frame analog signal includes a second frame reset analog signal and a second frame exposure analog signal; after the pixel unit 10 is exposed, the second frame reset analog signal of the third storage node FD2 is read out, and the second frame exposure analog signal of the third storage node FD2 is read out, wherein the noise of the respectively sampled second frame reset analog signal and second frame exposure analog signal is correlated, i.e., correlated double sampling, and the two signals are subtracted in the quantization structure 300, so that the reset noise of the second frame analog signal can be eliminated.
In a specific implementation, after the pixel unit 10 is exposed to light, there are four readout operations, that is, a first frame reset analog signal (first readout operation) to read out the first storage node FD1, a first frame exposure analog signal (second readout operation) to read out the first storage node FD1, a second frame reset analog signal (third readout operation) to read out the third storage node FD2, and a second frame exposure analog signal (fourth readout operation) to read out the third storage node FD2, and the order of the four readout operations may be arbitrary.
Preferably, both the first and second sensing operations or both the third and fourth sensing operations are continuously operated to reduce the number of times the first control transistor SW is turned on; more preferably, both the first and second sensing operations are continuously operated, and both the third and fourth sensing operations are continuously operated, to further reduce the number of times the first control transistor SW is turned on.
In some embodiments, the turning on or off of the first control transistor SW is controlled by the control module. The control module may be an isp (image Signal processor) image processor. In the global operation stage, the first control transistor SW is controlled by the control module to be turned off so that the charges of the first photoelectric conversion element PPD1 and the second photoelectric conversion element PPD2 can be collected at the same time. That is, the charge collected from the first photoelectric conversion element PPD1 during exposure is stored on the first storage node FD1, and at this time, the detail of the image dark place is stored for the high-sensitivity frame corresponding to the first frame analog signal. The charge collected from PPD2 during exposure is stored on third storage node FD2, which now stores the details of the image where it is bright for the second frame analog signal, which is a low sensitivity frame, which causes the full well capacity of the pixel to be large, thereby increasing the dynamic range of pixel cell 10.
The one of the first photoelectric conversion element PPD1 having a larger light sensing area and the second photoelectric conversion element PPD2 having a larger light sensing area is N times the one having a smaller light sensing area, and N is an integer greater than or equal to 8.
In a specific implementation, the optical signal is converted into an electric charge by the photodiode, and the electric charge is stored on the first storage node FD1 or on the third storage node FD2 by the transfer transistor.
In some embodiments, when the light sensing area of the first photoelectric conversion element PPD1 is larger than that of the second photoelectric conversion element PPD2, as shown in formula (1), where P ismaxIndicating the maximum intensity detectable, corresponding to the photosensitive area, P, of the first photoelectric conversion element PPD1minIndicating the minimum intensity of light detectable, corresponds to the photosensitive area of the second photoelectric conversion element PPD 2. The increased value of the dynamic range can be represented by 20lgN, and the light sensing area of the first photoelectric conversion element PPD1 is N times the light sensing area of the second photoelectric conversion element PPD2 as shown in formula (3): .
Wherein S isPPD1Is the photosensitive area, S, of the first photoelectric conversion element PPD1PPD2Is the light sensing area of the second photoelectric conversion element PPD 2. For example, when the light sensing area of the first photoelectric conversion element PPD1 is 32 times as large as the light sensing area of the second photoelectric conversion element PPD2, the dynamic range may be improved by about 30 dB;
in some embodiments, when the light sensing area of the first photoelectric conversion element PPD1 is smaller than the light sensing area of the second photoelectric conversion element PPD2, as shown in formula (1), where P ismaxIndicating the maximum intensity of light detectable, corresponding to the photosensitive area, P, of the second photoelectric conversion element PPD2minIndicating the minimum intensity of light that can be detected,corresponding to the light sensing area of the first photoelectric conversion element PPD 1. The increased value of the dynamic range can be represented by 20lgN, and the light sensing area of the second photoelectric conversion element PPD2 is N times the light sensing area of the first photoelectric conversion element PPD1, when this is as shown in formula (4):
for example, when the light sensing area of the second photoelectric conversion element PPD2 is 100 times the light sensing area of the first photoelectric conversion element PPD1, the dynamic range may be improved by about 40 dB.
Fig. 4 is a schematic structural diagram of a pixel unit of a CMOS image sensor according to another embodiment of the present invention. The pixel unit 20 includes a first global exposure structure 100 having a two-stage source follower, a second global exposure structure 200, and a quantization structure 300.
Specifically, the pixel unit 20 may further include a quantization structure 300 adapted to receive a first frame analog signal, quantize the first frame analog signal and obtain first frame quantized data based on the quantized first frame analog signal, receive a second frame analog signal, quantize the second frame analog signal and obtain second frame quantized data based on the quantized first frame analog signal, and add the first frame quantized data and the second frame quantized data to obtain final quantized data.
Specifically, the first frame analog signal includes a first frame reset analog signal and a first frame exposure analog signal, the second frame analog signal includes a second frame reset analog signal and a second frame exposure analog signal, and the quantization structure 300 includes: a first quantization sub-module adapted to quantize the first frame reset analog signal to obtain first frame reset quantized data, quantize the first frame exposure analog signal to obtain first frame signal quantized data, subtract the first frame reset quantized data and the first frame signal quantized data to obtain first frame quantized data; a second quantization sub-module adapted to quantize the second frame reset analog signal to obtain second frame reset quantized data, quantize the second frame exposure analog signal to obtain second frame signal quantized data, subtract the second frame reset quantized data and the second frame signal quantized data to obtain second frame quantized data; a processing sub-module adapted to add the first frame quantized data and the second frame quantized data to obtain final quantized data.
In a specific implementation, the first control transistor SW is controlled by the control module to be turned on or off. The first control transistor SW may be controlled by the control module to be turned off so that the charges of the first and second photoelectric conversion elements PPD1 and PPD2 may be collected at the same time. When the first control transistor SW is turned off, the charge collected from the first photoelectric conversion element PPD1 during exposure is stored on the first storage node FD1, and a first frame analog signal may be output as a high-sensitivity frame, which may correspond to details of an image dark place.
Specifically, the first frame analog signal includes a first frame reset analog signal and a first frame exposure analog signal; after the exposure of the pixel unit 20, the first frame reset analog signal and the first frame exposure analog signal of the first storage node FD are read out, wherein the noise of the first frame reset analog signal and the first frame exposure analog signal respectively sampled is correlated, i.e., correlated double sampling, and the two signals are subtracted in the quantization structure 300, so that the reset noise of the first frame analog signal can be eliminated.
When the first control transistor SW is turned off, charges collected from PPD2 during exposure are stored in the third storage node FD2, and a second frame analog signal may be output as a low-sensitivity frame, which may correspond to details where an image is bright.
Specifically, the second frame analog signal includes a second frame reset analog signal and a second frame exposure analog signal; after the exposure of the pixel unit 20, the second frame reset analog signal and the second frame exposure analog signal of the third storage node FD2 are read out first, wherein the noise of the second frame reset analog signal and the second frame exposure analog signal respectively sampled is correlated, i.e., correlated double sampling, and the two signals are subtracted in the quantization structure 300, so that the reset noise of the second frame analog signal can be eliminated.
By quantizing the high-sensitivity frame and the low-sensitivity frame, respectively. And the quantized high-sensitivity frame and the low-sensitivity frame are fused, so that the detail information of a bright area and a dark area in the transient image is reflected in the same image, a clear image is obtained, and the dynamic range of pixels is expanded.
For example, when adding the first frame quantized data and the second frame quantized data, the image data that is not saturated in the second frame quantized data may be taken, and the image data that is saturated or oversaturated in the second frame quantized data may be replaced by the quantized data at the corresponding position in the first frame multiplied by a multiple (sensitivity ratio of the second frame to the first frame), thereby fusing the first frame quantized data and the second frame quantized data.
Fig. 5 is a schematic structural diagram of a pixel unit having a 9T-type global exposure structure according to an embodiment of the present invention. The pixel cell 30 includes a 9T type first global exposure structure 110 and a 9T type second global exposure structure 210.
The 9T-type first global exposure structure 110 includes, in addition to the first photoelectric conversion element PPD1, the first transfer transistor TX1, the first reset transistor RST1, the first storage node FD1, the first stage source follower SF1, the first isolation transistor AMS1, the second storage node SD1, and the second stage source follower SF 2: a second control transistor SWR1, a third control transistor SWS1, a fourth control transistor BIAS1, a first capacitor Cr1, and a second capacitor Cs1, wherein an anode terminal of the first photoelectric conversion element PPD1 is coupled to a first power line, and a cathode terminal thereof is coupled to a first terminal of the first transmission transistor TX 1; a second terminal of the first transmission transistor TX1 is coupled to a second terminal of the first reset transistor RST 1; a first terminal of the first reset transistor RST1 is coupled to a second power line; a gate of the first stage source follower SF1 is coupled to the first storage node FD1, a first terminal is coupled to the second power line, and a second terminal is coupled to the first terminal of the first isolation transistor AMS 1; a second terminal of the first isolation transistor AMS1 is coupled to the second storage node SD 1; second ends of the first capacitor Cr1 and the second capacitor Cs1 are coupled to a first power line; first ends of the second, third and fourth control transistors SWR1, SWS1 and BIAS1 are coupled to the second storage node SD 1; a second terminal of the second control transistor SWR1 is coupled to a first terminal of the first capacitor Cr 1; a second terminal of the third control transistor SWS1 is coupled to the first terminal of the second capacitor Cs 1; a second terminal of the fourth control transistor BIAS1 is coupled to the first power line; the gate of the second stage source follower SF2 is coupled to the second storage node SD1, and the first terminal is coupled to the second power line VDD; the second power line VDD is a power line for supplying a working voltage to the pixel unit; the first end of the first row selection transistor SEL1 is coupled to the second end of the second stage source follower SF2, and the second end is coupled to the bit line of the pixel unit.
The 9T type second global exposure structure 210 includes, in addition to the second photoelectric conversion element PPD2, the second transfer transistor TX2, the second reset transistor RST2, the third storage node FD2, the third stage source follower SF3, the second isolation transistor AMS2, the fourth storage node SD2, the fourth stage source follower SF4, the second row selection transistor SEL2, the first control transistor SW: a fifth control transistor SWR2, a sixth control transistor SWS2, a seventh control transistor BIAS2, a third capacitor Cr2, and a fourth capacitor Cs2, wherein an anode terminal of the second photoelectric conversion element PPD2 is coupled to a first power line, a cathode terminal of the second photoelectric conversion element PPD2 is coupled to a first terminal of a second transmission transistor TX2, a second terminal of the second transmission transistor TX2 is coupled to a second terminal of a second reset transistor RST2, and a first terminal of the second reset transistor RST2 is coupled to a second power line VDD; a gate of the third stage source follower SF3 is coupled to the third storage node FD2, a first terminal is coupled to the second power line VDD, a second terminal is coupled to the first terminal of the second isolation transistor AMS2, and a second terminal of the second isolation transistor AMS2 is coupled to the fourth storage node SD 2; second terminals of the third capacitor Cr2 and the fourth capacitor Cs2 are coupled to a first power line, and first terminals of the fifth control transistor SWR2, the sixth control transistor SWS2 and the seventh control transistor BIAS2 are coupled to the fourth storage node SD 2; a second terminal of the fifth control transistor SWR2 is coupled to the first terminal of the third capacitor Cr 2; a second terminal of the sixth control transistor SWS2 is coupled to the first terminal of the fourth capacitor Cs 2; the second terminal of the seventh control transistor BIAS2 is coupled to the first power line, the first terminal of the second row select transistor is coupled to the second terminal of the fourth stage source follower, and the second terminal of the second row select transistor is coupled to the bit line of the pixel cell (for a complete description of the 9T-type second global exposure structure 210, the fourth stage source follower SF4 and the second row select transistor SEL2 and their connections are described herein, it should be understood that, as described above, the second stage source follower SF2 and the fourth stage source follower SF4 are the same source follower, and the first row select transistor SEL1 and the second row select transistor SEL2 are the same row select transistor).
In the embodiment shown in the figure, all transistors of the 9T-type global exposure structure 110 are NMOS transistors, but in other embodiments, PMOS transistors may be used instead of all NMOS transistors.
Fig. 6 is a method for controlling the pixel unit 30 according to an embodiment of the present invention, which can be based on the exposure timing chart shown in fig. 7. The method 40 comprises the steps of:
step S110: setting a gate control signal of the first control transistor SW to a low level; setting the gate control signals of the first reset transistor RST1, the second reset transistor RST2, the first transmission transistor TX1, and the second transmission transistor TX2 to a high level to reset the first photoelectric conversion element PPD1 and the second photoelectric conversion element PPD 2;
step S120: after the gate control signals of the first reset transistor RST1, the second reset transistor RST2, the first transmission transistor TX1 and the second transmission transistor TX2 are set to a low level, the pixel unit 30 starts exposure;
step S130: after exposure is finished, gate control signals of the first isolation transistor AMS1 and the second isolation transistor AMS2 are set to be at a high level, and gate control signals of the fourth control transistor BIAS1 and the seventh control transistor BIAS2 are set to be at a high level;
step S140: setting the gate control signals of the first reset transistor RST1 and the second reset transistor RST2 to a high level to empty the first storage node FD1 and the third storage node FD 2;
step S150: the gate control signals of the first reset transistor RST1 and the second reset transistor RST2 are set to a low level, and the gate control signals of the second control transistor SWR1 and the fifth control transistor SWR2 are set to a high level to charge the first capacitor Cr1 and the third capacitor Cr 2; the gate control signals of the second and fifth control transistors SWR1 and SWR2 are set to a low level to store the reset analog signal of the first frame on the first capacitance Cr1 and the reset analog signal of the second frame on the third capacitance Cr 2;
step S160: setting the gate control signals of the first and second transmission transistors TX1 and TX2 to a high level, transferring charges collected during exposure from the first and second photoelectric conversion elements PPD1 and PPD2 to the first and third storage nodes FD1 and FD2, respectively, and setting the gate control signals of the first and second transmission transistors TX1 and TX2 to a low level after completion of the transfer;
step S170: the gate control signals of the third and sixth control transistors SWS1 and SWS2 are set to a high level to charge the second and fourth capacitances Cs1 and Cs2, and the gate control signals of the third and sixth control transistors SWS1 and SWS2 are set to a low level after the signals are established to store the exposure analog signal of the first frame on the second capacitance Cs1 and the exposure analog signal of the second frame on the fourth capacitance Cs 2.
In the execution of step S140, clearing the first and third storage nodes FD1 and FD2 means clearing the charges stored in the first and third storage nodes FD1 and FD 2.
In the execution of step S150, the first control transistor SW may be controlled by the control module to be turned off so that the charges of the first and second photoelectric conversion elements PPD1 and PPD2 may be collected at the same time. That is, the gate control signal of the first control transistor SW is set to a low level, the first capacitor Cr1 and the third capacitor Cr2 are charged, the reset analog signal of the first frame is stored on the first capacitor Cr1, and the reset analog signal of the second frame is stored on the third capacitor Cr 2.
In the execution of step S160, the signal charges collected during exposure are transferred from the first photoelectric conversion element and PPD1 to the first storage node FD1 and the third storage node FD2, respectively, from the second photoelectric conversion element PPD.
In the execution of step S170, the second and fourth capacitances Cs1 and Cs2 are charged, the exposure analog signal of the first frame is stored on the second capacitance Cs1, and the exposure analog signal of the second frame is stored on the fourth capacitance Cs 2.
In the above embodiments of the present invention, the second control transistor SWR1, the fifth control transistor SWR2, the third control transistor SWS1 and the sixth control transistor SWS2 are sequentially operated, so as to reduce the turn-on and turn-off times of the first control transistor SW and improve the working efficiency of the pixel unit 30.
In other embodiments of the present invention, the operation sequence of the second control transistor SWR1, the fifth control transistor SWR2, the third control transistor SWS1, and the sixth control transistor SWS2 may be arbitrarily adjusted.
Specifically, after the pixel unit 30 is exposed to light, there are four readout operations, that is, a first frame reset analog signal (first readout operation) to read out the first storage node FD1 based on the on and off of the second control transistor SWR1, a second frame reset analog signal (second readout operation) to read out the third storage node FD2 based on the on and off of the fifth control transistor SWR2, a first frame exposure analog signal (third readout operation) to read out the first storage node FD1 based on the on and off of the third control transistor SWS1, and a second frame exposure analog signal (fourth readout operation) to read out the third storage node FD2 based on the on and off of the sixth control transistor SWS 2.
The order of these four read operations may be arbitrary. Preferably, both the first and second sensing operations or both the third and fourth sensing operations are continuously operated to reduce the number of times the first control transistor SW is turned on; more preferably, both the first and second sensing operations are continuously operated, and both the third and fourth sensing operations are continuously operated, to further reduce the number of times the first control transistor SW is turned on.
The above steps S110 to S170 belong to a global operation phase, and after the global operation phase is finished, a row-by-row readout phase may be entered. Accordingly, the method of embodiments of the present invention may include the following steps S210-S250.
Step S210: setting the gate control signals of the first isolation transistor AMS1, the second isolation transistor AMS2, the fourth control transistor BIAS1 and the seventh control transistor BIAS2 to low level, starting to enter a progressive readout phase;
step S220: setting the gate control signal of the first row selection transistor SEL1 to a high level, setting the gate control signal of the first control transistor SW to a low level, setting the gate control signal of the fourth control transistor BIAS1 to a high level, and then setting it again to a low level to clear the second storage node SD1, then setting the gate control signal of the second control transistor SWR1 to a high level, the second stage source follower SF2 passing the reset analog signal of the first frame of the first capacitance Cr1 to the bit line bin to sample the reset analog signal of the first frame, as indicated at s1 in fig. 7, and then setting the gate control signal of the second control transistor SWR1 to a low level;
step S230: setting the gate control signal of the fourth control transistor BIAS1 to a high level and then to a low level to clear the second storage node SD1, then setting the gate control signal of the third control transistor SWS1 to a high level, the second stage source follower SF2 passing the first frame exposure analog signal of the second capacitor Cs1 to the bit line Bitline to sample the first frame exposure analog signal, as indicated at s2 in fig. 7, and then setting the gate control signal of the third control transistor SWS1 to a low level;
step S240: setting the gate control signal of the first control transistor SW to a high level, setting the gate control signal of the seventh control transistor BIAS2 to a high level, then to a low level to clear the fourth storage node SD2, then setting the gate control signal of the fifth control transistor SWR2 to a high level, the second stage source follower SF2 passing the reset analog signal of the second frame of the third capacitance Cr2 to the bit line Bitline to sample the reset analog signal of the second frame, as indicated at s3 in fig. 7, and then setting the gate control signal of the fifth control transistor SWR2 to a low level;
step S250: the gate control signal of the seventh control transistor BIAS2 is set to a high level and then set to a low level to clear the fourth storage node SD2, the gate control signal of the sixth control transistor SWS2 is then set to a high level, and the second stage source follower SF2 passes the second frame exposure analog signal of the fourth capacitance Cs2 to the bit line Bitline to sample the second frame exposure analog signal, as indicated at s4 in fig. 7, and then the gate control signal of the sixth control transistor SWS2 is set to a low level.
In the execution of steps S220 and S230, clearing the second storage node SD1 means clearing the charge stored in the second storage node SD 1. Reading out a first frame reset analog signal and a first frame exposure analog signal collected in an exposure period to a bit line Bitline, wherein the first frame analog signal comprises the first frame reset analog signal and the first frame exposure analog signal, and the first frame analog signal can be a high-sensitivity frame and stores details of a dark place of an image.
In the execution of steps S240 and S250, clearing the fourth storage node SD2 means clearing the charge stored in the fourth storage node SD 2. Reading out a second frame reset analog signal and a second frame exposure analog signal collected in an exposure period to a bit line Bitline, wherein the second frame analog signal comprises the second frame reset analog signal and the second frame exposure analog signal, and the second frame analog signal can be a low-sensitivity frame and stores details of a bright part of an image.
In the above embodiment of the present invention, the second control transistor SWR1, the third control transistor SWS1, the fifth control transistor SWR2, and the sixth control transistor SWS2 are operated in sequence.
It is to be understood that in other embodiments of the present invention, the operation sequence of the second control transistor SWR1, the third control transistor SWS1, the fifth control transistor SWR2 and the sixth control transistor SWS2 may be freely adjusted.
The above steps S210-S250 belong to the progressive readout phase, after which the quantization phase can be entered. Accordingly, the method of an embodiment of the present invention may include the following steps S310-S330.
Step S310: quantizing the first frame reset analog signal to obtain first frame reset quantized data, quantizing the first frame exposure analog signal to obtain first frame sample quantized data, and subtracting the first frame reset quantized data and the first frame exposure quantized data to obtain first frame quantized data;
step S320: quantizing the second frame reset analog signal to obtain second frame reset quantized data, quantizing the second frame exposure analog signal to obtain second frame exposure quantized data, and subtracting the second frame reset quantized data from the second frame exposure quantized data to obtain second frame quantized data;
step S330: the first frame quantized data and the second frame quantized data are added to obtain final quantized data.
In the execution of step S310, the first frame reset analog signal may be quantized in the quantization structure 300 to obtain first frame reset quantized data, the first frame exposure analog signal may be quantized to obtain first frame exposure quantized data, and the first frame reset quantized data and the first frame exposure quantized data may be subtracted to obtain first frame quantized data, thereby eliminating reset noise of the first frame analog signal.
In the execution of step S320, the second frame exposure analog signal may be quantized in the quantization structure 300 to obtain second frame exposure quantized data, and the second frame reset quantized data and the second frame exposure quantized data may be subtracted to obtain second frame quantized data, thereby eliminating reset noise of the second frame analog signal.
In the step S320, the quantized high-sensitivity frame (first frame analog signal) and the low-sensitivity frame (second frame analog signal) may be fused, and the details of the bright area and the area in the transient image are reflected in the same image by an image fusion method, so as to obtain a clear image and expand the dynamic range of the pixels.
For example, when adding the first frame quantized data and the second frame quantized data, the image data that is not saturated in the second frame quantized data may be taken, and the image data that is saturated or oversaturated in the second frame quantized data may be replaced by the quantized data at the corresponding position in the first frame multiplied by a multiple (sensitivity ratio of the second frame to the first frame), thereby fusing the first frame quantized data and the second frame quantized data.
Fig. 8 is a schematic structural diagram of a CMOS image sensor according to an embodiment of the present invention.
The CMOS image sensor 400 includes a row selection circuit 410, a column selection circuit 420 and a pixel array 430, and the pixel array 430 includes a plurality of pixel units arranged in an array, and the pixel units may be the pixel units described above with reference to fig. 3 to 5.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A pixel cell of a CMOS image sensor, comprising a first global exposure structure adapted to output a first frame of analog signals, comprising a first photoelectric conversion element, a first transfer transistor, a first reset transistor, a first storage node, a first stage source follower, a first isolation transistor, a second storage node, a second stage source follower, a first row select transistor, the pixel cell further comprising:
a second global exposure structure adapted to couple to the first global exposure structure and output a second frame of analog signals, and including a first control transistor SW, a second photoelectric conversion element, a second transmission transistor, a second reset transistor, a third storage node, a third stage source follower, a second isolation transistor, a fourth storage node, a fourth stage source follower, a second row selection transistor, and a first control transistor, wherein a first terminal of the first control transistor is connected to the fourth storage node, and a second terminal of the first control transistor is connected to a gate of the fourth stage source follower;
wherein the second stage source follower and the fourth stage source follower are the same source follower, the first row selection transistor and the second row selection transistor are the same row selection transistor, and one of the first photoelectric conversion element and the second photoelectric conversion element has a larger light sensing area than the other.
2. The pixel cell according to claim 1, wherein one of a light sensing area of the first photoelectric conversion element and a light sensing area of the second photoelectric conversion element, which is larger, is N times larger than one of smaller light sensing areas, and N is an integer greater than or equal to 8.
3. The pixel cell of claim 1, comprising a control module adapted to control the first control transistor to be turned on or off to control the first global exposure structure to output the first frame analog signal and the second global exposure structure to output the second frame analog signal.
4. The pixel cell of claim 1, wherein the first global exposure structure is a 9T-type global exposure structure, further comprising: the first photoelectric conversion element comprises a first control transistor, a third control transistor, a fourth control transistor, a first capacitor and a second capacitor, wherein the anode end of the first photoelectric conversion element is coupled with the first power line, and the cathode end of the first photoelectric conversion element is coupled with the first end of the first transmission transistor; a second terminal of the first transmission transistor is coupled to a second terminal of the first reset transistor; a first end of the first reset transistor is coupled to the second power line; the grid electrode of the first stage source electrode follower is coupled with the first storage node, the first end of the first stage source electrode follower is coupled with the second power line, and the second end of the first stage source electrode follower is coupled with the first end of the first isolation transistor; a second terminal of the first isolation transistor is coupled to the second storage node; second ends of the first capacitor and the second capacitor are coupled with the first power line; first ends of the second control transistor, the third control transistor and the fourth control transistor are coupled to the second storage node; a second terminal of the second control transistor is coupled to a first terminal of the first capacitor; a second terminal of the third control transistor is coupled to a first terminal of the second capacitor; a second terminal of the fourth control transistor is coupled to the first power line; the grid electrode of the second stage source electrode follower is coupled with the second storage node, and the first end of the second stage source electrode follower is coupled with the second power line; the second power line is a power line for providing working voltage for the pixel unit; the first end of the first row selection transistor is coupled to the second end of the second stage source follower, and the second end of the first row selection transistor is coupled to the bit line of the pixel unit.
5. The pixel cell of claim 4, wherein the second global exposure structure is a 9T global exposure structure, further comprising: a fifth control transistor, a sixth control transistor, a seventh control transistor, a third capacitor, and a fourth capacitor, wherein an anode terminal of the second photoelectric conversion element is coupled to the first power line, a cathode terminal of the second photoelectric conversion element is coupled to the first terminal of the second transmission transistor, a second terminal of the second transmission transistor is coupled to the second terminal of the second reset transistor, and the first terminal of the second reset transistor is coupled to the second power line; a gate of the third stage source follower is coupled to the third storage node, a first terminal of the third stage source follower is coupled to the second power line, a second terminal of the third stage source follower is coupled to the first terminal of the second isolation transistor, and a second terminal of the second isolation transistor is coupled to the fourth storage node; second ends of the third capacitor and the fourth capacitor are coupled to the first power line, and first ends of the fifth control transistor, the sixth control transistor and the seventh control transistor are coupled to the fourth storage node; a second terminal of the fifth control transistor is coupled to a first terminal of the third capacitor; a second terminal of the sixth control transistor is coupled to the first terminal of the fourth capacitor; a second terminal of the seventh control transistor is coupled to the first power line; the first end of the second row selection transistor is coupled to the second end of the fourth-stage source follower, and the second end of the second row selection transistor is coupled to the bit line of the pixel unit.
6. The pixel cell of claim 5, further comprising a quantization structure adapted to receive the first frame analog signal, quantize the first frame analog signal and obtain first frame quantized data based on the quantized first frame analog signal, receive the second frame analog signal, quantize the second frame analog signal and obtain second frame quantized data based on the quantized second frame analog signal, and add the first frame quantized data and the second frame quantized data to obtain final quantized data.
7. The pixel cell of claim 6, wherein the first frame analog signal comprises a first frame reset analog signal and a first frame exposure analog signal, wherein the second frame analog signal comprises a second frame reset analog signal and a second frame exposure analog signal, and wherein the quantization structure comprises:
a first quantization sub-module adapted to quantize the first frame reset analog signal to obtain first frame reset quantized data, quantize the first frame exposure analog signal to obtain the first frame exposure quantized data, subtract the first frame reset quantized data and the first frame exposure quantized data to obtain the first frame quantized data;
a second quantization sub-module adapted to quantize the second frame reset analog signal to obtain second frame reset quantized data, quantize the second frame exposure analog signal to obtain second frame exposure quantized data, and subtract the second frame reset quantized data and the second frame exposure quantized data to obtain the second frame quantized data;
a processing sub-module adapted to add the first frame quantized data and the second frame quantized data to obtain the final quantized data.
8. A method of controlling the pixel cell of claim 7, comprising:
setting a gate control signal of the first control transistor to a low level; setting gate control signals of the first reset transistor, the second reset transistor, the first transfer transistor, and the second transfer transistor to a high level to reset the first photoelectric conversion element and the second photoelectric conversion element;
after the grid control signals of the first reset transistor, the second reset transistor, the first transmission transistor and the second transmission transistor are set to be in a low level, the pixel unit starts to be exposed;
after exposure is finished, setting the grid control signals of the first isolation transistor and the second isolation transistor to be high level, and setting the grid control signals of the fourth control transistor and the seventh control transistor to be high level;
setting gate control signals of the first reset transistor and the second reset transistor to a high level to empty the first storage node and the third storage node;
setting gate control signals of the first reset transistor and the second reset transistor to a low level, and setting gate control signals of the second control transistor and the fifth control transistor to a high level, so as to charge the first capacitor and the third capacitor; setting gate control signals of the second control transistor and the fifth control transistor to a low level to store the reset analog signal of the first frame on the first capacitor and the reset analog signal of the second frame on the third capacitor;
setting gate control signals of the first and second transfer transistors to a high level, transferring charges collected during exposure from the first and second photoelectric conversion elements to the first and third storage nodes, respectively, and setting the gate control signals of the first and second transfer transistors to a low level after completion of the transfer;
setting gate control signals of the third control transistor and the sixth control transistor to be at a high level to charge the second capacitor and the fourth capacitor, and setting the gate control signals of the third control transistor and the sixth control transistor to be at a low level after the signals are established, so as to store the exposure analog signal of the first frame on the second capacitor and store the exposure analog signal of the second frame on the fourth capacitor.
9. The method of claim 8, comprising:
setting the grid control signals of the first isolation transistor, the second isolation transistor, the fourth control transistor and the seventh control transistor to be low level, and starting to enter a line-by-line reading stage;
setting the gate control signal of the first row selection transistor to a high level, setting the gate control signal of the first control transistor to a low level, setting the gate control signal of the fourth control transistor to a high level, and then setting the gate control signal of the fourth control transistor to a low level again to clear the second storage node, and then setting the gate control signal of the second control transistor to a high level, the second-stage source follower passing the reset analog signal of the first frame of the first capacitor to the bit line to sample the reset analog signal of the first frame, and then setting the gate control signal of the second control transistor to a low level;
setting a gate control signal of the fourth control transistor to a high level and then to a low level again to empty the second storage node, and then setting a gate control signal of the third control transistor to a high level, the second stage source follower transmitting an exposure analog signal of a first frame of the second capacitance to the bit line to sample the exposure analog signal of the first frame, and then setting the gate control signal of the third control transistor to a low level;
setting a gate control signal of the first control transistor to a high level, setting a gate control signal of the seventh control transistor to a high level, then to a low level, to clear the fourth storage node, then setting a gate control signal of the fifth control transistor to a high level, the second stage source follower passing a reset analog signal of a second frame of the third capacitance to the bit line to sample the second frame reset analog signal, then setting a gate control signal of the fifth control transistor to a low level;
setting a gate control signal of the seventh control transistor to a high level and then to a low level to clear the fourth storage node, and then setting a gate control signal of the sixth control transistor to a high level, the second stage source follower passing an exposure analog signal of a second frame of the fourth capacitance to the bit line to sample the exposure analog signal of the second frame, and then setting the gate control signal of the sixth control transistor to a low level.
10. The method of claim 9, comprising:
quantizing the first frame reset analog signal to obtain first frame reset quantized data, quantizing the first frame exposure analog signal to obtain first frame exposure quantized data, and subtracting the first frame reset quantized data and the first frame exposure quantized data to obtain the first frame quantized data;
quantizing the second frame reset analog signal to obtain second frame reset quantized data, quantizing the second frame exposure analog signal to obtain second frame exposure quantized data, and subtracting the second frame reset quantized data and the second frame exposure quantized data to obtain the second frame quantized data;
adding the first frame quantized data and the second frame quantized data to obtain the final quantized data.
11. A CMOS image sensor, comprising a row selection circuit, a column selection circuit and a pixel array, wherein the pixel array comprises a plurality of pixel units arranged in an array, and the pixel unit is the pixel unit as claimed in any one of claims 1 to 7.
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| CN114363537A (en) * | 2022-01-12 | 2022-04-15 | 锐芯微电子股份有限公司 | Pixel structure and array, circuit and method, image sensor, and storage medium |
| CN114363537B (en) * | 2022-01-12 | 2024-04-26 | 锐芯微电子股份有限公司 | Pixel structure and array, circuit and method, image sensor, and storage medium |
| CN114896927A (en) * | 2022-05-17 | 2022-08-12 | 中国科学院新疆理化技术研究所 | Simulation method for influence of different light intensities on full well capacity of pixel unit of CMOS image sensor after irradiation |
| CN114896927B (en) * | 2022-05-17 | 2024-04-30 | 中国科学院新疆理化技术研究所 | Simulation method for influence of different light intensities on full well capacity of pixel unit of CMOS image sensor after irradiation |
| CN115118881A (en) * | 2022-06-24 | 2022-09-27 | 维沃移动通信有限公司 | Signal processing circuit, image sensor, electronic device, and image processing method |
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