CN111916398A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- CN111916398A CN111916398A CN202010627473.XA CN202010627473A CN111916398A CN 111916398 A CN111916398 A CN 111916398A CN 202010627473 A CN202010627473 A CN 202010627473A CN 111916398 A CN111916398 A CN 111916398A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims description 41
- 239000010410 layer Substances 0.000 claims abstract description 147
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000011241 protective layer Substances 0.000 claims abstract description 39
- 238000002955 isolation Methods 0.000 claims abstract description 35
- 230000001590 oxidative effect Effects 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 96
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 7
- 229910006990 Si1-xGex Inorganic materials 0.000 claims description 2
- 229910007020 Si1−xGex Inorganic materials 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 230000002401 inhibitory effect Effects 0.000 abstract description 2
- 239000002070 nanowire Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000012212 insulator Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N titanium dioxide Inorganic materials O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Abstract
The invention discloses a manufacturing method of a semiconductor device, relates to the technical field of semiconductors, and is used for inhibiting the electric leakage problem of a parasitic channel and a source drain and improving the performance of the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: a substrate is provided. A plurality of fin structures are formed on the substrate, and each fin structure at least comprises a connecting part and a semiconductor part positioned on the connecting part. And forming a first shallow trench isolation layer in the groove between the adjacent fin structures, wherein the top height of the first shallow trench isolation layer is less than or equal to that of the connecting part. A protective layer is formed at least on the outer periphery of the semiconductor section. And removing the first shallow trench isolation layer. And oxidizing the connecting part exposed outside the protective layer to form an insulating part. The insulating section is used for isolating the semiconductor section from the substrate.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
SiGe or Ge materials have high carrier mobility, reliability, and process compatibility, and thus are commonly used materials for manufacturing high-mobility conductive channels of PMOS (P-Metal-Oxide-Semiconductor) devices.
However, the forbidden bandwidth of the SiGe or Ge material is relatively small, so that the semiconductor device including the above conductive channel is prone to leakage problems of the parasitic channel and the source and drain, resulting in poor operation performance of the semiconductor device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which is used for inhibiting the leakage problem of a parasitic channel and a source drain and improving the performance of the semiconductor device.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, the method comprising:
providing a substrate; a plurality of fin-shaped structures are formed on the substrate, each fin-shaped structure at least comprises a connecting part and a semiconductor part positioned on the connecting part;
forming a first shallow trench isolation layer in the groove between the adjacent fin-shaped structures, wherein the top height of the first shallow trench isolation layer is less than or equal to the top height of the connecting part;
forming a protective layer at least on an outer periphery of the semiconductor section;
removing the first shallow trench isolation layer;
oxidizing the connecting part exposed outside the protective layer to form an insulating part; the insulating section is used for isolating the semiconductor section from the substrate.
Compared with the prior art, in the manufacturing method of the semiconductor device, after the first shallow trench isolation layer is formed in the groove between the adjacent fin-shaped structures, the protective layer is formed at least on the periphery of the semiconductor part included in the fin-shaped structures. The presence of the protective layer may improve the thermal stability of the semiconductor portion during subsequent low temperature oxidation processes. And then removing the first shallow slot isolation layer, and oxidizing the connecting part exposed outside the protective layer to form an insulating part. Based on this, the semiconductor section and the substrate can be separated by the insulating section. Meanwhile, a source region, a drain region and a channel region in the semiconductor device are all formed on the insulating part, and the insulating part is in a non-conductive insulating structure, so that the problem of electric leakage of a parasitic channel and the source and the drain can be solved. As is apparent from the above description, the insulating portion is an insulating structure formed by oxidizing the connecting portion in the process of manufacturing the semiconductor device, and does not form a part of the substrate. Under the above circumstances, in the process of manufacturing the semiconductor device, other substrates meeting the requirements, such as a silicon substrate or a germanium-silicon substrate with lower cost than a silicon-on-insulator substrate, can be adopted, so that the problem of leakage of a parasitic channel and a source drain can be solved, and the manufacturing cost of the semiconductor device can be reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a structure of a strained buffer material layer after forming the strained buffer material layer according to an embodiment of the invention;
FIGS. 3a to 3d are schematic structural diagrams illustrating a semiconductor material layer formed according to an embodiment of the invention;
fig. 4a to 4d are schematic structural diagrams illustrating a fin structure formed according to an embodiment of the present invention;
FIGS. 5a to 5d are schematic structural diagrams illustrating the first STI layer after being formed according to an embodiment of the present invention;
FIGS. 6a to 6d are schematic structural diagrams after forming a protection layer according to an embodiment of the invention;
FIGS. 7a to 7d are schematic views illustrating a process of forming an insulating portion according to an embodiment of the present invention;
FIGS. 8a 1-8 d5 are schematic diagrams of another process for forming an insulation portion according to an embodiment of the present invention;
fig. 9a to 9d are schematic structural diagrams illustrating the formation of the second shallow trench isolation layer and the removal of the protection layer and the mask pattern in the embodiment of the present invention.
Reference numerals:
the shallow trench isolation structure comprises a substrate 1, a strain buffer material layer 2, a strain buffer layer 21, a semiconductor material layer 3, a laminated layer 31, a sacrificial material layer 311, a channel material layer 312, a fin-shaped structure 4, a connecting portion 41, a semiconductor portion 42, a sacrificial layer 421, a channel layer 422, a mask pattern 5, a first shallow trench isolation layer 6, a protective layer 7, an insulating portion 8, an oxide layer 9 and a second shallow trench isolation layer 10.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Because the SiGe or Ge material has higher carrier mobility, reliability and process compatibility, the SiGe or Ge material becomes a common material for manufacturing a high-mobility conducting channel of a PMOS device. However, the forbidden bandwidth of the SiGe or Ge material is smaller than that of the Si material, so that the semiconductor device including the above conductive channel is more prone to have the leakage problem of the parasitic channel and the source and drain than the semiconductor device formed by the Si material, and the working performance of the semiconductor device is poor.
In order to solve the above-mentioned leakage problem, a silicon-on-insulator substrate is generally selected as a substrate of a semiconductor device during the manufacture of the semiconductor device. Based on this, structures such as a source region and a drain region in the semiconductor device are formed on a buried oxide layer of a silicon-on-insulator substrate. The buried oxide layer is a non-conductive insulating layer, so that the problem of electric leakage of a parasitic channel and a source drain can be solved. However, the conventional silicon-on-insulator substrate has a high cost, so that the manufacturing cost of the semiconductor device is high.
In order to solve the above technical problem, embodiments of the present invention provide a method for manufacturing a semiconductor device. By means of oxidizing the connection portion, an insulation portion is obtained at the location of the connection portion. The insulating portion can isolate the semiconductor portion from the substrate, thereby suppressing leakage of a parasitic channel and the source and drain. And the silicon-on-insulator substrate is not needed to be used as the substrate of the semiconductor device, so that the manufacturing cost of the semiconductor device is reduced.
Referring to fig. 1, embodiments of the present invention provide a method of fabricating a semiconductor device that may be used to fabricate a FinFET device, a stacked nanowire, or a gate-all-around-chip device. A method of manufacturing a semiconductor device provided by an embodiment of the present invention will be described below with reference to cross-sectional views of operations shown in fig. 2 to 9 d.
First, a substrate 1 is provided. The substrate 1 may be a semiconductor substrate such as a silicon substrate or a germanium substrate.
Referring to fig. 2, in one example, a layer of strain buffer material 2 may be formed on a substrate 1 overlying the substrate 1. The presence of the strained buffer material layer 2 may provide stress for a subsequently formed channel region (not shown). It is to be understood that the strain buffer material layer 2 may not be formed on the substrate 1.
Illustratively, the strain buffer material layer 2 may be formed on the substrate 1 by chemical vapor deposition or the like. The material contained in the strain buffer material layer 2 may be Si1-yGeyY is more than 0 and less than or equal to 1. The thickness of the strain buffer material layer 2 may be set according to practical application scenarios, and is not limited in particular here. Illustratively, the layer thickness of the strain buffer material layer 2 may be 0.5 μm to 3 μm.
Referring to fig. 3a to 3d, a layer of semiconductor material 3 is formed over a substrate 1.
Specifically, in one example, referring to fig. 3a, when the manufactured semiconductor device is a FinFET device, the semiconductor material layer 3 may be formed directly on the substrate 1 by chemical vapor deposition or the like. The material contained in the semiconductor material layer 3 determines the material contained in the subsequent channel region, and thus can be provided according to the material contained in the channel region. Illustratively, the semiconductor material layer 3 may be Si1-xGex，0＜x≤1。
In another example, referring to fig. 3b, when the semiconductor device being fabricated is a FinFET device and the layer of strain buffer material 2 has been formed on the substrate 1, the layer of semiconductor material 3 described above may be formed on the layer of strain buffer material 2 in the manner described above.
In yet another example, referring to fig. 3c, when the semiconductor device being fabricated is a stacked nanowire or gate-all-around-chip device, the semiconductor material layer 3 may be formed directly on the substrate 1 in the manner described above. The semiconductor material layer 3 comprises at least one layer stack 31. Each stack 31 includes a sacrificial material layer 311, and a channel material layer 312 on the sacrificial material layer 311. Wherein, for the convenience of obtaining nanowires or chips (not shown), the material contained in the channel material layer 312 and the material contained in the sacrificial material layer 311 need to have a certain etching selectivity. Illustratively, the channel material layer 312 may include Si as a material1-xGexX is more than 0 and less than or equal to 1. The material contained in the sacrificial material layer 311 may be Si1-zGezAnd z is more than or equal to 0 and less than or equal to 0.8. And, the content of Ge in the sacrificial material layer 311 is at least 20% lower than the content of Ge in the channel material layer 312.
In yet another example, referring to fig. 3d, when the semiconductor device being fabricated is a stacked nanowire or gate-all-around-chip device and the layer of strained buffer material 2 has been formed on the substrate 1, the layer of semiconductor material 3 described above may be formed on the layer of strained buffer material 2 in the manner described above.
Referring to fig. 4a to 4b, several fin structures 4 are formed on a substrate 1. Each fin structure 4 includes a connection portion 41, and a semiconductor portion 42 on the connection portion 41. The semiconductor portion 42 has a source region formation region (not shown), a drain region formation region (not shown), and a channel region between the source region formation region and the drain region formation region. The relevant parameters (height, width, etc.) of the fin structure 4 may be set with reference to the relevant parameters of the channel region.
Specifically, in one example, referring to fig. 4a and 4c, when only the semiconductor material layer 3 is formed on the substrate 1, and the strain buffer material layer 2 is not formed, the mask pattern 5 may be formed on the semiconductor material layer 3. The mask pattern 5 covers a region of the semiconductor material layer 3The domain is a region where the fin structure 4 needs to be formed. Then, under the effect of the mask pattern 5, the semiconductor material layer 3 and the substrate 1 may be etched from top to bottom by using a dry etching method or the like, so as to form the fin-shaped structure 4. The semiconductor portion 42 is a sub-fin portion formed by etching the semiconductor material layer 3. The connection portion 41 is a sub-fin portion formed by etching the substrate 1. The mask pattern 5 may be a mask pattern made of only SiN material, or the mask pattern 5 may be made of SiO2And a mask pattern of the SiN stack. Of course, the material contained in the mask pattern 5 and the specific structure thereof may be set according to actual conditions. Further, the depth of etching the substrate 1 may be set according to the actual situation.
In another example, referring to fig. 4b and 4d, when the strain buffer material layer 2 and the semiconductor material layer 3 are sequentially formed on the substrate 1, at least the semiconductor material layer 3 and the strain buffer material layer 2 may be etched in the above manner to form the fin structure 4.
When the thickness of the strain buffer material layer 2 is relatively thin, the substrate 1 needs to be etched partially after etching the semiconductor material layer 3 and the strain buffer material layer 2 from top to bottom in the process of forming the fin-shaped structure 4. At this time, the semiconductor portion 42 is a sub-fin portion formed by etching the semiconductor material layer 3. And the connection portion 41 is a sub-fin portion formed by etching the strain buffer material layer 2 and a part of the thickness of the substrate 1.
When the thickness of the strain buffer material layer 2 is relatively moderate, the fin structure 4 meeting the height requirement can be obtained after etching the semiconductor material layer 3 and the strain buffer material layer 2 from top to bottom in the process of forming the fin structure 4. At this time, the substrate 1 has no unetched strain buffer material layer 2 thereon, and the substrate 1 is not etched. When the thickness of the strain buffer material layer 2 is relatively thick, the semiconductor material layer 3 and the strain buffer material layer 2 are etched from top to bottom in the process of forming the fin-shaped structure 4, and after the fin-shaped structure 4 is obtained, a part of the strain buffer material layer 2 which is not etched still exists on the substrate 1. The non-etched portions of the strain buffer material layer 2 correspond to the strain buffer layer 21. As can be seen from the above, when the thickness of the strain buffer material layer 2 is relatively moderate or thick, the connection portion 41 is a sub-fin portion formed by etching the strain buffer material layer 2.
Further, when the manufactured semiconductor device is a stacked nanowire or a gate-all-around device, the above-described semiconductor section 42 includes a sacrificial layer 421 sequentially stacked on the connection section 41, and a channel layer 422 located on the sacrificial layer 421. The sacrificial layer 421 is a film layer formed after the sacrificial material layer 311 is etched, and the channel layer 422 is a film layer obtained after the channel material layer 312 is etched.
Referring to fig. 5a to 5d, a first shallow trench isolation layer 6 is formed in the trench between adjacent fin structures 4. The top height of the first shallow trench isolation layer 6 is less than or equal to the top height of the connection portion 41.
For example, an isolation material may be deposited on the formed structure, and then the isolation material may be planarized to ensure that the etching-back depth of the isolation material in each region is the same when the etching-back process is performed subsequently. And then, carrying out back etching treatment on the isolation material. After the etching back process, the first shallow trench isolation layer 6 is formed by the remaining isolation material. Specifically, the depth of the back etching can be set according to practical situations, and is not particularly limited herein. For example: the top height of first shallow trench isolation layer 6 after the etch back process is not higher than the top height of connection portion 41.
Referring to fig. 6a to 6d, the protective layer 7 is formed at least on the outer periphery of the semiconductor section 42. The presence of the protective layer 7 may improve the thermal stability of the semiconductor portion 42 during subsequent low temperature oxidation processes.
Specifically, referring to fig. 6a to 6d, in the case that the mask pattern 5 still remains on the fin-shaped structure 4, a protective material layer may be deposited on the formed structure by chemical vapor deposition or PEALD (plasma enhanced atomic layer deposition). The protective material layer is then anisotropically etched to obtain the protective layer 7. At this time, protective layer 7 is formed on the outer wall of mask pattern 5 and the outer wall of fin structure 4 exposed outside first shallow trench isolation layer 6.
Alternatively, in the case where the mask pattern 5 on the semiconductor portion 42 is removed after the fin structure 4 is formed, the protective layer 7 covering the outer periphery of the fin structure 4 at a predetermined height may be formed in the above-described manner. The fin structure 4 at the predetermined height is the fin structure 4 exposed outside the first sti 6. At this time, the protective layer 7 may also protect the top of the semiconductor section 42.
Specifically, the material contained in the protective layer 7 may be an insulating material such as SiN that satisfies the requirements.
After the formation of the protective layer 7, the first shallow trench isolation layer 6 needs to be removed in order to facilitate the subsequent oxidation of the connection portion 41 exposed outside the protective layer 7.
Referring to fig. 7a to 8d5, after removing first shallow trench isolation 6, connection portion 41 exposed outside protective layer 7 is oxidized to form insulating portion 8. The insulating portion 8 is used to isolate the semiconductor portion 42 from the substrate 1.
In one example, referring to fig. 7a to 7d, the connection portion 41 exposed outside the protective layer 7 may be subjected to a low-temperature oxidation process so that the connection portion 41 exposed outside the protective layer 7 is oxidized at one time to form the insulating portion 8. Specifically, a furnace tube heat treatment mode or a rapid heat treatment mode can be adopted; and in O2And N2In an atmosphere containing O, or in a gas containing O3The connection portion 41 exposed to the outside of the protective layer 7 is subjected to low-temperature oxidation treatment in the atmosphere of (a). Wherein, when the furnace tube heat treatment mode is adopted for low-temperature oxidation treatment, the treatment temperature can be 500-850 ℃, and the treatment time can be 10-60 min. When the low-temperature oxidation treatment is carried out by adopting a rapid thermal treatment mode, the treatment temperature can be 600-850 ℃, the treatment time can be 30-60 s, and the treatment period can be 1-10. The specific values of the above-mentioned processing time, processing temperature, and processing cycle may be set according to actual circumstances, and are not particularly limited herein. In addition, when in O2And N2O in the low-temperature oxidation treatment in the atmosphere of (2)2And N2The gas volume ratio of (2) can also be set according to actual conditions.
In another example, referring to fig. 8a1 to 8d5, the insulating portion 8 may be formed by performing low-temperature oxidation treatment and etching a plurality of times on the connecting portion 41 exposed outside the protective layer 7. Specifically, referring to fig. 8a1 to 8d1, the first low-temperature oxidation treatment is performed on the connection portion 41 exposed outside the protective layer 7 (the conditions of the first low-temperature oxidation treatment can be referred to above). After the first low-temperature oxidation treatment, an oxide layer 9 is formed on the connecting portion 41 exposed outside the protective layer 7 and the surface of the substrate 1 and/or the strain buffer layer 21, and the thickness of the oxide layer 9 can be set according to actual conditions. Referring to fig. 8a2 to 8d2, the oxide layer 9 formed after the first low-temperature oxidation treatment may be removed by using an HF solution to expose the remaining connecting portion 41 that is not oxidized. Referring to fig. 8a3 to 8d3, the non-oxidized residual connection 41 is subjected to a second low temperature oxidation process to form an oxide layer 9 again with a certain thickness on the residual connection 41 and the surface of the substrate 1 and/or the strain buffer layer 21. Referring to fig. 8a4 to 8d4, the second oxide layer 9 is removed again using HF solution. The above operation is repeated until the entire region of the connection portion 41 exposed outside the protective layer 7 is oxidized to form the oxide layer 9. Referring to fig. 8a 5-8 d5, the oxide layer 9 formed last is the insulation 8. Specifically, in order to avoid the insulating portion 8 and the semiconductor portion 42 from being inclined due to a large difference between the width of the insulating portion 8 and the width of the semiconductor portion 42, the finally formed oxide layer 9 needs to have a certain width. The specific value of the width may be set according to an actual application scenario, and is not particularly limited herein.
Referring to fig. 9a to 9d, a second shallow trench isolation layer 10 is formed in the trench between adjacent fin structures 4. The top height of the second shallow trench isolation 10 is less than or equal to the bottom height of the semiconductor section 42. The second shallow trench isolation layer 10 may contain a material of SiO2Etc. insulating material. The protective layer 7 and the mask pattern 5 on the semiconductor portion 42 are then removed, exposing at least the semiconductor portion 42.
In an actual application process, when the FinFET device and the stacked nanowire or gate-around-chip device are manufactured by using the manufacturing method of the semiconductor device provided by the embodiment of the invention, after the protective layer 7 and the mask pattern 5 are removed, operations such as formation of the sacrificial gate, the sidewall, the source region, the drain region, the gate stack structure, and the like need to be performed.
Illustratively, sacrificial gates and spacers are formed at least at the periphery of the semiconductor portion 42 in the channel region. Thereafter, at least the portions of the semiconductor portions 42 located in the source region formation region and the drain region formation region are removed. Then, a source region is epitaxially grown in the source region formation region, and a drain region is epitaxially grown in the drain region formation region. The sacrificial gate is then removed, exposing the channel region. For a FinFET device, after the channel region is exposed, a gate stack structure may be formed at the periphery of the channel region. For the stacked nanowire or chip-on-gate device, after the channel region is exposed, the sacrificial layer 421 in the channel region needs to be selectively removed, and the channel layer 422 in the channel region is released, so as to obtain at least one layer of nanowire or chip. Finally, a gate stack structure surrounding the nanowire or the sheet is formed.
The gate stack structure may include a gate dielectric layer and a gate electrode sequentially formed. Wherein, the gate dielectric layer may contain HfO2、ZrO2、TiO2Or Al2O3And materials with higher dielectric constants. The gate electrode may be made of conductive material such as TiN, TaN, or TiSiN.
It should be noted that the above operations for forming the sacrificial gate, the sidewall spacer, the source region, the drain region and the gate stack structure are not essential features of the embodiments of the present invention, and therefore, only brief descriptions thereof are provided in this specification so that those skilled in the art can easily implement the embodiments of the present invention. It is fully contemplated by one of ordinary skill in the art that the above-described structures may be otherwise fabricated.
As can be seen from the above, the semiconductor section 42 and the substrate 1 can be isolated by the insulating section 8. Meanwhile, a source region, a drain region and a channel region in the semiconductor device are all formed on the insulating part 8 and the second shallow trench isolation layer 10, and the insulating part 8 and the second shallow trench isolation layer 10 are in a non-conductive insulating structure, so that the problem of electric leakage of a parasitic channel and a source drain can be solved. The insulating portion 8 is an insulating structure formed by oxidizing the connecting portion 41 in the process of manufacturing the semiconductor device, and does not constitute a part of the substrate 1. Under the above circumstances, in the process of manufacturing the semiconductor device, other substrates meeting the requirements, such as a silicon substrate or a germanium-silicon substrate with lower cost than a silicon-on-insulator substrate, can be adopted, so that the problem of leakage of a parasitic channel and a source drain can be solved, and the manufacturing cost of the semiconductor device can be reduced.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (11)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate; a plurality of fin-shaped structures are formed on the substrate, each fin-shaped structure at least comprises a connecting part and a semiconductor part positioned on the connecting part;
forming a first shallow trench isolation layer in a trench between adjacent fin structures, wherein the top height of the first shallow trench isolation layer is less than or equal to the top height of the connecting part;
forming a protective layer at least on an outer periphery of the semiconductor section;
removing the first shallow groove isolation layer;
oxidizing the connecting part exposed outside the protective layer to form an insulating part; the insulating portion is used for isolating the semiconductor portion from the substrate.
2. The method according to claim 1, wherein the fin-shaped structure comprises the connection portion, a semiconductor portion on the connection portion, and a mask pattern on the semiconductor portion;
forming the protective layer at least on the outer periphery of the semiconductor section includes:
forming the protective layer surrounding the outer wall of the mask pattern and the outer wall of the fin structure exposed outside the first shallow trench isolation layer.
3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein a material contained in the protective layer is SiN.
4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein oxidizing the connection portion exposed outside the protective layer to form the insulating portion comprises:
and carrying out low-temperature oxidation treatment on the connecting part exposed outside the protective layer, so that the connecting part exposed outside the protective layer forms the insulating part.
5. The method for manufacturing a semiconductor device according to claim 4, wherein O is2And N2In an atmosphere containing O, or in a gas containing O3Is performed in the atmosphere of (a).
6. The method for manufacturing a semiconductor device according to claim 4, wherein the low-temperature oxidation treatment is performed on the connection portion by a furnace heat treatment method or a rapid heat treatment method; wherein the content of the first and second substances,
the treatment temperature of the furnace tube heat treatment mode is 500-850 ℃, and the treatment time is 10-60 min;
the rapid heat treatment mode has the treatment temperature of 600-850 ℃, the treatment time of 30-60 s and the treatment period of 1-10.
7. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein oxidizing the connection portion exposed outside the protective layer to form the insulating portion comprises:
oxidizing the connecting part exposed outside the protective layer to form an oxide layer at least on the surface of the connecting part;
removing the oxide layer;
and circulating the two steps of operation until all the areas of the connecting part exposed outside the protective layer are oxidized to form the oxide layer, wherein the finally formed oxide layer is the insulating part.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the oxide layer is removed with an HF solution.
9. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the semiconductor portion includes a source region formation region, a drain region formation region, and a channel region located between the source region formation region and the drain region formation region;
the channel region contains a material including at least Si1-xGex，0＜x≤1。
10. The method as claimed in claim 1 or 2, wherein a strain buffer material layer is formed on the substrate, and the connecting portion comprises at least a sub-fin portion formed by etching the strain buffer material layer.
11. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein after the insulating portion is formed, the method for manufacturing a semiconductor device further comprises:
forming a second shallow trench isolation layer in the trench between the adjacent fin structures, wherein the top height of the second shallow trench isolation layer is less than or equal to the bottom height of the semiconductor part;
and removing the protective layer.
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