CN111913840A

CN111913840A - Verification method of APB-UART module based on UVM

Info

Publication number: CN111913840A
Application number: CN202010360438.6A
Authority: CN
Inventors: 王忆文; 段一杰
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-04-30
Filing date: 2020-04-30
Publication date: 2020-11-10

Abstract

The invention relates to the field of chip verification, and mainly realizes a verification method of an APB-UART module based on UVM. The verification platform constructed by the verification method comprises the following steps: the agent component realizes data interaction with different protocol ports; the scoreboard component is used for realizing data comparison; a checker component for realizing baud rate detection; a register model with an early warning mechanism is added; a verification environment env component; a coverage collection component, and the like. The verification method also designs corresponding test cases and sequences according to various functions of the APB-UART module. The verification platform can realize the input of various test stimuli, has the functions of automatic comparison of results and coverage rate collection, and can quickly and completely verify the APB-UART module.

Description

Verification method of APB-UART module based on UVM

Technical Field

The invention relates to the field of chip Verification, in particular to a Verification method of a protocol conversion module based on UVM (Universal Verification method).

Background

With the continuous development of the integrated circuit theory and the appearance of soc (system On chip) technology, designers have improved the design capability and efficiency of chips to some extent, which makes the complexity and scale of chips increase gradually. Because of the continuous improvement of the process and the lower tolerance of the market to the product defects, the loss to be borne after each tape-out failure is larger and larger, so that the verification work before tape-out becomes very important and becomes an indispensable loop in the chip design flow gradually.

The APB (advanced Peripheral bus) protocol belongs to one of AMBA bus protocols, has the characteristics of low power consumption, simple interconnection signals and the like, and is suitable for low-performance Peripheral modules. The UART (Universal Asynchronous Receiver-Transmitter) protocol is a common protocol in serial Asynchronous communication, has low cost and is suitable for low-performance long-distance transmission scenes. In a typical AMBA bus architecture, the APB-UART module may perform protocol conversion on read and write data and perform certain control on data transmission, and if the processor wants to access data in a UART format, the APB-UART module is indispensable. In addition, due to the requirement of data transmission, the module can also realize functions of hardware flow control, data format adjustment, interrupt feedback, UART format detection and the like.

The Universal Verification Methodology (UVM) provides a set of standard class library based on SystemVerilog language, which not only enables a Verification engineer to quickly complete the construction work of a bottom Verification platform, but also provides a set of unified standards, restricts and guides the Verification method and improves the reusability and portability of the Verification platform. The verification platform established according to the UVM verification methodology can realize the functions of test excitation random generation, verification result self-detection, function coverage rate collection and the like, and can sufficiently cope with most scenes in the current verification process.

For the verification of the APB-UART protocol conversion module, the traditional verification method generally uses Verilog language to write a test platform, and verifies the module functions one by applying a directional test excitation mode. In the verification process, an FPGA development board can be used for hardware detection, or MATLAB software is used for related assistance. However, the above methods all have the disadvantages of low reusability, low verification efficiency, difficulty in complete verification, and the like, and cannot be qualified for the verification work of complex functional modules.

Disclosure of Invention

In order to solve the problems, the invention compiles an APB-UART module verification platform based on UVM verification methodology, and fully and completely verifies the module by applying various stimuli. Due to the universality and portability of the UVM verification platform, the verification platform can be transplanted for use, so that the verification work of other modules with similar functions is accelerated.

The composition of the APB-UART module verification platform is as follows.

interface: and packaging the signal ports with specific attributes together to realize the interconnection work between the module to be tested and the verification platform. The verification platform has three interfaces, and corresponding signals of the APB, the UART and the Modem are respectively packaged.

agent class component: the assembly is used for processing operations related to a specific port, realizing conversion of signal-level data and transaction-level data, and completing driving and acquisition work of a specific protocol. The verification platform comprises four agents which respectively correspond to an APB end, a UART receiving end, a UART transmitting end and a Modem end.

scoreboard-like components: the component is used for realizing data comparison work and is a key component for verifying the automatic detection result of the platform. The verification platform has three scoreboards which are respectively used for UART received data comparison, UART sent data comparison and Modem data comparison.

A checker component: the system is used for sampling the baud rate signal and judging whether the signal frequency is consistent with the configured expected frequency.

A coverage component: the verification platform is used for collecting functional coverage rates, and the verification platform respectively collects the coverage rates of the registers and the read-write data formats.

The env component: the creation and interconnection work of the components is realized, and a complete verification platform for a specific module is constructed.

Register model: the modeling work of the internal register of the DUT is realized, a total number of 15 registers are included, and the related register types comprise Readable and Writable (RW), read-only (RO), write-only (WO), zero clearing after Reading (RC) and the like. In addition, the component also adds a hardware access path of each register, and provides a basis for the back door access of the registers.

Test cases and sequences: the method is used for establishing a verification environment, interconnecting the module to be tested and the verification platform and realizing corresponding test excitation.

Drawings

FIG. 1 is a general architecture of an APB-UART module validation platform.

FIG. 2 is a schematic diagram of frequency-doubled sampling of the UART data 16.

Figure 3 is an interconnection diagram of scoreboard components and related components.

Detailed Description

The general architecture of the present verification platform is shown in fig. 1, wherein the specific implementation of each module is as follows.

The verification platform uses agents to realize the driving and collection work of a specific port, and comprises four agents which are Apb _ Agent, Rx _ Agent, Tx _ Agent and Modem _ Agent in total, wherein the Rx _ Agent and the Tx _ Agent are generated by instantiating a Uart _ Agent. As can be seen in the overall architecture diagram, the different agents encapsulate the corresponding driver, monitor, sequence. Each agent realizes the conversion of data from a transaction level to a signal level through a corresponding driver component and drives the data to a related port of the DUT; collecting related port signals at a specific moment through a corresponding monitor component, converting the signals from a signal level to a transaction level, and sending the signals to a subsequent module for use; and independently sending out the generation work of different incentives through the corresponding sequence r, and completing the generation work of the incentives by cooperating with the sequence. Apb _ Agent and Modem _ Agent use APB clock as reference clock for driving and sampling, and Uart _ Agent uses multiplied baud rate signal additionally, and adopts different sampling strategies to different UART data bits in internal monitor to ensure data accuracy: for the start bit and the stop bit in the UART data, the first 8 periods are continuously taken to eliminate interference, and for the data bit, the data in the 8 th period represents the final sampling value, as shown in fig. 2. In addition, the control of sampling time is realized through an event in the Uart _ Monitor; and data receiving and transmitting information of the UART port is timely collected through semaphore and transmitted to the corresponding test, so that the problem of indefinite simulation ending time is solved.

The verification platform uses the Scoreboard component to realize data comparison work, and the Scoreboard component comprises three scoreboards, namely Rx _ Scoreboard, Tx _ Scoreboard and Modem _ Scoreboard. The data source in the Scoreboard is divided into two parts, the first part is the register read-write data information collected by Apb _ Agent, and the second part is the data information collected by the corresponding Agent, including data received and sent by UART and modem input and output data. In addition, a register model is introduced into the scoreboard, and specific information can be transferred to the coverage collection component through a corresponding transmission port, as shown in fig. 3.

The verification platform uses a checker component to realize the detection related to the baud rate configuration. The component can continuously acquire frequency information of a corresponding clock and detect the baud rate frequency division function according to the value of a relevant register in the DUT.

The register model adopts a three-level structure to realize the modeling of the registers in the DUT, namely, the information of addresses, attributes and the like of 15 registers is described through field, reg and block structures. The register model also adds a hardware access path of each register, and provides a basis for the back door access of the registers. In addition, because part of registers have the same access address, the register model adds an early warning mechanism by using a callback mechanism and a hook function, and can output early warning information when unexpected access is performed on a specific register.

The verification platform verifies the common functions of the APB-UART module by applying various test stimuli and sequences, and related test cases cover the following contents: detecting related functions of a register; detecting basic transceiving functions, including various data content and data format combinations; detecting a hardware flow control function; detecting an interrupt function; detecting a baud rate configuration function; detecting a character/half character read-write function; detecting a port protocol; detecting an overrun function; receiving data error monitoring function detection; receiving a break low level function detection; sending data null prompt detection; sending a break low level function detect; FIFO flush function detection, etc.

The verification platform covers the access condition and the receiving and sending data format of each register through the coverage rate collection component, and provides an important basis for representing the verification progress.

Claims

1. A verification method of an APB-UART module based on UVM is characterized in that a verification platform is established by adopting UVM verification methodology, and the APB-UART module is verified by applying a plurality of test stimuli, and the verification platform comprises: the four agent components are internally packaged with corresponding drivers, monitors, sequencers and the like, and respectively realize data driving and acquisition work of an APB port, a UART transmitting port, a UART receiving port and a Modem port; the three scoreboard assemblies respectively realize comparison work of APB read-write data, UART received data, UART sent data and Modem data; the checker component realizes the detection of the baud rate function; the register model with an early warning mechanism realizes the early warning function when the specific register is illegally accessed; the coverage rate collection component realizes the collection of the functional coverage rate; verifying the environment env and configuring a config file; a plurality of test cases and sequences cover the common functions of the APB-UART module, and mainly comprise: register correlation detection, basic transceiving function detection, Modem function detection, interrupt function detection, baud rate function detection, word/half-word read-write function detection, port protocol detection and the like.

2. The verification method of the APB-UART module based on UVM of claim 1, characterized in that the problem of interaction effect among the same address registers is solved by using callback mechanism and hook function: the UART module generally uses a DLAB register/domain as a selection signal, different registers with the same address are respectively enabled according to the level of DLAB, at the moment, the condition of register access error caused by DLAB configuration error is easy to occur, the register model realizes the alarm function when unexpected access is carried out on a specific register, and the problems are solved.

3. The verification method of the APB-UART module based on UVM of claim 1, wherein: the problem of unclear simulation ending time is solved by collecting the data receiving and sending conditions of the UART port in time through semaphore and transmitting the data receiving and sending conditions to the corresponding test.

4. The verification method of the APB-UART module based on UVM of claim 1, wherein: the problem of ambiguous sampling time in Modem _ Monitor is solved through the event.

5. The verification method of the APB-UART module based on UVM of claim 1, wherein: the data results are automatically compared through the scoreboard component; the collection of the function coverage rate is realized through the coverage rate collection component, and a judgment basis is provided for the simulation progress.