CN111900163A - Transistor and preparation method thereof - Google Patents

Transistor and preparation method thereof Download PDF

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Publication number
CN111900163A
CN111900163A CN202010568263.8A CN202010568263A CN111900163A CN 111900163 A CN111900163 A CN 111900163A CN 202010568263 A CN202010568263 A CN 202010568263A CN 111900163 A CN111900163 A CN 111900163A
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layer
metal contact
side wall
gate stack
stack structure
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CN111900163B (en
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崔锺武
金成基
杨涛
高建峰
李俊峰
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

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  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application relates to the technical field of semiconductors, in particular to a transistor and a preparation method thereof, which comprises the following steps: a substrate having source/drain regions formed thereon; the gate stack structure is positioned on the substrate; a metal contact plug connected to the source/drain region; the side wall is positioned between the gate stack structure and the metal contact plug; and the air gap is positioned in the side wall. Because the dielectric constant of the air is far smaller than that of the silicon oxide, the parasitic capacitance between the gate stack structure and the metal contact plug is greatly reduced, and the performance of the transistor is improved.

Description

Transistor and preparation method thereof
Technical Field
The application relates to the technical field of semiconductors, in particular to a transistor and a preparation method thereof.
Background
With the increasing density (scaling down) of DRAM peripheral region transistors (DRAM peripheral transistors), the proportion (contribution) of parasitic capacitance (parasitic capacitance) between the gate and the metal contact (gate to MC contact) becomes larger, degrading the performance of the transistor.
Disclosure of Invention
The present application is directed to solving the above-mentioned technical problems in the related art. Therefore, the application provides a transistor and a preparation method thereof, which can reduce the parasitic capacitance between a grid and a metal contact and improve the performance of the transistor.
In order to achieve the above object, a first aspect of the present application provides a transistor including:
a substrate having source/drain regions formed thereon;
the gate stack structure is positioned on the substrate;
a metal contact plug connected to the source/drain region;
the side wall is positioned between the gate stack structure and the metal contact plug;
and the air gap is positioned in the side wall.
In a second aspect, the present application provides a method for manufacturing a transistor, including the steps of:
providing a substrate;
forming the source/drain region on the substrate;
forming a gate stack structure on the substrate;
forming first side walls on two sides of the gate stack structure;
forming a metal contact hole on the source/drain region;
depositing an isolation layer on the inner wall of the metal contact hole, and filling a metal contact plug;
removing the first side wall;
and backfilling the side wall materials to form second side walls with air gaps on two sides of the gate stack structure.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram showing a gate stack structure, an offset spacer and a cap layer formed on a semiconductor substrate;
FIG. 2 is a schematic diagram showing the structure of FIG. 1 after removal of a portion of the cap layer;
FIG. 3 is a schematic diagram showing the structure of FIG. 2 after an etch stop layer has been formed thereon;
FIG. 4 is a schematic diagram illustrating the structure of FIG. 3 after an interlevel dielectric layer has been formed thereon;
FIG. 5 is a schematic diagram illustrating the structure of FIG. 4 after metal contact holes have been formed therein;
FIG. 6 shows a schematic view of the structure after forming an isolation layer on the structure shown in FIG. 5;
FIG. 7 shows a schematic view of the structure shown in FIG. 6 after removal of the bottom wall of the isolation layer;
fig. 8 is a schematic view showing a structure after filling a metal contact plug on the structure shown in fig. 7;
FIG. 9 is a schematic diagram illustrating the structure of FIG. 8 after removal of the interlevel dielectric layer;
FIG. 10 shows a schematic view of the structure after removal of a portion of the etch stop layer over the structure shown in FIG. 9;
FIG. 11 is a schematic diagram of the structure shown in FIG. 10 after the removal of the sidewalls;
fig. 12 is a schematic structural diagram illustrating the structure after forming a sidewall cap with an air gap on the structure illustrated in fig. 11.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Referring to fig. 12, a first aspect of the present application provides a transistor 100, and specifically, the present application is illustrated by taking a planar gate transistor as an example, but the present application is not limited thereto, and the transistor 100 includes:
a semiconductor substrate 10 having source/drain regions 101 formed thereon, the source/drain regions 101 may have a conductivity different from that of the semiconductor substrate 10. For example, the source/drain regions may have P-type conductivity to form a PMOS transistor. In one embodiment, the source/drain region may include a trivalent impurity element. The source/drain regions may include, for example, boron (B) or indium (In).
The semiconductor substrate 10 may be, for example, a bulk silicon semiconductor substrate, a silicon-on-insulator (SOI) semiconductor substrate, a germanium-on-insulator (GOI) semiconductor substrate, a silicon germanium semiconductor substrate, a III-V group compound semiconductor substrate, or an epitaxial thin film semiconductor substrate obtained by performing Selective Epitaxial Growth (SEG).
When the semiconductor substrate 10 is a silicon-based semiconductor substrate, the semiconductor substrate 10 may include, for example, dangling bonded silicon atoms that are not bonded to oxygen ions. The operating characteristics of the transistor may be stabilized by a hydrogen annealing process by which hydrogen atoms are bonded to dangling-bonded silicon atoms of the semiconductor substrate 10. In this case, the hydrogen atom may be easily separated from the silicon atom, but boron may increase the binding energy between the silicon atom and the hydrogen atom. Thus, the variable retention time or charge retention time of a memory cell (e.g., capacitor CP) in a semiconductor structure may be improved.
The gate stack structure 11 is positioned on the substrate 10, and the source/drain region 101 is positioned at two sides of the gate stack structure 11; the gate stack structure 11 includes a gate oxide layer 111, a polysilicon layer 112, a barrier layer 113, a gate metal layer 114, and a gate mask layer 115, which are stacked from bottom to top. Specifically, the gate oxide layer 111 may be a conventional gate oxide layer such as silicon oxide, silicon oxynitride, or a high-K material such as hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, aluminum oxide, lanthanum oxide, or lanthanum aluminum oxide. The barrier layer 113 is a metal barrier layer, and the materials used for the barrier layer 113 and the gate metal layer 114 include metals such as Ti, TiN, Ta, TaN, TiAl, W, Mo, TaC, Al, Pd, Sc, Au, TiPd, Mo, and the like, or alloys or multi-layer metal stack materials thereof. In addition, it should be noted that, according to actual needs, the material of the gate oxide layer 111 may be selected in a form of a single-layer or multi-layer structure, for example, a composite structure of silicon oxide or silicon oxynitride and a high-K material is adopted, and the gate mask layer 115 may be SiN.
A second interlayer dielectric layer 12 formed on the upper surface of the semiconductor substrate 10 and having a metal contact hole 120 formed therein. The second interlayer dielectric layer 12 can be formed by depositing silicon oxide or spin-coating a layer of insulating dielectric SOD by PECVD, SACVD, LPCVD, HDPCVD or other methods. The second interlevel dielectric layer 12(ILD) material may be doped or undoped silicon oxide, low-k materials including, but not limited to, organic low-k materials (e.g., aryl or multi-ring containing organic polymers), inorganic low-k materials such as amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicone glasses, borosilicate glasses (BSG), phosphosilicate glasses (PSG), borophosphosilicate glasses (BPSG), porous low-k materials (e.g., disiloxatrialkane (SSQ) -based porous low-k materials, porous silicon dioxide, porous SiOCH, C-doped silicon dioxide, F-doped porous amorphous carbon, porous organic polymers). The second interlevel dielectric layer 12(ILD) is formed by depositing silicon oxide using PECVD in this embodiment.
The isolation layer 13 covers the surface of the metal contact hole 120, and the material used for the isolation layer 13 includes SiCN, TiN, TaN, Ta, or Ti, and in particular, in this embodiment, the isolation layer 13 may be SiCN.
And a metal contact plug 14 connected to the source/drain region 101, the metal contact plug 14 filling the metal contact hole 120. Specifically, the second interlayer dielectric layer 12 is located on the sidewall of the metal contact plug 14, and the metal contact plug 14 may be a conductive metal, such as Ti, Al, TiAl, Cu, W, or the like.
And a sidewall 15 located between the gate stack structure 11 and the metal contact plug 14 and covering a sidewall of the gate stack structure 11, wherein the air gap 16 is located in the sidewall 15.
And a cap covering the top of the gate stack structure 11, the cap and the sidewall 15 being integrally formed, the material of the cap and the sidewall 15 being the same as the material of the second interlayer dielectric layer 12, and in this embodiment, both may be selected from silicon oxide.
And the nitride layer 17 is positioned between the isolation layer 13 and the side wall 15, and the nitride layer 17 extends for a certain distance from the surface of the semiconductor substrate 10 along the interface between the isolation layer 13 and the side wall 15. Specifically, the nitride layer 17 is typically formed by PECVD, and has a thickness of 5-50nm, depending on the device requirements. In the present embodiment, silicon nitride is used as the nitride layer 17.
And the offset isolation layer 18 comprises a vertical part and a horizontal part connected with the vertical part, wherein the vertical part is positioned between the side wall of the gate stack structure 11 and the side wall 15, and the horizontal part is positioned between the upper surface of the semiconductor substrate 10 and the bottom end of the side wall 15. Specifically, in the present embodiment, the material of the offset spacers 18 may be selected from SiN.
It is worth mentioning that the dielectric constant of the air in the air gap 16 is about 1, the dielectric constant of the material silicon oxide of the sidewall cap 15 is about 3.9, and the parasitic capacitance between the gate stack structure 11 and the metal contact plug 14 is greatly reduced because the dielectric constant of the air is far smaller than that of the silicon oxide, thereby improving the performance of the transistor.
A method of manufacturing the transistor 100 in the embodiment of the present application is described below.
Fig. 1-12 illustrate cross-sectional views of intermediate stages in the manufacture of a transistor 100 according to some embodiments of the present application. Specifically, the method for manufacturing the transistor 100 includes the following steps:
as shown in fig. 1, a semiconductor substrate 10 is provided, a source/drain region 101 is formed on the semiconductor substrate 10, and the source/drain region 101 may be formed by an ion implantation and diffusion process, in this embodiment, the source/drain region 101 may be formed by ion implantation, and a thermal annealing process may be performed after the ion implantation process is performed to form the source/drain region 101, where the thermal annealing process has a temperature of, for example, 900 ℃ to 1100 ℃. The source/drain region 101 is further activated by the dopant ions in the source/drain region 101, and the dopant ions are diffused to form the source/drain region 101 with more uniform particle distribution, and further ion migration can be driven by the thermal annealing process, so that the dopant ions in the active/drain region 101 are distributed in a descending manner in the direction away from the top surface, and the advantage of having a concentration gradient and the maximum dopant ion concentration being located in the top region of the dopant region is that the concentration difference of the dopant ion concentration between the top region of the source/drain region 101 and other regions contacting with the top of the source/drain region 101 is reduced on the premise of not increasing the total amount of the dopant ions of the source/drain region 101, so that the ion diffusion of high-concentration dopant ions to the low-dopant ion-concentration region due to activation can be reduced in the subsequent thermal annealing treatment process.
The gate oxide layer 111 may be formed on the semiconductor substrate 10 through a high temperature oxidation process, for example, at a temperature of 900 to 1200 ℃. The high temperature oxidation process forms an oxide layer on the surface of the semiconductor substrate 10, which serves as the gate oxide layer 111, and in the present embodiment, the gate oxide layer 111 may include other materials and be formed by other processes, such as a deposition process, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide/nitride/oxide (ONO) layer, or a high-k dielectric layer having a higher dielectric constant than that of the silicon oxide layer. For example, the high-k dielectric layer may have a dielectric constant of about 10 to 25, and may include, for example, hafnium oxide (HfO)2) Aluminum oxide (Al)2O3) Hafnium aluminum oxide (HfAlO)3) Tantalum oxide (Ta)2O3) And/or titanium oxide (TiO)2). In this embodiment, the material of the gate oxide layer 111 may be silicon oxide.
The polysilicon layer 112, the barrier layer 113, the gate metal layer 114 and the gate mask layer 115 may be formed on the gate oxide layer 111 by a Physical Vapor Deposition (PVD) process, a CVD process or other suitable process. Gate oxide layer 111, polysilicon layer 112, barrier layer 113, gate metal layer 114, and gate mask layer 115 constitute gate stack structure 11.
Offset spacers 18 are formed on sidewalls of the gate stack 11 and surfaces of the source/drain regions 101, and a first interlayer dielectric layer 19 is formed on surfaces of the offset spacers 18 and a top surface of the gate stack 11. The first interlayer dielectric layer 19 may be formed by depositing silicon oxide or spin-coating an insulating dielectric SOD layer by PECVD, SACVD, LPCVD or HDPCVD, and the first interlayer dielectric layer 19 may be doped or undoped silicon oxide, low-k materials including but not limited to organic low-k materials (e.g., organic polymers containing aryl or multi-membered rings), inorganic low-k materials such as amorphous carbon nitride (nbn), poly-boro-nitride (pbn), fluoro-silicate glass (fsg), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), porous low-k materials (e.g., disiloxane (SSQ) -based porous low-k materials, porous silicon dioxide, porous SiOCH, C-doped silicon dioxide, F-doped porous amorphous carbon, porous organic polymers). In the present embodiment, the first interlayer dielectric layer 19 is formed by depositing silicon oxide using PECVD.
Next, as shown in fig. 2, a portion of the first interlayer dielectric layer 19 is removed, and a first sidewall of the gate stack structure 11 is formed outside the offset isolation layer 18. The process of removing part of the first interlayer dielectric layer 19 is dry etching.
Next, as shown in fig. 3, an etch stop layer 17 (i.e., a nitride layer 17) is deposited on the surface of the first sidewall and the top surface of the gate stack 11, and is typically formed by PECVD, and the thickness of the etch stop layer is determined according to the device requirements, and is typically 5-50 nm.
Next, as shown in fig. 4, a second interlayer dielectric layer 12 covering the etching stop layer 17 is formed on the semiconductor substrate 10, and the second interlayer dielectric layer 12 may be formed by depositing silicon oxide or spin-coating a layer of insulating dielectric SOD by PECVD, SACVD, LPCVD, HDPCVD, or the like. The second interlevel dielectric layer 12(ILD) material may be doped or undoped silicon oxide, low-k materials including, but not limited to, organic low-k materials (e.g., aryl or multi-ring containing organic polymers), inorganic low-k materials such as amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicone glasses, borosilicate glasses (BSG), phosphosilicate glasses (PSG), borophosphosilicate glasses (BPSG), porous low-k materials (e.g., disiloxatrialkane (SSQ) -based porous low-k materials, porous silicon dioxide, porous SiOCH, C-doped silicon dioxide, F-doped porous amorphous carbon, porous organic polymers). The second interlevel dielectric layer 12(ILD) is formed by depositing silicon oxide using PECVD in this embodiment. Chemical Mechanical Polishing (CMP) is used to planarize the second interlayer dielectric layer 12 (ILD).
Next, as shown in fig. 5, a metal contact area is defined on the source/drain region 101, and a metal contact hole 120 is formed in the second interlayer dielectric layer 12 by an etching process, such that the first sidewall portion with the etch stop layer 17 is located in the metal contact hole 120.
Next, as shown in fig. 6, an isolation layer 13 is deposited in the metal contact hole 120, the isolation layer 13 is at least partially located on the surface of the etching stop layer 17 of the first sidewall, the material of the isolation layer 13 is selected from SiCN, and the process for forming the isolation layer 13 is selected from thermal atomic layer deposition, wherein the deposition temperature is 600-. Thermal type atomic layer deposition is used so that the C concentration in the SiCN is about 20% to prevent the thickness of the spacer layer 13 from being dispersed.
Next, as shown in fig. 7, the isolation layer 13 on the surface of the semiconductor substrate 10 in the metal contact hole 120 is removed, and the sidewall of the isolation layer 13 is remained. The process for removing the isolation layer 13 on the surface of the semiconductor substrate 10 in the metal contact hole 120 is dry etching or physical ion bombardment etching
Next, as shown in fig. 8, the metal contact hole 120 is filled with the metal contact plug 14. Specifically, the metal contact plug 14 may be formed using a metal deposited in the metal contact hole 120.
Next, as shown in fig. 9, the second interlayer dielectric layer 12 above the etching stop layer 17 is removed, and the process of removing the second interlayer dielectric layer 12 above the etching stop layer 17 is wet etching, wherein the wet etching solution is HF.
Next, as shown in fig. 10, a portion of the etch stop layer 17 outside the metal contact hole 120 is removed. The process for removing part of the etching stop layer 17 is wet etching, wherein the wet etching solution is H3PO4。
Next, as shown in fig. 11, the first sidewall is removed to expose the opening 20 between the metal contact plug 14 and the gate stack structure 11; the wet etching process can be adopted, and the wet etching solution is HF
Next, as shown in fig. 12, sidewall material is backfilled in the opening 20 with a low step coverage to form second sidewalls (i.e., the sidewalls 15) including air gaps, and the backfilled material extends to the space above the gate stack 11 to form a cap.
In this embodiment, the process of removing the first sidewall is wet etching, wherein the wet etching solution is HF. The material of the side wall 15 and the cap can be selected from SiO2Formation of SiO2The precursor gas comprises TEOS or SiO4(CH3)4。
It should be noted that the isolation layer 13 is made of SiCN, and since SiCN has a low thickness and good step coverage, it can protect the metal contact plug 14 when the etching stop layer 17 and the sidewall are subsequently removed. Further, SiCN uses H in comparison with SiN3PO4Or the wet etching rate of SiCN by HF solution is slow.
The transistor in this embodiment can be used in DRAM, Flash and Logic, and the capacitor (not shown) coupled in series with the capacitor can be formed by a known manufacturing process to complete the manufacturing of the DRAM.
Further, the DRAM, Flash, and Logic having the capacitor in this embodiment can be used in various chips.
Still further, the chip with the above capacitor may be used in various electronic devices, in particular, smart phones, computers, tablets, wearable smart devices, artificial smart devices, mobile power sources, and the like.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (16)

1. A transistor, comprising:
a substrate having source/drain regions formed thereon;
the gate stack structure is positioned on the substrate;
a metal contact plug connected to the source/drain region;
the side wall is positioned between the gate stack structure and the metal contact plug;
and the air gap is positioned in the side wall.
2. The transistor of claim 1, further comprising:
and the cap is positioned at the top of the gate stack structure, and the cap and the side wall are integrally formed.
3. The transistor of claim 2, further comprising:
and the offset isolation layer comprises a vertical part and a horizontal part connected with the vertical part, wherein the vertical part is positioned between the side wall of the gate stack structure and the side wall, and the horizontal part is positioned between the upper surface of the substrate and the side wall.
4. The transistor of claim 3, further comprising:
an interlayer dielectric layer formed on the substrate;
the isolation layer is positioned on the side wall of the metal contact plug;
and the interlayer dielectric layer is made of the same material as the side wall and the cap.
5. The transistor of claim 4, further comprising:
and the nitride layer is positioned between the isolation layer and the side wall, and extends for a certain distance from the surface of the substrate along the interface between the isolation layer and the side wall.
6. The transistor according to any of claims 1-5, wherein the gate stack structure comprises a gate oxide layer, a polysilicon layer, a barrier layer, a gate metal layer and a gate mask layer which are stacked from bottom to top.
7. A preparation method of a transistor is characterized by comprising the following steps:
providing a substrate;
forming the source/drain region on the substrate;
forming a gate stack structure on the substrate;
forming first side walls on two sides of the gate stack structure;
forming a metal contact hole on the source/drain region;
depositing an isolation layer on the inner wall of the metal contact hole, and filling a metal contact plug;
removing the first side wall;
and backfilling the side wall materials to form second side walls with air gaps on two sides of the gate stack structure.
8. The method of claim 7, wherein an offset isolation layer is formed on a sidewall of the gate stack structure and a surface of the source/drain region, and the first sidewall of the gate stack structure is formed outside the offset isolation layer.
9. The method of claim 8, wherein an etch stop layer is formed on the surface of the first sidewall and the top surface of the gate stack structure, and an interlayer dielectric layer covering the etch stop layer is formed on the substrate.
10. The method of claim 9, wherein the metal contact hole is formed in the interlevel dielectric layer such that the first sidewall portion with the etch stop layer is located within the metal contact hole;
depositing and forming an isolation layer in the metal contact hole, wherein at least part of the isolation layer is positioned on the surface of the etching stop layer of the first side wall;
and removing the isolating layer positioned on the surface of the substrate in the metal contact hole.
11. The method for manufacturing a transistor according to claim 10, wherein the step of removing the first side walls comprises: etching the interlayer dielectric layer above the stop layer; then removing part of the etching stop layer outside the metal contact hole; and removing the first side wall.
12. The method of claim 11, wherein the step coverage is low and the sidewall material is backfilled to form a second sidewall comprising an air gap, and the backfilling material extends to a space above the gate stack structure to form a cap.
13. The method for manufacturing a transistor according to claim 12, wherein the processes of removing the isolation layer on the surface of the substrate in the metal contact hole, removing the interlayer dielectric layer above the etch stop layer, and removing the first sidewall are wet etching, and a wet etching solution is HF.
14. The method for manufacturing a transistor according to claim 13, wherein the processes for removing the etching stop layer outside the metal contact hole are wet etching, and the wet etching solutions are all H3PO4。
15. The method as claimed in claim 14, wherein the material of the isolation layer is SiCN, and the process for forming the isolation layer is selected from thermal atomic layer deposition, wherein the deposition temperature is 600-650 ℃.
16. The method according to claim 12, wherein the second sidewall spacers and the cap are made of a material selected from the group consisting of SiO2Formation of SiO2The precursor gas comprises TEOS or SiO4(CH3)4。
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