CN111897274A - FPGA-based weak signal detection device and method - Google Patents
FPGA-based weak signal detection device and method Download PDFInfo
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Abstract
A FPGA-based weak signal detection device comprises an interferometer, wherein the signal output end of the interferometer is connected with the signal input end of a photoelectric detector, and the signal output end of the photoelectric detector is connected with a phase sensitive detector through an amplifier I and a filter in a signal channel; meanwhile, a signal generator sends out a signal, and the signal is processed by a reference channel and then is connected with a phase sensitive detector; after the phase-sensitive detector calculates the phase shift difference of the two groups of signals, interference signals are eliminated through a low-pass filter, the interference signals are input into the input end of a programmable logic gate array (FPGA) through an amplifier II, synchronous demodulation is completed through a CORDIC algorithm module, and then data are transmitted to an upper computer and a detection system through a communication interface to complete processing of demodulation information; the invention has the advantages of high data processing speed, strong flexibility and universality, high detection precision and convenient operation.
Description
Technical Field
The invention relates to a weak signal detection device, in particular to a weak signal detection device based on an FPGA and a method thereof.
Background
The interferometer is used as a core device for measuring the angular velocity of an object, is mainly used for a carrier motion information perception technology, is a measuring instrument with the characteristics of good autonomy, comprehensive information, real-time continuity, strong anti-interference performance and the like, and is widely used in the aspects of geodetic surveying and the field of earth science.
With the wider application range of interferometer technology, the current signal acquisition and processing aiming at the output of the interferometer are also continuously and rapidly developed, and as an important link of subsequent signal processing, research and development effort is required to be increased in the aspects of detection and processing of weak signals. Through reading relevant documents and reports, the invention based on the aspect of rapidly processing weak signals is relatively lacked at present.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a weak signal detection device based on an FPGA, which can obtain an electric signal convenient to analyze from a weak optical signal measured by an interferometer through a conversion device, and realizes the detection of the weak signal by using a programmable gate array (FPGA) as a core device for weak signal processing.
In order to achieve the purpose, the invention adopts the following technical scheme:
a FPGA-based weak signal detection device comprises an interferometer 1, wherein the signal output end of the interferometer 1 is connected with the signal input end of a photoelectric detector 2, the signal output end of the photoelectric detector 2 is connected with the input end of a signal channel 6, and the output end of the signal channel 6 is connected with the signal input end I of a phase-sensitive detector 8; the signal output end of the signal generator 11 is connected with the signal input end of the reference channel 7, and the signal output end of the reference channel 7 is connected with the signal input end II of the phase-sensitive detector 8; the signal output end of the phase sensitive detector 8 is connected with the signal input end of the low-pass filter 9, the signal output end of the low-pass filter 9 is connected with the signal input end of the programmable logic gate array FPGA12 through an amplifier II10, and the data output end of the programmable logic gate array FPGA12 transmits data to an upper computer and a detection system through a communication interface.
The interferometer 1 is a quadrilateral annular cavity with reflecting mirrors 3 arranged at four corners, and laser beams are reflected and transmitted by the reflecting mirrors 3 in the interferometer 1 to generate beat frequency signals.
The signal channel 6 includes an amplifier I4 and a filter 5 connected in sequence, and amplifies and filters the electric signal of the photodetector 2.
The reference channel 7 is a process of making the signal sent by the signal generator 11 and the signal to be measured output by the signal channel 6 have the same frequency and phase.
A detection method of a weak signal detection device based on an FPGA specifically comprises the following steps:
firstly, starting a device, wherein an interferometer 1 transmits beat frequency signals generated by reflection and transmission of incident laser beams to a signal input end of a photoelectric detector 2;
secondly, the photoelectric detector 2 converts the beat frequency signals in the first step into electric signals and transmits the electric signals to the signal channel 6;
step three, amplifying and filtering the electric signal converted in the step two through a signal channel 6 to obtain a signal to be detected, simultaneously, sending a reference signal by a signal generator 11, synchronously triggering and phase-shifting the reference signal by a reference channel 7, and enabling the reference signal processed by the reference channel 7 and the signal to be detected output by the signal channel 6 to have the same frequency and the same phase;
inputting the signal to be detected and the reference signal in the third step into a phase-sensitive detector 8, detecting the phase between the two signals by using the phase-sensitive detector 8 to obtain the phase difference value of the two beams of signals, eliminating an interference signal through a low-pass filter 9, amplifying, inputting the processed mixing signal into the input end of a programmable logic gate array FPGA12, completing synchronous demodulation by adopting a CORDIC algorithm module, and transmitting data to an upper computer and a detection system through a communication interface to complete the processing of demodulated information.
Step four, the synchronous demodulation is divided into two paths, one path is forward demodulation: the mixed frequency signals are collected through an ADC (analog-to-digital converter) module in the FPGA12, transmitted to a CORDIC1 algorithm module for demodulation, and then transmitted to a PC (personal computer) through a communication serial port by a DAC1 digital-to-analog conversion module for real-time display; one path is reverse demodulation; the mixed frequency signals are acquired through an ADC analog-to-digital conversion module in a programmable gate array FPGA12, transmitted to a CORDIC2 algorithm module for demodulation, then subjected to filtering processing through a low-pass filter 9, amplified, and transmitted to a PC through a communication serial port by a DAC2 analog-to-digital conversion module for real-time display.
The CORDIC1 and CORDIC2 algorithm modules belong to the same module, and the CORDIC1 module is used for generating a sine wave of synchronous forward demodulation, the input angle value (90-0 degrees) of the sine wave is linearly increased, the linearity of the phase is converted into time domain change of a modulation waveform, and the output of the sine waveform is a sine waveform; the CORDIC2 algorithm module realizes cosine wave of reverse synchronous demodulation, the input angle value (-90-0 deg.) is increased linearly, the phase linearity is converted into time domain variation of modulation waveform, the output is cosine waveform, wherein the high frequency component in the signal can be filtered by the low pass filter 9, the output after filtering high frequency is demodulation signal, the synchronous demodulation of the signal is ensured, and the same frequency and phase of the detected signal and the reference signal must be ensured.
The invention has the beneficial effects that:
through the weak signal detection device, a detected signal enters a phase sensitive detector 8(PSD) after being filtered and conditioned by a signal channel 6, meanwhile, a carrier reference signal is synchronously triggered and phase-shifted (same frequency and phase as the detected signal) through a reference channel 7 and is also input to the phase sensitive detector 8 to be mixed with the signal to be detected, and the mixed signal is output to a programmable logic gate array FPGA12 to be processed after being processed by a low pass filter 9(LPF) and conditioned and amplified, so that the processing performance of the detection system can be enhanced, and the precise detection function of the weak signal is realized.
In conclusion, the invention has the advantages of high data processing speed, strong flexibility and universality, high detection precision and convenient operation.
Drawings
FIG. 1 is a schematic view of the structure of the apparatus of the present invention.
FIG. 2 is a schematic diagram of mixed signal processing according to the present invention.
In the figure: 1. an interferometer; 2. a photodetector; 3. a mirror; 4. an amplifier I; 5. a filter; 6. a signal channel; 7. a reference channel; 8. a phase sensitive detector; 9. a low-pass filter; 10. an amplifier II; 11. a signal generator; 12. and a programmable logic gate array FPGA.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, a weak signal detection device based on an FPGA includes an interferometer 1, a signal output end of the interferometer 1 is connected with a signal input end of a photodetector 2, a signal output end of the photodetector 2 is connected with an input end of a signal channel 6, and an output end of the signal channel 6 is connected with a signal input end I of a phase sensitive detector 8; the signal output end of the signal generator 11 is connected with the signal input end of the reference channel 7, and the signal output end of the reference channel 7 is connected with the signal input end II of the phase-sensitive detector 8; the signal output end of the phase sensitive detector 8 is connected with the signal input end of the low-pass filter 9, the signal output end of the low-pass filter 9 is connected with the signal input end of the programmable logic gate array FPGA12 through an amplifier II10, and the data output end of the programmable logic gate array FPGA12 transmits data to an upper computer and a detection system through a communication interface.
The interferometer 1 is a quadrilateral annular cavity with reflecting mirrors 3 arranged at four corners, and laser beams are reflected and transmitted by the reflecting mirrors 3 in the interferometer 1 to generate beat frequency signals.
The signal channel 6 comprises an amplifier I4 and a filter 5 which are connected in sequence, and amplifies and filters the electric signal collected by the photoelectric detector 2.
The reference channel 7 is a process of making the signal sent by the signal generator 11 and the signal to be measured output by the signal channel 6 have the same frequency and phase.
The phase sensitive detector 8 is used for calculating the phase shift difference of the two groups of signals, and the low-pass filter 9 is used for eliminating interference signals.
A detection method of a weak signal detection device based on an FPGA specifically comprises the following steps:
firstly, starting a device, wherein an interferometer 1 transmits beat frequency signals generated by reflection and transmission of incident laser beams to a signal input end of a photoelectric detector 2;
secondly, the photoelectric detector 2 converts the beat frequency signals in the first step into electric signals and transmits the electric signals to the signal channel 6;
step three, amplifying and filtering the electric signal converted in the step two through a signal channel 6 to obtain a signal to be detected, simultaneously, sending a reference signal by a signal generator 11, synchronously triggering and phase-shifting the reference signal by a reference channel 7, and enabling the reference signal processed by the reference channel 7 and the signal to be detected output by the signal channel 6 to have the same frequency and the same phase;
inputting the signal to be detected and the reference signal in the third step into a phase-sensitive detector 8, detecting the phase between the two signals by using the phase-sensitive detector 8 to obtain the phase difference value of the two beams of signals, eliminating an interference signal through a low-pass filter 9, then amplifying, inputting the processed mixing signal into the input end of a programmable logic gate array FPGA12, completing synchronous demodulation by adopting a CORDIC algorithm module, and transmitting data to an upper computer and a detection system through a communication interface to complete the processing of demodulated information.
Step four, the synchronous demodulation is divided into two paths, one path is forward demodulation: the mixed frequency signals are collected through an ADC (analog-to-digital converter) module in the FPGA12, transmitted to a CORDIC1 algorithm module for demodulation, and then transmitted to a PC (personal computer) through a communication serial port by a DAC1 digital-to-analog conversion module for real-time display; one path is reverse demodulation; the mixed frequency signals are acquired through an ADC analog-to-digital conversion module in a programmable gate array FPGA12, transmitted to a CORDIC2 algorithm module for demodulation, then filtered through a low-pass filter 9, amplified by an amplifier II10, and then transmitted to a PC through a communication serial port for real-time display through a DAC2 digital-to-analog conversion module.
The CORDIC1 and CORDIC2 algorithm modules belong to the same module, the CORDIC1 module is used for producing sine waves of synchronous forward demodulation, the input angle value (90-0 degrees) of the sine waves is linearly increased, the linearity of the phase is converted into time domain change of modulation waveforms, and the output of the sine waves is sine waveforms; the CORDIC2 algorithm module realizes cosine waves of reverse synchronous demodulation, the input angle value (-90-0 ℃) of the cosine waves is increased linearly, the phase linearity is converted into time domain change of modulation waveforms, the time domain change is output as cosine waveforms, high-frequency components in the signals can be filtered through an LPF, and the output after the high frequency is filtered is demodulation signals.
The working principle of the invention is as follows:
beat frequency signals of two laser beams can be obtained through an interferometer 1, the beat frequency signals are connected with a photoelectric detector 2 through transmission, the photoelectric detector 2 converts optical signals into electric signals, a signal channel 6 amplifies and filters the converted electric signals and provides reference signals at the same time, a signal to be detected and the reference signals are input into a phase sensitive detector 8(PSD), the phase between the two signals is detected by the phase sensitive detector 8(PSD), the phase difference value of the two signals can be obtained, the two signals are connected into a low pass filter 9(LPF), interference signals are eliminated and then amplified, the processed signals are input into an input end of a programmable logic gate array FPGA12, a CORDIC algorithm module is adopted, after synchronous demodulation is completed, a communication interface realizes data transmission of an upper computer and a detection system, processing of demodulation information is completed, and therefore accuracy of weak signal detection is guaranteed.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that are not thought of through the inventive work should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope defined by the claims.
Claims (7)
1. The utility model provides a weak signal detection device based on FPGA, includes interferometer (1), its characterized in that: the signal output end of the interferometer (1) is connected with the signal input end of the photoelectric detector (2), the signal output end of the photoelectric detector (2) is connected with the input end of a signal channel (6), and the output end of the signal channel (6) is connected with the signal input end I of the phase-sensitive detector (8); the signal output end of the signal generator (11) is connected with the signal input end of the reference channel (7), and the signal output end of the reference channel (7) is connected with the signal input end II of the phase-sensitive detector (8); the signal output end of the phase sensitive detector (8) is connected with the signal input end of the low-pass filter (9), the signal output end of the low-pass filter (9) is connected with the signal input end of the programmable logic gate array FPGA (12) through the amplifier II (10), and the data output end of the programmable logic gate array FPGA (12) transmits data to the upper computer and the detection system through the communication interface.
2. The FPGA-based weak signal detection device of claim 1, wherein: the interferometer (1) is a quadrilateral annular cavity with reflecting mirrors (3) arranged at four corners, and laser beams are reflected and transmitted by the reflecting mirrors (3) in the interferometer (1) to generate beat frequency signals.
3. The FPGA-based weak signal detection device of claim 1, wherein: the signal channel (6) comprises an amplifier I (4) and a filter (5) which are connected in sequence, and the electric signals collected by the photoelectric detector (2) are amplified and filtered.
4. The FPGA-based weak signal detection device of claim 1, wherein: the reference channel (7) is a process of enabling the signal sent by the signal generator (11) and the signal to be detected output by the signal channel (6) to be in the same frequency and phase.
5. A detection method of a weak signal detection device based on FPGA is characterized in that: the method specifically comprises the following steps:
firstly, starting a device, wherein an interferometer (1) reflects and transmits beat frequency signals generated by incident laser beams to a signal input end of a photoelectric detector (2);
secondly, the photoelectric detector (2) converts the beat frequency signals in the first step into electric signals and transmits the electric signals to a signal channel (6);
step three, amplifying and filtering the electric signal converted in the step two into a signal to be detected through a signal channel (6), simultaneously, sending a reference signal by a signal generator (11), synchronously triggering and phase-shifting the reference signal by a reference channel (7), and enabling the reference signal processed by the reference channel (7) and the signal to be detected output by the signal channel (6) to have the same frequency and the same phase;
inputting the signal to be detected and the reference signal in the third step into a phase-sensitive detector (8), detecting the phase between the two signals by using the phase-sensitive detector (8) to obtain the phase difference value of the two beams of signals, eliminating an interference signal through a low-pass filter (9), amplifying, inputting the processed mixing signal into the input end of a programmable logic gate array (FPGA) (12), completing synchronous demodulation by adopting a CORDIC algorithm module, and transmitting data to an upper computer and a detection system through a communication interface to complete the processing of demodulated information.
6. The detection method of the FPGA-based weak signal detection device according to claim 5, characterized in that: step four, the synchronous demodulation is divided into two paths, one path is forward demodulation: the mixed frequency signals are collected through an ADC analog-to-digital conversion module in a programmable gate array FPGA (12), transmitted to a CORDIC1 algorithm module for demodulation, and then transmitted to a PC (personal computer) for real-time display through a communication serial port by a DAC1 analog-to-digital conversion module; one path is reverse demodulation; the frequency mixing signals are acquired through an ADC analog-to-digital conversion module in a programmable gate array FPGA (12), transmitted to a CORDIC2 algorithm module for demodulation, then subjected to filtering through a low-pass filter (9), amplified by an amplifier II (10), and then transmitted to a PC (personal computer) through a communication serial port through a DAC2 digital-to-analog conversion module for real-time display.
7. The detection method of the FPGA-based weak signal detection device according to claim 6, characterized in that: the CORDIC1 and CORDIC2 algorithm modules belong to the same module, the CORDIC1 module is used for producing sine waves of synchronous forward demodulation, the input angle value (90-0 degrees) of the sine waves is linearly increased, the linearity of the phase is converted into time domain change of modulation waveforms, and the output of the sine waves is sine waveforms; the CORDIC2 algorithm module realizes cosine waves of reverse synchronous demodulation, the input angle value (-90-0 ℃) of the cosine waves is increased linearly, the phase linearity is converted into time domain change of modulation waveforms, the time domain change is output as cosine waveforms, high-frequency components in the signals can be filtered through an LPF, and the output after the high frequency is filtered is demodulation signals.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117914309A (en) * | 2024-03-19 | 2024-04-19 | 成都中微达信科技有限公司 | Molecular clock, molecular clock frequency control method and electronic equipment |
| CN117914308A (en) * | 2024-03-19 | 2024-04-19 | 成都中微达信科技有限公司 | Molecular clock device, molecular clock frequency control method and electronic equipment |
| CN117914308B (en) * | 2024-03-19 | 2024-05-31 | 成都中微达信科技有限公司 | Molecular clock device, molecular clock frequency control method and electronic equipment |
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