CN111896865A - Fault position detection method for signal acquisition system - Google Patents
Fault position detection method for signal acquisition system Download PDFInfo
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- CN111896865A CN111896865A CN202010748971.XA CN202010748971A CN111896865A CN 111896865 A CN111896865 A CN 111896865A CN 202010748971 A CN202010748971 A CN 202010748971A CN 111896865 A CN111896865 A CN 111896865A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
- G01R31/31711—Evaluation methods, e.g. shmoo plots
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31932—Comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
- G01R31/31935—Storing data, e.g. failure memory
Abstract
The invention relates to a method for detecting a fault part of a signal acquisition system, which solves the problems of automatic judgment and positioning of hardware faults of the acquisition system. The signal acquisition system comprises a plurality of parts such as an AD chip, a programmable gate array FPGA, a storage chip, a DSP digital signal processing chip, an upper computer and the like. The high resolution, e.g., 24 bit AD chip, can observe the noise floor of the circuit (noise generated by the chip itself). This makes the low order of the high resolution AD acquisition system fluctuate with noise under normal operation of the acquisition system. The last bit fluctuation is stopped because the failure of the acquisition system can cause the stagnation of the output data updating. Based on the random fluctuation characteristic of the low-order binary code of the 24-bit AD conversion chip, the invention provides an automatic judgment and positioning method for hardware faults of an acquisition system by utilizing multiple codes and data analysis by taking a 24-bit acquisition card as a blue book.
Description
Technical Field
The invention relates to the fields of high-precision data acquisition, signal acquisition system fault detection and the like.
Background
The signal acquisition system is generally composed of a plurality of parts, such as an AD chip (for realizing sampling-quantization-coding), a programmable gate array FPGA (serving as a sampling logic control module), a storage chip, a DSP digital signal processing chip, an upper computer and the like. This makes the data acquisition circuit often the structure complicated, and the chip variety that uses is various, therefore in the debugging process of circuit, when breaking down, it is difficult only based on output signal characteristic, judges the type and the position of trouble. High resolution AD (such as 24 bit AD chip) can observe the background noise of the circuit (the noise generated by the chip and other devices). This makes the low order of the high resolution AD acquisition system fluctuate with noise under normal operation of the acquisition system. The last bit fluctuation is stopped because the failure of the acquisition system can cause the stagnation of the output data updating.
The data acquisition circuit is often complicated in structure, and the chip variety that uses is various, therefore in the debugging process of circuit, when breaking down, it is difficult only based on output signal characteristic, judge the type and the position of trouble. Due to the high resolution AD (such as 24 bit AD chip), the background noise of the circuit (the noise generated by the chip and other devices) can be observed. This makes the low order of the high resolution AD acquisition system fluctuate with noise under normal operation of the acquisition system. The last bit fluctuation is stopped because the failure of the acquisition system can cause the stagnation of the output data updating. Based on the random fluctuation characteristic of the low-bit binary code of the high-precision AD conversion chip, the invention provides an automatic judgment and positioning method for hardware faults of an acquisition system by utilizing multiple codes and data analysis by taking a 24-bit acquisition card as a blue book.
Disclosure of Invention
The invention aims to provide a signal acquisition system fault part detection method for accurately determining a fault part of an acquisition system.
The invention is realized by the following steps:
comprises a signal acquisition processing system, an analog-to-digital conversion circuit AD, a programmable logic gate array FPGA, a plurality of storage processing subsystems, an upper computer and a USB interface chip, wherein the storage processing subsystems consist of a switch chip, a digital signal processing chip DSP and a static random access memory SRAM,
the method comprises the following specific steps:
1) the upper computer sends an acquisition instruction to the USB interface chip:
the upper computer sets the enabling control end CS and the read-write control end R/W of the USB interface chip to be in an effective state and a write state respectively, sends an acquisition instruction to the USB chip through the USB bus,
2) the USB interface chip transmits an acquisition instruction to the digital signal processing chip DSP:
after the digital signal processing chip USB obtains an acquisition instruction sent by an upper computer, the enable control end CS and the read-write control end R/W of the DSP are respectively set to be in an effective state and a write state, the acquisition instruction is written into the DSP through the SPI bus and the interface chip USB,
3) the DSP chip transmits an acquisition instruction to the FPGA:
after the DSP obtains a signal acquisition instruction sent by the USB chip, the FPGA enabling control end CS and the read-write control end R/W are set to be in an effective state and a write state respectively. The DSP writes the instruction into the FPGA through a universal asynchronous transmission bus UART;
4) the FPGA controls the AD chip to collect data:
the FPGA sets the enabling control end CS and the read/write control end R/W of the AD chip to be in an effective state and a write state respectively, the data ready indication end DRDY is in an ineffective state at the initial moment, after the port configuration is completed, the FPGA writes a control signal into the AD chip through sixteen-way bidirectional parallel port data lines D [0:15], controls the AD chip to start sampling,
5) data acquisition by the AD chip:
the AD chip is responsible for signal acquisition, quantization and coding after acquiring an acquisition instruction, when the AD chip completes data conversion once, the DRDY pin is set to be in an effective state and continues for a period to inform the FPGA that data is ready to wait for reading,
6) the FPGA reads data from the AD chip:
when the DRDY pin of the FPGA is set to be in an effective state, the FPGA sets the AD chip enable terminal CS and the read/write control terminal R/W to be in an effective state and a read state respectively, at the moment, the AD chip writes the acquired data into an internal register of the FPGA through sixteen-way bidirectional parallel port data lines D [0:15],
7) repeating the steps (4) to (6), sequentially collecting a plurality of groups of data,
8) judging whether the function of the AD chip is normal:
the FPGA compares whether the last two bits of the binary codes of the plurality of groups of data are completely the same, if so, the AD chip of the system is in failure, the step (9) is carried out, otherwise, the AD chip is in normal function, the step (12) is carried out,
9) the FPGA sends an AD chip fault code to the DSP,
10) after the DSP obtains the fault code, the DSP does not perform digital signal processing on the group of data, meanwhile, the DSP transmits the error code to an upper computer through a USB chip,
11) the upper computer displays the fault information after obtaining the fault code, and sets the RESET end of the AD chip to be in an effective state so as to restart the AD chip,
12) the FPGA writes 100 groups of data into the SRAM of the memory chip.
13) Judging whether the FPGA function is normal:
the DSP reads the group of data stored in the step (12) from the SRAM and compares whether the last two binary codes of the data are completely the same or not, if yes, the FPGA of the system is in failure, the step (14) is carried out, otherwise, the FPGA is in normal function, the step (16) is carried out,
14) the DSP does not perform digital signal processing on the group of data any more; meanwhile, the DSP sends the FPGA fault code to an upper computer,
15) the upper computer displays the error information after obtaining the fault code and restarts the FPGA chip,
16) the DSP performs digital signal processing on the plurality of groups of data and sends the processed data to an upper computer through a USB chip,
17) whether the DSP function is normal or not is judged,
the upper computer compares whether the last two bits of the binary code of the group of data transmitted from the DSP are completely the same or not, if so, the DSP chip of the system can be judged to have a fault, and the step (18) is carried out; otherwise, the DSP function is normal, go to step (19),
18) the upper computer sends out a DSP error code prompt and restarts the DSP chip,
19) the upper computer sends out the information that the detection system is normal in function.
The signal acquisition and processing system is characterized in that a signal to be detected is connected with an input end of a programmable logic gate array (FPGA) through a single-ended to differential circuit and an analog-to-digital conversion circuit (AD), the AD adopts 24 bits, the output of the FPGA is connected with a storage processing subsystem, the storage processing subsystem consists of a switch chip, a digital signal processing chip (DSP) and a Static Random Access Memory (SRAM), the signal to be detected is converted into a differential signal through the single-ended to differential circuit, the analog-to-digital conversion circuit (AD) converts the differential signal into a digital signal and then transmits the digital signal to the FPGA, when the potential of a control line pin on the switch chip of the storage processing subsystem is pulled low, the FPGA transmits data to the SRAM of the storage processing subsystem, and when the potential of a control line pin is pulled high, the digital signal processing chip (DSP) reads, after the DSP finishes processing data, the data is transmitted to an upper computer for display, an analog-to-digital conversion circuit and a programmable logic gate array FPGA are provided with 16-bit data lines and RESET, SYNC, CS, RD/WR, DRDY and MCLK control lines are connected, MCLK provides clock signals for AD, the falling edge of the RESET pin enables an internal digital circuit to RESET, SYNC enables an internal filter to RESET, DRDY can generate a low-level effective pulse each time new conversion data exists, a chip selection pin CS is matched with RD/WR for use, and when CS is at a low level and RD/WR is at a low level, reading operation occurs; the FPGA is connected with a switch chip in each storage processing subsystem through 5 lines, the FPGA comprises a serial peripheral interface SP and a control line, the CLK, the CS, the SDI, the SDO and the CS of the serial peripheral interface SP generate a device enable signal, the CLK provides a clock pulse, the SDI and the SDO finish data transmission based on the pulse, the switch chip is connected with the SRAM in the storage processing subsystem through an SPI interface line, the DSP and the FPGA transmit an instruction through a universal asynchronous receiver transmitter UART, the DSP is connected with the switch chip of the internal storage processing subsystem through the SPI interface line and connected with a universal serial bus USB outside the storage processing subsystem through the SPI interface line, the USB chip is connected with an upper computer through the universal serial bus USB bus to judge whether the last bits of the acquired data are completely the same or not, the system failure site can be detected.
The invention has the following advantages:
when the signal acquisition system breaks down, the fault part can be quickly judged directly according to the characteristics of the output signal.
Drawings
FIG. 1 is a block diagram of a data acquisition system.
FIG. 2 is a diagram of the connection structure of the AD module and the FPGA.
FIG. 3 is a diagram of the connection between the FPGA and the storage processing subsystem.
Detailed Description
A signal acquisition system fault position detection method, an acquisition processing system, a signal to be detected is connected with the input end of a programmable logic gate array FPGA through a single-end to differential circuit and an analog-to-digital conversion circuit AD, the analog-to-digital conversion circuit AD adopts 24 bits, the output of the programmable logic gate array is connected with a storage processing subsystem, the storage processing subsystem is composed of a switch chip, a digital signal processing chip DSP and a static random access memory SRAM, the signal to be detected is converted into a differential signal through the single-end to differential circuit, the analog-to-digital conversion circuit AD converts the differential signal into a digital signal and then transmits the digital signal to the programmable logic gate array FPGA, when the potential of a control line pin on the switch chip of the storage processing subsystem is pulled down, the FPGA transmits data to the static random access memory SRAM of the storage processing subsystem, when the potential of the control line pin is pulled up, the, after the DSP finishes processing data, the data is transmitted to an upper computer for display, an analog-to-digital conversion circuit and a programmable logic gate array FPGA are provided with 16-bit data lines and RESET, SYNC, CS, RD/WR, DRDY and MCLK control lines are connected, MCLK provides clock signals for AD, the falling edge of the RESET pin enables an internal digital circuit to RESET, SYNC enables an internal filter to RESET, DRDY can generate a low-level effective pulse each time new conversion data exists, a chip selection pin CS is matched with RD/WR for use, and when CS is at a low level and RD/WR is at a low level, reading operation occurs; the FPGA is connected with a switch chip in the storage processing subsystem through 5 lines, the FPGA comprises a serial peripheral interface SP and a control line, the CLK, the CS, the SDI, the SDO and the CS of the serial peripheral interface SP generate a device enable signal, the CLK provides clock pulse, the SDI and the SDO complete data transmission based on the pulse, the control line, the switch chip is connected with the SRAM in the storage processing subsystem through an SPI interface line, the DSP and the FPGA transmit instructions through a universal asynchronous receiver transmitter UART, the DSP is connected with the switch chip of the internal storage processing subsystem through the SPI interface line and connected with a universal serial chip USB outside the storage processing subsystem through the SPI interface line, the USB chip is connected with an upper computer through the universal serial bus USB bus to judge whether the last several bits of the 100 groups of data are completely the same or not, then the fault position of the system can be detected, and the specific steps are as follows:
(1) the upper computer sends an acquisition instruction to the USB interface chip:
the upper computer sets the USB interface chip enable control end CS and the read-write control end R/W to be in an effective state and a write state respectively. Through the USB bus, the host computer sends a capture command (e.g., 11111111) to the USB chip.
(2) The USB interface chip transmits an acquisition instruction to the DSP chip:
after the USB interface chip obtains an acquisition instruction sent by the upper computer, the DSP chip enable control end CS and the read-write control end R/W are respectively set to be in an effective state and a write state. The USB chip writes the acquisition instruction into the DSP through the SPI bus;
(3) the DSP chip transmits an acquisition instruction to the FPGA:
after the DSP obtains a signal acquisition instruction sent by the USB chip, the FPGA enabling control end CS and the read-write control end R/W are set to be in an effective state and a write state respectively. The DSP writes the instruction into the FPGA through a universal asynchronous transmission bus UART;
(4) the FPGA controls the AD chip to collect data:
the FPGA sets the AD chip enable control end CS and the read/write control end R/W to be in an effective state and a write state respectively. At the initial moment, the data ready indication terminal DRDY is in an invalid state. After the port configuration is completed, through sixteen paths of bidirectional parallel port data lines D [0:15], the FPGA writes a control signal into the AD chip and controls the AD chip to start sampling.
(5) Data acquisition by the AD chip:
and after the AD chip obtains the acquisition instruction, the AD chip is responsible for signal acquisition, quantization and coding. And after the AD chip completes one-time data conversion, the DRDY pin is set to be in an effective state and continues for one period to inform the FPGA that the data is ready and waits for reading.
(6) The FPGA reads data from the AD chip:
and when the DRDY pin is set to be in an effective state, the FPGA sets the AD chip enabling terminal CS and the read/write control terminal R/W to be in an effective state and a read state respectively. At this time, the AD chip writes the acquired 100 groups of data into the FPGA internal register through sixteen-way bidirectional parallel port data lines D [0:15 ].
(7) And (5) repeating the steps (4) to (6) and sequentially collecting 100 groups of data.
(8) Judging whether the function of the AD chip is normal:
the FPGA compares whether the last two bits of the binary codes of the 100 groups of data are identical or not. If yes, the AD chip of the system is judged to be in fault, and the step (9) is carried out; otherwise, the AD chip is normal in function, and the step (12) is carried out.
(9) The FPGA sends an AD chip fault code (e.g., 00000100) to the DSP.
(10) After the DSP obtains the fault code, the digital signal processing is not carried out on the 100 groups of data; meanwhile, the error code is transmitted to the upper computer by the DSP through the USB chip.
(11) And the upper computer displays the fault information after obtaining the fault code and sets the RESET end of the AD chip to be in an effective state so as to restart the AD chip.
(12) The FPGA writes the 100 groups of data into the SRAM of the memory chip.
(13) Judging whether the FPGA function is normal:
and (3) the DSP reads the 100 groups of data stored in the step (12) from the SRAM and compares whether the last two bits of binary codes of the data are completely the same or not. If yes, indicating that the FPGA of the system has a fault, and turning to the step (14); otherwise, the FPGA is normal in function, and the step (16) is carried out.
(14) The DSP does not perform digital signal processing on the 100 groups of data any more; meanwhile, the DSP sends an FPGA fault code (for example 00000010) to the upper computer.
(15) And the upper computer displays the error information after obtaining the fault code and restarts the FPGA chip.
(16) The DSP performs digital signal processing on the 100 groups of data and sends the processed data to an upper computer through a USB chip.
(17) Judging whether the DSP function is normal:
the upper computer compares whether the last two bits of the binary codes of the 100 groups of data transmitted from the DSP are completely the same or not. If yes, judging that the DSP chip of the system has a fault, and turning to the step (18); otherwise, the DSP functions normally, and the step (19) is carried out.
(18) The upper computer sends out a DSP error code (for example 00000001) prompt and restarts the DSP chip;
(19) the upper computer sends out the information that the detection system is normal in function.
Claims (2)
1. The method for detecting the fault part of the signal acquisition system is characterized by comprising a signal acquisition processing system, an analog-to-digital conversion circuit AD, a programmable logic gate array FPGA, a plurality of storage processing subsystems, an upper computer and a USB interface chip, wherein the storage processing subsystems consist of a switch chip, a digital signal processing chip DSP and a static random access memory SRAM,
the method comprises the following specific steps:
(1) the upper computer sends an acquisition instruction to the USB interface chip:
the upper computer sets the enabling control end CS and the read-write control end R/W of the USB interface chip to be in an effective state and a write state respectively, sends an acquisition instruction to the USB chip through the USB bus,
(2) the USB interface chip transmits an acquisition instruction to the digital signal processing chip DSP:
after the digital signal processing chip USB obtains an acquisition instruction sent by an upper computer, the enable control end CS and the read-write control end R/W of the DSP are respectively set to be in an effective state and a write state, the acquisition instruction is written into the DSP through the SPI bus and the interface chip USB,
(3) the DSP chip transmits an acquisition instruction to the FPGA:
after the DSP obtains a signal acquisition instruction sent by the USB chip, the FPGA enabling control end CS and the read-write control end R/W are respectively set to be in an effective state and a write state, and the DSP writes the instruction into the FPGA through a universal asynchronous transmission bus UART;
(4) the FPGA controls the AD chip to collect data:
the FPGA sets the enabling control end CS and the read/write control end R/W of the AD chip to be in an effective state and a write state respectively, the data ready indication end DRDY is in an ineffective state at the initial moment, after the port configuration is completed, the FPGA writes a control signal into the AD chip through sixteen-way bidirectional parallel port data lines D [0:15], controls the AD chip to start sampling,
(5) data acquisition by the AD chip:
the AD chip is responsible for signal acquisition, quantization and coding after acquiring an acquisition instruction, when the AD chip completes data conversion once, the DRDY pin is set to be in an effective state and continues for a period to inform the FPGA that data is ready to wait for reading,
(6) the FPGA reads data from the AD chip:
when the DRDY pin of the FPGA is set to be in an effective state, the FPGA sets the AD chip enable terminal CS and the read/write control terminal R/W to be in an effective state and a read state respectively, at the moment, the AD chip writes the acquired data into an internal register of the FPGA through sixteen-way bidirectional parallel port data lines D [0:15],
(7) repeating the steps (4) to (6), sequentially collecting a plurality of groups of data,
(8) judging whether the function of the AD chip is normal:
the FPGA compares whether the last two bits of the binary codes of the plurality of groups of data are completely the same, if so, the AD chip of the system is in failure, the step (9) is carried out, otherwise, the AD chip is in normal function, the step (12) is carried out,
(9) the FPGA sends an AD chip fault code to the DSP,
(10) after the DSP obtains the fault code, the DSP does not perform digital signal processing on the group of data, meanwhile, the DSP transmits the error code to an upper computer through a USB chip,
(11) the upper computer displays the fault information after obtaining the fault code, and sets the RESET end of the AD chip to be in an effective state so as to restart the AD chip,
(12) the FPGA writes the group of data into the SRAM of the memory chip,
(13) judging whether the FPGA function is normal:
the DSP reads the group of data stored in the step (12) from the SRAM and compares whether the last two binary codes of the data are completely the same or not, if yes, the FPGA of the system is in failure, the step (14) is carried out, otherwise, the FPGA is in normal function, the step (16) is carried out,
(14) the DSP does not perform digital signal processing on the data; meanwhile, the DSP sends the FPGA fault code to an upper computer,
(15) the upper computer displays the error information after obtaining the fault code and restarts the FPGA chip,
(16) the DSP performs digital signal processing on the plurality of groups of data and sends the processed data to an upper computer through a USB chip,
(17) judging whether the DSP function is normal:
the upper computer compares whether the last two bits of the binary code of the group of data transmitted from the DSP are completely the same or not, if so, the DSP chip of the system can be judged to have a fault, and the step (18) is carried out; otherwise, the DSP function is normal, go to step (19),
(18) the upper computer sends out a DSP error code prompt and restarts the DSP chip,
(19) the upper computer sends out the information that the detection system is normal in function.
2. The method according to claim 1, wherein the signal acquisition processing system, the signal to be tested is connected to the input terminal of the FPGA through the single-ended to differential circuit and the AD circuit, the AD circuit has 24 bits, the output terminal of the FPGA is connected to the storage processing subsystem, the storage processing subsystem is composed of a switch chip, a DSP chip and a SRAM, the signal to be tested is converted into a differential signal through the single-ended to differential circuit, the AD circuit converts the differential signal into a digital signal and transmits the digital signal to the FPGA, when the potential of the control line pin on the switch chip of the storage processing subsystem is pulled low, the FPGA transmits data to the SRAM of the storage processing subsystem, when the potential of the control line pin is pulled high, the DSP chip reads and processes data from the SRAM, and is connected with a 16-bit data line of the FPGA and a RESET, SYNC, CS, RD/WR, DRDY and MCLK control line, the MCLK provides a clock signal for the AD, the falling edge of the RESET pin RESETs an internal digital circuit, the SYNC RESETs an internal filter, the DRDY generates a low-level effective pulse each time new conversion data is provided, the chip selection pin CS is matched with the RD/WR for use, and when the CS is at a low level and the RD/WR is at a low level, reading operation occurs; the FPGA is connected with a switch chip in each storage processing subsystem through 5 lines, the FPGA comprises a serial peripheral interface SP and a control line, the CLK, the CS, the SDI, the SDO and the CS of the serial peripheral interface SP generate a device enable signal, the CLK provides a clock pulse, the SDI and the SDO finish data transmission based on the pulse, the switch chip is connected with the SRAM in the storage processing subsystem through an SPI interface line, the DSP and the FPGA transmit an instruction through a universal asynchronous receiver transmitter UART, the DSP is connected with the switch chip of the internal storage processing subsystem through the SPI interface line and connected with a universal serial bus USB outside the storage processing subsystem through the SPI interface line, the USB chip is connected with an upper computer through the universal serial bus USB bus to judge whether the last bits of the acquired data are completely the same or not, the system failure site can be detected.
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