CN111885300B

CN111885300B - Control circuit and control method for industrial camera system time sequence

Info

Publication number: CN111885300B
Application number: CN202010589066.4A
Authority: CN
Inventors: 主宾; 汪雪林; 余章卫
Original assignee: Suzhou Zhongke Whole Elephant Intelligent Technology Co ltd
Current assignee: Suzhou Zhongke Whole Elephant Intelligent Technology Co ltd
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2021-07-30
Anticipated expiration: 2040-06-24
Also published as: CN111885300A

Abstract

The invention discloses a control circuit and a control method of an industrial camera system time sequence, which belong to the technical field of high-speed industrial cameras.

Description

Control circuit and control method for industrial camera system time sequence

Technical Field

The invention belongs to the technical field of high-speed industrial cameras, and particularly relates to a control circuit and a control method for a time sequence of an industrial camera system.

Background

The application scenarios of the industrial camera have high requirements on the environment, such as large difference between high and low temperatures, complex magnetic field change, severe vibration, etc., which can affect the service life of the industrial camera to a certain extent, and thus engineers face huge challenges in order to ensure stable operation and long service life of industrial equipment. Generally, once an industrial device is started, it is required to continuously operate without a failure. It should be noted that the industrial camera is only a fuzzy name for the image capturing and processing capability of the camera itself, and the industrial camera is different from a normal high-speed industrial camera in industrial application, and has core processing chips such as an ARM, an FPGA and the like, and the corresponding core processing chips and various application chips are matched to have very strict requirements on time sequence, and after the time sequence is used for system startup, the system can be ensured to normally load an image processing algorithm and logic operation, and also used for power-on time sequence and logic control of the chips.

In the past, the ARM, the FPGA and various chips of the system are powered on by adopting hardware, and logic software is not additionally adopted for intervention control. For industrial equipment, repeated power-on and power-off of a system is a normal state. If the time sequence of the system is controlled only by the hardware, the method is feasible under the condition of low requirement on industrial equipment. However, for industrial and above demanding times, the normal operation or shutdown of the system may be temporary, as there is no extensive experimental verification: even if the power-on sequence of the system is wrong, the system can still reliably work without any risk. In industrial or more demanding application scenarios, the requirements for use are more stringent, and operations that do not meet the requirements of the chip mean that the risk is huge, and may also be irreversible, and the device state cannot work continuously, and does not meet the actual application requirements. Except for the power-on core chip and part of power-on sequence required by the chip which is designed and collocated, the power-off is also strictly required: if the power is turned off only by the characteristics of hardware, a switch inside an IC is sometimes turned on or off at the same time, large current is generated inside a chip instantly, and repeated occurrence can cause partial or all damage of the chip, thereby bringing great trouble to the maintenance of industrial equipment.

Therefore, how to better control the system timing of the industrial camera, extend the lifetime of the industrial equipment, and improve the reliability of the industrial equipment is a main problem to be solved at present. The time sequence control of the system is realized only by adopting hardware, and the method has the defects of self and low precision; but also has the advantages of low hardware design cost, simple software and hardware design and convenient maintenance. The software and hardware combined control mode can realize the high-reliability life cycle of the equipment with relatively low cost.

Chinese patent application CN201210328916.0 (a method for implementing system timing control based on CPLD), during the startup process of the system, 1) judges whether the preceding stage state is ok according to the Power, enable signals and time delay of the system, and in the hardware connection of the CPLD, the signals of various Powerready include: VTTPwrwood of CPU, Pwrwood of VSA, Pwrwood of Vcore; core electricity Pwrwood of PCH; the signals for each Reset are connected to: RST _ IBMC _ NIC _ N, RST _ PERST0_ N, RST _ LVC3_ CPU1_ RESET _ N, RST _ PERST1_ N; 2) in the program modules of the CPLD, the program names and the functional relationships of the respective modules are defined first, the execution sequence first obtains the corresponding program module title from the file of the Rom _ PLD _ top, and in the modules of the sub-program, the program content of the corresponding Rom _ PLD _ vr _ control or the corresponding Timer function is called according to the function names. In the method, the power-on and power-off logic control of the system is realized by using software, and the requirement on corresponding hardware equipment is high, so that the application occasion is limited. The invention patent application CN201910150766.0 (a method and a device for upgrading a CPLD) in China adopts a CPLD system and utilizes GPIO to realize system time sequence control, and the method is direct and simple. The GPIO is controlled in a software mode, and the GPIO of the CPLD directly controls an enabling pin of the power supply chip. Such an approach may cause some unpredictable problems: in practical experiments, it is found that the state of the GPIO is often uncontrollable during the period when the external power supply is connected to the CPLD to operate formally, sometimes a glitch occurs, sometimes a high level occurs, sometimes a pulse occurs, and so on. Uncontrollable factors cause the next-stage chip to suddenly work and stop working, and the system time sequence is abnormal. In the chinese patent application CN102065246A (an integrated timing control system for CCD camera), a system control module is connected to a timing module, the system control module is responsible for scheduling and controlling the timing control system, the timing module is used for generating CCD driving signals, video processing signals, image frame header data and chip selection signals, a central processing unit with high radiation resistance and a logic device of the timing module are adopted, and software adopts a fault-tolerant design, so that the safety and reliability are high when in use. However, the system mainly depends on and selects a Q-grade processor (80C32E) of ATMEL company and a Q-grade FPGA (A54SX32A) of ACTEL company, and the two core devices have high manufacturing cost, so that the industrial application cost of the system is greatly increased. It can be seen that the methods in the above two patents have high requirements on hardware devices when applied to system timing control, and have large application limitations in actual industrial production.

In addition, since the sale of industrial equipment is now applied to various scenes. The matching of hardware devices and software from different brands is very easy to generate the problem that the use sequence of each application module needs to be matched. If the occurrence of such things can be reduced or the current trouble can be adapted by using a general method, so that the industrial equipment is applied in a foolproof manner, the friendliness between operators and the equipment can be greatly improved.

Disclosure of Invention

The invention aims to solve the technical problems that in the time sequence control of an industrial camera system in the prior art, the existing time sequence control method has higher requirements on hardware equipment, has not wide applicability, has certain difficulty in operation and the like.

In order to solve the technical problem, the invention discloses a control circuit of the time sequence of an industrial camera system, which comprises an energy storage circuit and a power-on time sequence control circuit, wherein the input end of the energy storage circuit is connected with an input power supply, the output end of the energy storage circuit is connected with the input end of the power-on time sequence control circuit, and the output end of the power-on time sequence control circuit is connected with the input end of the industrial camera system; the energy storage circuit comprises a super capacitor; the power-on sequence control circuit comprises a programmable logic device CPLD serving as a sequence control chip, wherein the CPLD is a programmable logic device and mainly comprises a logic block, a programmable interconnection channel and an I/O block, wherein the I/O block is a module formed by input/output ports, and a plurality of General programmable input/output ports, namely GPIO (General-Purpose IO ports), are usually provided in the CPLD.

According to the invention, the CPLD is subjected to logic programming in advance according to the time sequence requirement of power output, so that a plurality of GPIO ports of the CPLD can output control signals according to the required time sequence requirement; when the CPLD is logically programmed, all GPIO ports are divided into a plurality of BANKs (pages), different BANKs are respectively marked as BANK0 and BANK1, and a plurality of port GPIOs are respectively contained in the BANK0 and the BANK 1.

GPIO in BANK0 is connected with MOS-FET through bootstrap circuit, the output end of MOS-FET is connected with the input end of BANK1, GPIO in BANK1 is connected with the input end of industrial camera system. The BANK0 comprises a power supply pin VCCIO1, which is an input end of the BANK0 and is also an input end of the power-on timing sequence control circuit; the BANK1 includes a power supply pin VCCIO2, which is an input terminal of the BANK 1.

Further, GPIOs in the BANK0 include 3 ports, which are respectively denoted as GPIO1, GPIO2, GPIO 3; a GPIO1 in the BANK0 is connected with the input end of the bootstrap circuit 1, and the GPIO2 is connected with the input end of the bootstrap circuit 2; the output end of the bootstrap circuit 1 and the output end of the bootstrap circuit 2 are connected with the input end of the MOS-FET; the GPIO3 is connected with a switch of the industrial camera system. The MOS-FET is a metal-oxide-semiconductor field effect transistor, called MOS field effect transistor for short, and realizes the voltage control of the circuit by controlling the electric field effect, and the MOS-FET is essentially a triode.

Furthermore, the GPIO in the BANK0 further includes two other ports, which are respectively denoted as GPIO4 and GPIO5, and the system input power supply is connected to the GPIO4 through a voltage division circuit; GPIO5 is connected with ARM. Arm (advanced RISC machines) is a microprocessor, which is a CPU core that issues instructions to circuits to control their operation.

Furthermore, the voltage dividing circuit is a combined circuit comprising two voltage dividing resistors and a controllable precise voltage stabilizing source TL 431.

Further, a diode connected in series with the super capacitor is included in the energy storage circuit. Furthermore, the super capacitors are divided into two groups, and the diodes are connected between the two groups of super capacitors in series.

Furthermore, a power supply conversion device is arranged between the input power supply and the input end of the energy storage circuit; the power module (220V to 48V/24V/12V) or the power adapter which is usually purchased directly can be directly input at 220V without power conversion, but usually the direct input at 220V is not used, because the power conversion device is added, one more layer of protection can be provided, and the board end design is relatively simpler.

And a power supply conversion device is arranged between the output end of the MOS-FET and the input end of the BANK 1.

Further, GPIOs in the BANK1 include 2 ports, which are respectively denoted as GPIO1 and GPIO 2; GPIO1 and GPIO2 in the BANK1 are connected with the input end of the industrial camera system. Furthermore, a power supply conversion device is arranged between the GPIO1 and the GPIO2 in the BANK1 and the input end of the industrial camera system.

The invention also claims a control method of the industrial camera system time sequence, which comprises a control circuit using the industrial camera system time sequence.

In the invention, the number of the super capacitors in the two groups of super capacitors is 1 or more, and when the number of the super capacitors is more, different super capacitors are connected in parallel in the super capacitor group. A super capacitor is introduced here in order to store energy in order to meet the back-end power supply. The size of the capacity can be selected according to the overall power consumption of the system and the desired application scenario. If the requirement on the time of short power failure of the outside is high and the power consumption of the system is high, a super capacitor with high capacity can be selected. If the requirement on the power-off time is not high and the power consumption of the system is relatively low, a relatively small super capacitor can be selected. The diode isolation mainly cuts off a power supply path of the CPLD and an external system, and the main purpose of the diode and the super capacitor is to store electric energy again after passing through the diode, because the diode has one-way conductivity, namely the electric energy stored in the super capacitor II is not supplied to a relevant chip at the input end of the diode except for being supplied to the CPLD.

In the present invention, the switch of the industrial camera system may be a mechanical switch. Besides mechanical switches, lockless switches or any other devices capable of realizing starting or stopping signal input by external signal line control can be adopted, namely, the system can be controlled by external signal input.

The power supply simultaneously enters a voltage division circuit before entering the input control circuit, a power supply input signal enters the GPIO4 in the BANK0, the GPIO4 detects the stability of an external input power supply in real time, the GPIO5 in the BANK0 sends out an early warning notice to a system core chip ARM or FPGA, the ARM or FPGA feeds back a signal to notify the GPIO5, and then the CPLD performs corresponding processing action; when the GPIO4 detects the unstable condition of the external power supply, the situation is delayed for a period of time and then secondary repeated judgment is carried out, if the situation is judged for two times, the GPIO4 judges that the external power supply is unstable and the power-down time exceeds the preset value, the GPIO5 sends an early warning notice to an ARM, and an ARM feedback signal informs the CPLD to carry out power-down time sequence process; otherwise, the CPLD is informed by the ARM feedback signal not to do any processing action.

In the invention, when the control circuit is used for carrying out the power-off time sequence, the power-off time sequence is opposite to the power-on time sequence.

The invention provides a control circuit and a control method for a time sequence of an industrial camera system, which enhance the control of an industrial camera and industrial equipment on an input power supply. The service life influence caused by uncontrollable factors is eliminated, the service life of the system is greatly prolonged, the system works in a special application scene, the power consumption of the system is reduced, and the stability of the system is improved.

The software and hardware combined mode controls any time sequence of the system, and the power-on time sequence and the power-off time sequence are greatly controlled. All chips needing power-on and power-off time sequences can be precisely achieved according to the requirements of specification. In addition, compared with the application of direct hardware power-off in the past, all the power supplies of the system can be powered off sequentially according to the requirement, so that the rebound of energy of power supply paths is effectively avoided, and chip damage caused by power-off is avoided.

In an industrial application scene, equipment may be in a power supply state all the time, even if the equipment does not work, if the power supply of the system can be effectively managed, most power supply paths are automatically closed when the equipment does not work, and the equipment is in a state that the equipment can rest. When the device is used next time, the device can be quickly opened to work normally, so that the power consumption of the system and the self-heating of the device are reduced, and the service life of the device is greatly prolonged.

In an industrial environment, power input can be unstable for a long time, and a short power-down for a certain period, usually in the order of milliseconds, is very common. The invention provides a control circuit of an industrial camera system time sequence, wherein a super capacitor is introduced in the design, so that the system can still normally work when the system is powered off in a short time which is close to a second. The capacity of the super capacitor can be adjusted even further to improve the time for the system to be allowed to be powered down. This is clearly very helpful for industrial plants. On one hand, the stability of the system can be provided, and on the other hand, more time can be won for the system timing control and the integrity of the system data.

In the context of industrial equipment use, there are generally two types: one is that the equipment is kept at a very great distance from the operator or is not easily accessible, and the other is that the equipment is in the immediate vicinity of the operator. The application scenarios of the mechanical switch in the invention are three: 1. triggering the system to start working; 2. triggering the system to stop working; 3. and adjusting the collocation use sequence of the system and the external equipment. The mechanical switch can also control the system by inputting signals through an external signal line, so that the mechanical switch can be more flexible, and the application scenes of the mechanical switch are all in accordance with two application scenes used by equipment. By introducing a software and hardware combined control method, after the system is connected with a power supply, part of chips of the equipment can work firstly and work in a very low power consumption environment. When an operator needs to use the equipment, the system quickly enters a working state; when the device is not used, the power supply does not need to be turned off, and the switch is only needed to determine whether the device is put into a temporary dormant state or not.

In the past, CPLD is used for time sequence control, which is more direct and simpler. The GPIO is controlled by software, and the GPIO of the CPLD directly controls the enabling pin of the power chip. Such attempts have caused unpredictable problems. In practical experiments, it is found that the state of the GPIO is often uncontrollable when the external power supply is connected to the CPLD during the period of regular operation. Glitches sometimes occur, high levels sometimes occur, pulses sometimes occur, and so forth. Uncontrollable factors cause the next-stage chip to suddenly work and stop working, and the system time sequence is abnormal. The invention provides a method for controlling the time sequence of an industrial camera system, which introduces the design of combining double GPIO with a bootstrap circuit to achieve the accurate control of a control power supply chip. And the GPIO of the CPLD can be completely controlled.

Compared with the prior art, the method for controlling the time sequence of the industrial camera system has the following advantages:

(1) the random time sequence of the system is controlled in a mode of combining software and hardware, and the power-on time sequence and the power-off time sequence are greatly controlled.

(2) The application of the super capacitor is introduced into the design, so that the system can still normally work when the system is powered off in a short time which is close to the second basic time, and the capacity of the super capacitor can be adjusted to further improve the time of the system which is allowed to be powered off.

(3) The use of the mechanical switch and the control method of combining software and hardware can lead part of devices in the system to work firstly and work under the environment with very low power consumption after the system is connected with a power supply.

Drawings

FIG. 1: a control circuit schematic diagram of the timing sequence of an industrial camera system.

FIG. 2: a voltage divider circuit schematic.

Description of reference numerals: 1-energy storage circuit, 2-power-on sequence control circuit.

Detailed Description

The technical solution of the present invention will be described in detail by the following specific examples.

As shown in fig. 1, a schematic diagram of a control circuit of an industrial camera system timing sequence is provided, the control circuit includes an energy storage circuit 1 and a power-on timing sequence control circuit 2, the energy storage circuit 1 includes two groups of super capacitors, which are respectively a first super capacitor and a second super capacitor, a power conversion device is arranged between an input end of the first super capacitor and an input power supply, and a directly purchased power conversion module (220V to 48V/24V/12V) or a power adapter is usually used. The number of the super capacitors in the first super capacitor and the second super capacitor is 1, the capacity is selected according to the overall power consumption of the system and the required application scene, and a diode is connected in series between the first super capacitor and the second super capacitor. And the output end of the second super capacitor is connected with the input port of the CPLD.

In BANK0, there are 5 GPIO ports, which are respectively denoted as GPIO1, GPIO2, GPIO3, GPIO4, and GPIO 5; in BANK1, there are 2 GPIO ports, which are respectively denoted as GPIO1 and GPIO2, each GPIO port has its own logic operation, and there is a logic relationship between different GPIO ports, so that after the CPLD is logically programmed, different GPIO ports can control the output of the power supply signal and the high and low levels of the output according to the time requirement. The process of performing logic programming on the CPLD is called burning, and after the burning is finished, the CPLD is connected into a circuit to realize the control of the time sequence of the industrial camera system.

In BANK0 and BANK1, each of which has 1 VCCIO port, the VCCIO port is a supply pin of BNAK, the voltage of VCCIO can be set, and when the input voltage matches the voltage of VCCIO, the corresponding BANK starts to operate. The VCCIO port in BANK0 is denoted as VCCIO1, and the VCCIO port in BANK1 is denoted as VCCIO 2. The BANK0 comprises a power supply pin VCCIO1, which is an input end of the BANK0 and is also an input end of the power-on timing sequence control circuit; the BANK1 includes a power supply pin VCCIO2, which is an input terminal of the BANK 1.

The power-on timing sequence control circuit 2 comprises a timing sequence control chip CPLD, wherein the CPLD comprises BANK0 and BANK1, and GPIOs in the BANK0 comprise GPIO1, GPIO2 and GPIO 3; the GPIO1 is connected with the input end of the bootstrap circuit 1, and the GPIO2 is connected with the input end of the bootstrap circuit 2; the output end of the bootstrap circuit 1 and the output end of the bootstrap circuit 2 are connected with the input end of the MOS-FET; a power conversion device is provided between the output of the MOS-FET and the input of the BANK 1. The GPIO3 is connected to a switch of the industrial camera system. GPIOs in BANK0 also include GPIO4, GPIO5, the system input power supply is connected with GPIO4 through the bleeder circuit; GPIO5 is connected with ARM. As shown in fig. 2, the voltage divider circuit is a combined circuit including two voltage divider resistors and TL 431.

GPIOs in BANK1 include GPIO1, GPIO 2; GPIO1 and GPIO2 in BANK1 are connected to the input of the industrial camera system. And a power supply conversion device is arranged between the GPIO1 and the GPIO2 in the BANK1 and the input end of the industrial camera system.

The method for controlling the time sequence of the industrial camera system by adopting the control circuit comprises the following steps:

(1) after the power supply of the system is input, the system power supply is converted into a system universal power supply path, then the system universal power supply path enters a first super capacitor, and then enters a second super capacitor through a diode;

(2) after passing through the second super capacitor, a power supply is supplied to BANK0 of the CPLD through a BANK0 VCCIO1 port (a VCCIO1 port is a power supply pin of the BANK 0), GPIO1 and GPIO2 in the BANK0 output PWM (pulse width modulation) specified waveforms, when the voltage difference output by GPIO1 and GPIO2 in the BANK0 is greater than the voltage of the output level of GPIO in BNAK0, through MOS-FET (metal oxide semiconductor field effect transistor) switching, the period of the PWM waveform is set to be 500KHz, the PWM waveforms are respectively passed through a bootstrap line, so that GPIO1 and GPIO2 respectively reach the voltage output capacities of 12V and 7V, and then the power supply is output after being switched through MOS-FETs and being subjected to power supply conversion;

(3) the output power is supplied to BANK1 of the CPLD through a BANK1 VCCIO2 port (VCCIO2 is a power supply pin of BANK 1), at the moment, GPIO in BANK1 can work normally, at the moment, GPIO1 and GPIO2 in BANK1 control an enabling pin of a power conversion chip, and at the moment, the industrial camera system is in a standby state;

(4) when the conditions of the external equipment are all prepared, whether the next work is needed or not can be determined only by the specified operation of the mechanical switch;

at the moment, a mechanical switch of the system is turned on, and after the GPIO3 in the CPLD receives an input signal of the mechanical switch, the power supply conversion is controlled through the GPIO1 and the GPIO2 in the BANK1, so that the system can start to work;

(5) in the working process of the system, before the power input enters the system power conversion in the circuit, the input end of the power passes through the voltage division circuit and a block of the voltage division circuit, and the block is specifically a combined circuit comprising two voltage division resistors and TL 431. The power input signal enters GPIO4 of BANK0 in the CPLD, the GPIO4 can detect the stability of an external input power in real time, the GPIO5 of the BANK0 sends out an early warning notice to a system core chip ARM, the ARM feedback signal informs the GPIO5, and then the CPLD performs corresponding processing action;

the process of detecting the stability of the external input power supply by the GPIO4 is as follows: when the external power supply signal is unstable, the triggering software firstly identifies, a period of delay time is added in the software, and then the state of the GPIO is judged once. Specifically, after the GPIO4 detects that the external power supply is unstable, the next determination is performed after delaying for 0.1s, if the power is temporarily lost, the system can still work normally due to the existence of the super capacitors i and ii, and the second repeated determination is to avoid the influence of erroneous determination on the normal work of the system. If the GPIO4 judges that the external power supply is unstable and the power-down time exceeds the preset value after two determinations, the GPIO5 sends an early warning notice to the ARM, and the ARM feedback signal informs the CPLD to perform power-down time sequence. Otherwise, the CPLD is informed not to do any processing action by the ARM feedback signal;

(6) when the ARM feedback signal informs the CPLD to carry out power-off time sequence, the GPIO control of the BANK1 is quickly closed according to the specified requirements, so that the power supply chip accurately finishes the power-off time sequence, and the power supply chip completely meets the power-on and power-off sequence requirements in the specifications of chips such as FPGA, AMR or ZYNQ. The power down sequence is exactly opposite to the power up sequence.

After the power-off time sequence is completed, the CPLD waits for the next power input until the electric energy in the second super capacitor can not support the normal working position of the CPLD any more; when the power supply output is available again next time, the operation of the step (1) is repeated again.

In step (2), due to the logic programming timing design in the CPLD, the power is first supplied to BANK0 of the CPLD and not supplied to BANK 1. So GPIO on BANK0 is controllable and functional, while GPIO on BANK1 is temporarily non-functional.

In the step (4), the power supply conversion is controlled through the GPIO1 and the GPIO2 of the BANK1, and only two paths of power supply control are enumerated here, and the two paths of power supply control can be increased or decreased according to actual conditions. Because the GPIO is controlled by software, the GPIO controls the enabling pin of the power supply chip, so that the power-on sequence of each power supply path can be accurately controlled.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, so any modifications, equivalents, improvements and the like made within the spirit of the present invention should be included in the scope of the present invention.

Claims

1. A control circuit of industrial camera system time sequence is characterized in that: the power-on time sequence control circuit comprises an energy storage circuit and a power-on time sequence control circuit, wherein the input end of the energy storage circuit is connected with an input power supply, the output end of the energy storage circuit is connected with the input end of the power-on time sequence control circuit, and the output end of the power-on time sequence control circuit is connected with the input end of an industrial camera system; the energy storage circuit comprises a super capacitor; the power-on time sequence control circuit comprises a programmable logic device CPLD, the CPLD comprises a plurality of general programmable input/output ports GPIO, the CPLD is subjected to logic programming in advance according to the time sequence requirement of power output, and all the GPIOs are divided into two pages BANK0 and BANK 1; the BANK0 and the BANK1 respectively comprise a plurality of ports GPIO; the GPIOs in the BANK0 comprise 3 ports which are respectively marked as GPIO1, GPIO2 and GPIO 3; the GPIO1 is connected with the input end of the bootstrap circuit 1, and the GPIO2 is connected with the input end of the bootstrap circuit 2; the output end of the bootstrap circuit 1 and the output end of the bootstrap circuit 2 are connected with the input end of the MOS-FET; the GPIO3 is connected with a mechanical switch of the industrial camera system; the output end of the MOS-FET is connected with the input end of the BANK1, and the GPIO in the BANK1 is connected with the input end of the industrial camera system.

2. The industrial camera system timing control circuit of claim 1, wherein: the GPIO in the BANK0 also comprises another two ports which are respectively marked as GPIO4 and GPIO5, and a system input power supply is connected with the GPIO4 through a voltage division circuit; the GPIO5 is connected with the microprocessor ARM.

3. The industrial camera system timing control circuit of claim 2, wherein: the voltage division circuit is a combined circuit comprising two voltage division resistors and a controllable precise voltage stabilization source TL 431.

4. The industrial camera system timing control circuit of claim 1, wherein: the energy storage circuit comprises a diode connected with a super capacitor in series.

5. The industrial camera system timing control circuit of claim 4, wherein: the super capacitors are divided into two groups, and the diodes are connected between the two groups of super capacitors in series.

6. The industrial camera system timing control circuit of claim 1, wherein: and a power supply conversion device is arranged between the input power supply and the input end of the energy storage circuit.

7. The industrial camera system timing control circuit of claim 1, wherein: the GPIOs in the BANK1 comprise 2 ports which are respectively marked as GPIO1 and GPIO 2; GPIO1 and GPIO2 in the BANK1 are connected with the input end of the industrial camera system.

8. A method for controlling the time sequence of an industrial camera system is characterized in that: use of the control circuit of an industrial camera system timing according to any of claims 1-7 for controlling an industrial camera system timing, the control method comprising the steps of:

s1, after the power supply of the system is input, the power supply is converted into a system general power supply path through the energy storage circuit and enters the power-on time sequence control circuit;

s2, power supply BANK0, GPIO1 and GPIO2 in BANK0 output PWM specified waveform, when the voltage difference output by GPIO1 and GPIO2 in BANK0 is larger than the voltage of output level of GPIO in BNAK0, output is switched through MOS-FET;

s3, supplying the power supply output after MOS-FET switching to BANK1 in the CPLD, wherein GPIO in BANK1 can work normally, and the industrial camera system is in a standby state;

s4, the mechanical switch is turned on, after the GPIO3 in the CPLD receives an input signal of the mechanical switch, the power supply conversion is controlled through the GPIO in the BANK1, and the system can start to work;

s5, in the working process of the system, the BANK0 can detect the stability of an external input power supply in real time and send out an early warning signal, and the CPLD receives the feedback signal to process the feedback signal so as to realize time sequence control;

s6, when the CPLD is informed by the feedback signal to carry out power-off time sequence, the GPIO control of BANK1 is quickly closed according to the specified requirements, so that the power chip accurately completes the power-off time sequence, and the power chip completely meets the power-on and power-off sequence requirements in the specification of the FPGA, AMR or ZYNQ chip; the power down sequence is exactly opposite to the power up sequence.