CN111883898A - Method for manufacturing micro delay line chip of micro coaxial structure - Google Patents
Method for manufacturing micro delay line chip of micro coaxial structure Download PDFInfo
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- CN111883898A CN111883898A CN202010519992.4A CN202010519992A CN111883898A CN 111883898 A CN111883898 A CN 111883898A CN 202010519992 A CN202010519992 A CN 202010519992A CN 111883898 A CN111883898 A CN 111883898A
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- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
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- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P11/00—Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
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Abstract
The invention is suitable for the technical field of radio frequency microwave, and provides a method for manufacturing a micro delay line chip of a micro coaxial structure, which comprises the following steps: preparing a plurality of first through holes on a first substrate, a second substrate and a third substrate, and preparing a plurality of second through holes on the second substrate and the third substrate; preparing a first groove and a second groove corresponding to the first substrate and the third substrate; respectively preparing a switching support structure in the grooves at the two ends of the second groove, arranging a third through hole in each switching support structure, preparing a fourth through hole at the bottom of each groove, communicating the third through holes with the fourth through holes, and preparing a bonding pad on the lower surface of a third substrate; preparing a coaxial core on a second substrate; the first substrate, the second substrate and the third substrate are bonded in sequence to obtain the micro-delay line chip with a micro-coaxial structure, and the length of the transmission line can be controlled and the delay amount of the chip can be adjusted by changing the structural forms of the coaxial core (transmission line) in the micro-delay line chip, such as turning, winding or stacking.
Description
Technical Field
The invention belongs to the technical field of radio frequency microwave, and particularly relates to a manufacturing method of a micro delay line chip with a micro coaxial structure.
Background
The delay line is widely applied to the technical fields of radar, communication and the like. In addition, the delay chip of the Monolithic Microwave Integrated Circuit (MMIC) has a large size and a single function, so that the application of the chip in a system is difficult, and the indexes of the system and components are difficult to optimize. The coaxial line delay line has the problems of large volume, incapability of integration and the like.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a method for manufacturing a micro delay line chip with a micro coaxial structure, and aims to solve the problems of large loss, large temperature drift, large volume and incapability of inheritance in the delay line technology in the prior art.
In order to achieve the above object, a first aspect of an embodiment of the present invention provides a method for manufacturing a micro delay line chip with a micro coaxial structure, including:
respectively preparing a plurality of first through holes corresponding to positions at first preset positions of a first substrate, a second substrate and a third substrate, and respectively preparing a plurality of second through holes corresponding to positions at second preset positions of the second substrate and the third substrate, wherein the first preset positions are different from the second preset positions;
respectively preparing a first groove and a second groove corresponding to the first substrate and the third substrate in position, wherein the plurality of first through holes are arranged around the corresponding first groove or second groove;
preparing a switching support structure in each of the grooves at the two ends of the second groove, wherein a third through hole is arranged in each switching support structure, a fourth through hole is prepared at a position corresponding to the third through hole in the second groove, a bonding pad is prepared in a region corresponding to the switching support structure on the lower surface of the third substrate, and the lower surface of the third substrate is a surface corresponding to the second groove;
preparing a coaxial core on a second substrate;
and sequentially bonding the first substrate, the second substrate and the third substrate, and enabling the positions of the first through holes on the substrates to correspond to each other, the positions of the first groove and the second groove and the positions of the notches to correspond to each other respectively, wherein the coaxial core is positioned in a cavity formed by the first groove and the second groove.
As another embodiment of the present application, the preparing a coaxial core on a second substrate includes:
etching a plurality of fifth through holes on the second substrate by adopting a DRIE (deep etching) or wet etching method, so that the second substrate forms a structure comprising a hollow first silicon wafer, a plurality of silicon beams and a coaxial core, wherein the coaxial core is positioned in the first silicon wafer, two ends of the coaxial core are respectively connected with an O bend of the first silicon wafer, and the silicon beams which are arranged at intervals are respectively positioned at two sides of the coaxial core and used as supporting beams of the coaxial core.
As another embodiment of the present application, after the preparing the coaxial core structure on the second substrate, the method further includes:
and electroplating a first metal layer on the upper surface and the lower surface of the first silicon wafer, the inner side of the first silicon wafer, the outer surface of the part except the joint part with the preset length away from the two ends of the coaxial core body, the interiors of the fifth through holes, the interiors of the first through holes and the second through holes on the second substrate.
As another embodiment of this application, a plurality of first through-holes a plurality of second through-holes a third through-hole a fourth through-hole and a plurality of fifth through-holes's shape is circular, rectangle or square, and there is the inclination between pore wall perpendicular to ground plane or pore wall and the ground plane.
As another embodiment of the present application, widths and depths of the first groove and the second groove are determined according to a frequency of a transmission signal of the coaxial core;
the etching depth of the first groove and the second groove is adjusted according to the etching process time, and the groove wall is perpendicular to the ground plane or an included angle is formed between the groove wall and the ground plane.
As another embodiment of the present application, the second groove includes an adapter groove in which the adapter support structure is disposed and a third groove excluding a groove corresponding to the adapter support structure; the side length of the switching groove in the direction vertical to the signal transmission direction is larger than that of the third groove in the direction vertical to the signal transmission direction.
As another embodiment of the present application, the method further includes:
electroplating a second metal layer on the lower surface of the first substrate, the groove wall of the first groove and the interiors of the first through holes on the first substrate, wherein the lower surface of the first substrate is the surface where the first groove is located;
and electroplating a third metal layer on the upper surface of the third substrate, the preset position of the lower surface of the third substrate, the preset position of the upper surface of the transfer support structure, the interiors of the plurality of first through holes, the interiors of the plurality of second through holes, the interiors of the third through holes and the interiors of the fourth through holes, wherein the preset position of the lower surface of the third substrate is an area except for the corresponding area of the transfer support structure, the preset position of the upper surface of the transfer support structure is the position around the third through hole, and the upper surface of the third substrate is the surface where the second groove is located.
As another embodiment of the present application, the electroplating a second metal layer on the lower surface of the first substrate, on the walls of the first groove, and inside the plurality of first through holes on the first substrate includes:
preparing a seed layer on the lower surface of the first substrate, the groove wall of the first groove and the insides of the first through holes on the first substrate by adopting a sputtering process;
coating photoresist on the seed layer, transferring a preset pattern onto the photoresist, and photoetching according to the preset pattern;
electroplating the photoetching area on the photoresist to thicken the pattern of the exposed area;
removing the photoresist outside the electroplating area;
and removing the seed layer to form a second metal layer comprising the circuit structure.
As another embodiment of the present application, the preparing a pad in a region corresponding to the transfer support structure on the lower surface of the third substrate includes:
depositing a dielectric layer on the lower surface of the third substrate in the region corresponding to the switching support structure;
and preparing the bonding pad on the dielectric layer by adopting a chemical deposition, sputtering, evaporation or electroplating mode.
As another embodiment of the present application, the metals used in the first metal layer, the second metal layer, and the third metal layer are the same metals.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: compared with the prior art, the invention respectively prepares a plurality of first through holes corresponding to the positions at the first preset positions of the first substrate, the second substrate and the third substrate, and respectively prepares a plurality of second through holes corresponding to the positions at the second preset positions of the second substrate and the third substrate, wherein the first preset positions are different from the second preset positions; respectively preparing a first groove and a second groove corresponding to the first substrate and the third substrate in position, wherein a plurality of first through holes are arranged around the corresponding first groove or second groove; respectively preparing a switching support structure in the grooves at the two ends of the second groove, arranging a third through hole in each switching support structure, preparing a fourth through hole at the position corresponding to the third through hole in the second groove, and preparing a bonding pad in the corresponding area of the switching support structure on the lower surface of the third substrate; preparing a coaxial core on a second substrate; the first substrate, the second substrate and the third substrate are bonded in sequence to obtain a micro-delay line chip of a micro-coaxial structure, and the length of a transmission line can be controlled and the delay amount of the chip can be adjusted by performing turning, winding or stacking structure transformation on a coaxial core (transmission line) in the micro-delay line chip, so that the problems of large loss, large temperature drift, large volume and incapability of integration in the delay line technology in the prior art can be solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flow chart illustrating an implementation of a method for manufacturing a micro delay line chip with a micro coaxial structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a first via provided by an embodiment of the present invention;
FIG. 3 is a schematic view of an end of a second groove provided in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of a bonding pad provided by an embodiment of the invention;
FIG. 5 is a schematic view of one end of a coaxial core provided by an embodiment of the present invention;
fig. 6 is a schematic view of a broken line type O-ring according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic flow chart of an implementation of a method for manufacturing a micro delay line chip with a micro coaxial structure according to an embodiment of the present invention, which is described in detail below.
Optionally, the shapes of the first through holes and the second through holes may be circular, rectangular or square, and the hole wall is perpendicular to the ground plane or an inclination angle exists between the hole wall and the ground plane. The angle of inclination here refers to an angle other than 90 deg..
Alternatively, the first preset positions may be both ends of the first substrate, both ends of the second substrate, and both ends of the third substrate, and the second preset positions may be positions other than both ends of the first substrate, the second substrate, and the third substrate. Alternatively, the first substrate, the second substrate and the third substrate may be silicon wafers.
Optionally, a first metal is electroplated in the first through hole and the second through hole on each substrate, and the first metal may be gold.
Optionally, in this step, a plurality of first through holes and a plurality of second through holes may be respectively formed on the first substrate, the second substrate, and the third substrate by Deep Reactive Ion Etching (DRIE) or wet Etching. The steps for preparing a plurality of first through holes by taking the first substrate as an example are as follows: firstly, coating a layer of photoresist on one surface of a first substrate, photoetching a preset pattern at the position of a through hole on the photoresist, photoetching according to the preset pattern, and etching to form the through hole penetrating through the upper surface and the lower surface of the first substrate. Similarly, corresponding through holes are etched on the second substrate and the third substrate respectively according to the mode of etching a plurality of first through holes on the first substrate.
Optionally, for convenience of etching, the first through hole may be etched into a long rectangular through hole, so as to improve etching efficiency.
Alternatively, the shape of the first through-hole may be different in different location areas. As shown in fig. 2, for example, taking the first substrate as an example, a plurality of first through holes are disposed around two ends of the first substrate, wherein the plurality of first through holes may be three rectangular through holes perpendicular to each other (one end of the first substrate is shown in fig. 2). As shown in fig. 3, a plurality of first through holes are disposed around two ends of the third substrate, wherein the plurality of first through holes may be three rectangular through holes perpendicular to each other, a plurality of second through holes are disposed between the first through holes at two ends, and the second through holes may be circular through holes, square through holes, or rectangular through holes. The second through hole in fig. 3 is a circular through hole.
102, preparing a first groove and a second groove corresponding to the first substrate and the third substrate respectively, wherein the plurality of first through holes are arranged around the corresponding first groove or second groove.
Alternatively, the cross-sectional shapes of the first groove and the second groove may be regular patterns or irregular patterns, for example, as shown in fig. 3, the cross-sectional shape of the first groove and the second groove may be a rectangle, a shape in which a plurality of rectangles are connected, or a shape in which the edge is not a straight line. The shape of the cross-section of the first groove and the second groove is not limited in this application.
Optionally, the widths and depths of the first groove and the second groove are determined according to the frequency of the transmission signal of the coaxial core; the etching depth of the first groove and the second groove is adjusted according to the etching process time, and the groove wall is perpendicular to the ground plane or an included angle is formed between the groove wall and the ground plane. The groove wall is used as a supporting wall of the coaxial structure outer conductor.
Optionally, in this step, a Deep Reactive Ion Etching (DRIE) or wet Etching method may be used to prepare the first groove and the second groove on the first substrate and the second substrate respectively.
The process flow of preparing a first recess in the first substrate may include: and coating photoresist on the lower surface (or the upper surface) of the first substrate, then carrying out photoetching development on the photoresist, etching according to the developed image to obtain the shape of the first groove, and adjusting the etching depth through etching process time. And after the etching is finished, removing the residual photoresist.
Optionally, the second groove includes a transfer groove provided with the transfer support structure and a third groove excluding the corresponding groove of the transfer support structure. As shown in fig. 3, the side length of the through recess in the vertical signal transmission direction is greater than the side length of the third recess in the vertical signal transmission direction. It will be appreciated that the lithographically developed image used in making the second recess is different from the lithographically developed image used in making the first recess.
After the first groove on the first substrate is prepared, the method further comprises the following steps: and electroplating a second metal layer on the lower surface of the first substrate, the groove wall of the first groove and the interiors of the plurality of first through holes on the first substrate, wherein the lower surface of the first substrate is the surface where the first groove is located, and the lower surface of the first substrate comprises the groove bottom of the first groove.
Optionally, the electroplating a second metal layer on the lower surface of the first substrate, on the walls of the first groove, and inside the plurality of first through holes on the first substrate may include:
preparing a seed layer on the lower surface of the first substrate, the groove wall of the first groove and the insides of the first through holes on the first substrate by adopting a sputtering process; coating photoresist on the seed layer, transferring a preset pattern onto the photoresist, and photoetching according to the preset pattern; electroplating the photoetching area on the photoresist to thicken the pattern of the exposed area; removing the photoresist outside the electroplating area; and removing the seed layer to form a second metal layer comprising the circuit structure.
When the seed layer is prepared by a sputtering process, a pretreatment of the sputtering process is required, for example, cleaning a sputtering region, and performing plasma activation on the cleaned sputtering region, followed by sputtering. The metal used for the seed layer can include TiCu, WAu and the like, and the seed layer can play a role in blocking and adhering and provides a manufacturing basis for the next electroplating. Optionally, a double-sided sputtering mode may be adopted during sputtering, and the multiple layers of metal simultaneously or respectively play roles in blocking, adhering and conducting.
Optionally, when the seed layer is removed, the seed layer may be removed by wet etching or dry etching to form a designed circuit structure.
Optionally, the metal material corresponding to the second metal layer formed by electroplating may be gold.
103, respectively preparing a transfer support structure in the grooves at the two ends of the second groove, wherein a third through hole is arranged in each transfer support structure, a fourth through hole is prepared at a position corresponding to the third through hole in the second groove, a bonding pad is prepared in a region corresponding to the transfer support structure on the lower surface of the third substrate, and the lower surface of the third substrate is a surface corresponding to the second groove.
Optionally, the third through hole and the fourth through hole are circular, rectangular or square, and the hole walls are perpendicular to the ground plane or an inclination angle exists between the hole walls and the ground plane.
A schematic view of the second groove as shown in fig. 3. The switching support structure is prepared in the switching groove, the surface where the second groove is located is set as the upper surface of the third substrate, and the bonding pad can be prepared in the area corresponding to the switching groove in the lower surface of the third substrate, so that the third through hole formed in the switching support structure and the fourth through hole formed in the second groove can be communicated with the bonding pad and further grounded. Alternatively, the adapting groove may be a square groove. The depth of the switching groove is determined according to the frequency of the transmission signal of the coaxial core, and the etching depth is adjusted according to the etching process time.
Optionally, the third through hole can set up the intermediate position at switching bearing structure, for example in fig. 3, switching bearing structure is the bearing structure who comprises the long and thin square body in both sides and thick cuboid in the middle, and the third through hole can set up thick cuboid intermediate position in the middle, and is optional, and thick cuboid in the middle also can be the square. Alternatively, the length of the transfer support structure may be the same as the inner length of the transfer groove, or slightly smaller than the inner length of the transfer groove. It should be noted that the structural configuration of the transition support structure is not limited in this application, as long as the structure can provide a support function for the coaxial core.
Optionally, the fourth through hole may be disposed at a bottom of the adapting groove and communicated with the third through hole.
Alternatively, the transfer support structure may be prepared simultaneously with the second groove on the third substrate, or after the preparation of the second groove is completed, the transfer support structure may be separately prepared and then bonded into the transfer groove through metal.
Optionally, after the second groove and the transfer support structure are prepared, a third metal layer is electroplated on the upper surface of the third substrate, the preset position of the lower surface of the third substrate, the preset position of the upper surface of the transfer support structure, the inside of the plurality of first through holes, the inside of the plurality of second through holes, the inside of the third through holes and the inside of the fourth through holes, the preset position of the lower surface of the third substrate is an area except for an area corresponding to the transfer support structure, the preset position of the upper surface of the transfer support structure is a position around the third through hole, and the upper surface of the third substrate is a surface where the second groove is located.
Optionally, the process method adopted for electroplating the third metal layer is as follows: preparing a seed layer at the position needing electroplating by adopting a sputtering process; coating photoresist on the seed layer, transferring a preset pattern onto the photoresist, and photoetching according to the preset pattern; electroplating the photoetching area on the photoresist to thicken the pattern of the exposed area; removing the photoresist outside the electroplating area; and removing the seed layer to form a third metal layer comprising the circuit structure.
Optionally, the metal used for electroplating the third metal layer may be the same as the metal used for electroplating the second metal layer, for example, the metal used for electroplating the third metal layer may be gold.
As shown in the schematic diagram of the pad of fig. 4. Optionally, an area corresponding to the adapting groove on the lower surface of the third substrate is a square frame area, and the pad may be disposed in the middle of the square frame area. It should be noted that the third through hole and the fourth through hole disposed on the adapting groove may be connected to the pad, so as to be grounded.
Optionally, the preparing the pad on the lower surface of the third substrate may include:
depositing a dielectric layer on the lower surface of the third substrate in the region corresponding to the switching support structure; and preparing the bonding pad on the dielectric layer by adopting a chemical deposition, sputtering, evaporation or electroplating mode.
Optionally, a dielectric layer may be prepared by chemical vapor deposition, sputtering, evaporation, or oxidation, and the prepared dielectric layer may play a role in protecting the silicon wafer, protecting the circuit structure on the third substrate, and insulating the surface of the third substrate.
Optionally, the prepared bonding pad can be used for ball mounting process, iron bonding, gold wire bonding, gold belt bonding and other processes. Optionally, the UBM metal layer used in the pad preparation may be made of metals such as Ni, Pt, Cu, W, or Rh, the solder mask layer around the UBM metal layer may be made in a chemical vapor deposition manner, a sputtering process, an evaporation manner, or a spin coating manner, and the solder mask layer is made of materials such as Si3N4, SiO2, or Polyimide (PI). Optionally, when the pad is prepared, the UBM metal layer may be prepared first, and then the solder mask layer on the periphery of the UBM metal layer is prepared, or the solder mask layer is prepared first by using a photolithography process, and then the pad enclosed in the solder mask layer is prepared, and the preparation sequence of the UBM metal layer and the pad is not limited in this application.
Optionally, the switching support structure and the bonding pad in the switching groove form a switching structure of the micro delay line chip of the micro coaxial structure, and the switching structure is used for switching signals on the coaxial core. And the pad may serve as an input port or an output port for signals.
Optionally, this step may include: etching a plurality of fifth through holes on the second substrate by adopting a DRIE (deep etching) or wet etching method, so that the second substrate forms a structure comprising a first silicon wafer, a plurality of silicon beams and a coaxial core body, wherein the first silicon wafer can be in the shape of an O-shaped silicon wafer, a rectangular frame silicon wafer and the like, the coaxial core body is positioned in the first silicon wafer, two ends of the coaxial core body are respectively connected with an O bend of the first silicon wafer, and the plurality of silicon beams which are arranged at intervals are respectively positioned at two sides of the coaxial core body and are used as supporting beams of the coaxial core body.
Optionally, the shape of the fifth through holes may be circular, rectangular or square, and the hole walls are perpendicular to the ground plane or an inclination angle exists between the hole walls and the ground plane.
As shown in fig. 5, a schematic view of one end of the coaxial core is shown, a silicon beam supporting the coaxial core is formed between two adjacent fifth through holes along the signal transmission direction, and the coaxial core is formed between two adjacent fifth through holes perpendicular to the signal transmission direction. The plurality of first through holes and the plurality of second through holes prepared in step 101 are provided on the first silicon wafer. The length of the coaxial core is not limited, and the transmission line of the coaxial core as the micro-coaxial structure may be in various forms such as a straight line, a broken line, or a bent winding, and may be prepared in structural forms such as a bend, a winding, or a stack, so as to control the length of the transmission line and adjust the delay amount of the delay line. The shape of the first silicon wafer changes with the shape of the coaxial core, that is, the first silicon wafer may be a regular O-ring or a broken line O-ring (as shown in fig. 6).
Optionally, the coaxial core is used as a transmission line of a micro delay line chip of a micro coaxial structure, and the length of the coaxial core determines the delay amount of the delay line at different frequencies.
Alternatively, the beam walls of the plurality of silicon beams may be perpendicular to the ground plane or have an inclination angle with the ground plane.
Optionally, after the coaxial core is prepared, a first metal layer is electroplated on the upper and lower surfaces of the first silicon wafer, the inner side of the first silicon wafer, the outer surface of the part except for the preset length away from the joint at the two ends of the coaxial core, the interiors of the fifth through holes, the interiors of the first through holes and the second through holes on the second substrate.
When the first metal layer is electroplated, the two ends of the coaxial core body connected with the first silicon wafer are respectively free with a section distance, the coaxial core body corresponding to the section distance is not electroplated, if electroplating is carried out, a signal uploaded to the coaxial core body cannot be led out through a bonding pad of the third substrate, or a signal led in by the bonding pad cannot be conducted to the coaxial core body.
Optionally, the method for electroplating the first metal layer is the same as the above-mentioned method for electroplating the second metal layer or electroplating the third metal layer, and the details are not repeated again. The metal adopted for electroplating the first metal layer is the same as the metal adopted for electroplating the second metal layer, and can also be gold, the metal adopted for electroplating the first metal layer is also the same as the metal adopted for electroplating the third metal layer, namely the metal adopted for electroplating the first metal layer, the second metal, the third metal layer and the metal electroplated in all the through holes can all be the same metal, and can be iron, copper, nickel, silver or gold, etc. in the application, and gold can be adopted in the application.
It should be noted that, when the first substrate, the second substrate, and the third substrate are prepared, the first substrate, the second substrate, and the third substrate may be sequentially prepared, or the first substrate, the second substrate, and the third substrate may be prepared by the same process on different substrates according to different preparation processes, so that the preparation efficiency may be improved.
And 105, sequentially bonding the first substrate, the second substrate and the third substrate, and enabling the positions of the first through holes on the substrates to correspond to each other, the positions of the first groove and the second groove and the positions of the notches to correspond to each other respectively, wherein the coaxial core is positioned in a cavity formed by the first groove and the second groove.
Optionally, after the preparation is completed, the first substrate, the second substrate and the third substrate need to be bonded in sequence, that is, the lower surface of the first substrate is bonded to the upper surface of the second substrate, and the lower surface of the second substrate is bonded to the upper surface of the third substrate. The lower surface of the first substrate is the surface where the first groove is located, and the upper surface of the third substrate is the surface where the second groove is located. Optionally, wafer-level bonding, such as metal thermocompression bonding, eutectic bonding, anodic bonding, or fusion bonding, may be used for bonding.
In addition, the first through holes on all the substrates correspond to and are communicated, so that direct grounding can be realized. And the second substrate corresponds to the third substrate in position of the second through hole. The positions of the first groove and the second groove correspond to the positions of the notches respectively, and the coaxial core is positioned in a cavity formed by the first groove and the second groove, so that a signal of the coaxial core is transmitted in the cavity, is connected with the bonding pad through a third through hole and a fourth through hole in a switching support structure on a third substrate, and is led out or input.
Optionally, during the specific bonding, firstly, surface treatment is performed on all the substrates, high-precision alignment is performed, then, the environment where the substrates are located is vacuumized, and heating and pressurizing are performed in the vacuum environment, so that the micro delay line chip with the micro coaxial structure is obtained.
After obtaining the micro delay line chip with the micro coaxial structure, the micro delay line core piece with the micro coaxial structure formed by the first substrate, the second substrate and the third substrate after bonding is separated from other wafer parts in a scribing way. Optionally, the scribing mode may be a grinding wheel scribing mode or a laser scribing mode, so as to scribe the prepared micro delay line chips with the micro coaxial structures from a large wafer, thereby obtaining the micro delay line chips with the micro coaxial structures.
Optionally, in this embodiment, the first substrate, the second substrate, and the third substrate are prepared on three large wafers, and then the prepared three substrates are aligned and bonded, and are divided by dicing, so that there is no need to manually adjust a circuit portion or other connection portions that need to be manually adjusted, and batch production can be achieved.
Optionally, the delay amount of the micro delay line chip of the micro coaxial structure mainly depends on the length of the transmission line, and the transmission line may be a single-layer transmission line or a double-layer transmission line. The double-layer transmission line is connected with the upper layer and the lower layer through the switching structure, and the winding length is increased by increasing the longitudinal thickness (for example, the direction represented by the Z axis in the three-dimensional coordinate system) under the condition that the area of a plane (for example, the area represented by the x axis and the y axis in the three-dimensional coordinate system) is not increased, so that the delay amount is increased. For example, the two micro-delay line chips with micro-coaxial structures are connected by the adapter structure to form a micro-delay line chip with a double-layer micro-coaxial structure.
The manufacturing method of the micro delay line chip with the micro coaxial structure comprises the steps of respectively manufacturing a plurality of first through holes corresponding to the positions at first preset positions of a first substrate, a second substrate and a third substrate, and respectively manufacturing a plurality of second through holes corresponding to the positions at second preset positions of the second substrate and the third substrate; respectively preparing a first groove and a second groove corresponding to the first substrate and the third substrate in position, wherein a plurality of first through holes are arranged around the corresponding first groove or second groove; respectively preparing a switching support structure in the grooves at the two ends of the second groove, arranging a third through hole in each switching support structure, preparing a fourth through hole at the position corresponding to the third through hole in the second groove, and preparing a bonding pad in the corresponding area of the switching support structure on the lower surface of the third substrate; preparing a coaxial core on a second substrate; the first substrate, the second substrate and the third substrate are bonded in sequence to obtain the micro-delay line chip with the micro-coaxial structure, and the coaxial core (transmission line) in the micro-delay line chip is prepared in different structural forms such as turning, winding or stacking, so that the length of the transmission line can be controlled, the delay amount of the chip can be adjusted, and the loss is reduced. The micro delay line chip with the micro coaxial structure can be integrated by increasing the longitudinal thickness without increasing the plane area, so that the problems of large volume and incapability of integration in the delay line technology in the prior art can be solved. In addition, the micro-delay wire core sheet with the micro-coaxial structure can reduce temperature drift and improve the performance of the chip.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A manufacturing method of a micro delay line chip with a micro coaxial structure is characterized by comprising the following steps:
respectively preparing a plurality of first through holes corresponding to positions at first preset positions of a first substrate, a second substrate and a third substrate, and respectively preparing a plurality of second through holes corresponding to positions at second preset positions of the second substrate and the third substrate, wherein the first preset positions are different from the second preset positions;
respectively preparing a first groove and a second groove corresponding to the first substrate and the third substrate in position, wherein the plurality of first through holes are arranged around the corresponding first groove or second groove;
preparing a switching support structure in each of the grooves at the two ends of the second groove, wherein a third through hole is arranged in each switching support structure, a fourth through hole is prepared at a position corresponding to the third through hole in the second groove, a bonding pad is prepared in a region corresponding to the switching support structure on the lower surface of the third substrate, and the lower surface of the third substrate is a surface corresponding to the second groove;
preparing a coaxial core on a second substrate;
and sequentially bonding the first substrate, the second substrate and the third substrate, and enabling the positions of the first through holes on the substrates to correspond to each other, the positions of the first groove and the second groove and the positions of the notches to correspond to each other respectively, wherein the coaxial core is positioned in a cavity formed by the first groove and the second groove.
2. The method for manufacturing a micro delay line chip of a micro coaxial structure according to claim 1, wherein the preparing of the coaxial core on the second substrate comprises:
etching a plurality of fifth through holes on the second substrate by adopting a DRIE (deep etching) or wet etching method, so that the second substrate forms a structure comprising a hollow first silicon wafer, a plurality of silicon beams and a coaxial core, wherein the coaxial core is positioned in the first silicon wafer, two ends of the coaxial core are respectively connected with an O bend of the first silicon wafer, and the silicon beams which are arranged at intervals are respectively positioned at two sides of the coaxial core and used as supporting beams of the coaxial core.
3. The method for manufacturing a micro delay line chip of a micro coaxial structure according to claim 2, further comprising, after the preparing the coaxial core structure on the second substrate:
and electroplating a first metal layer on the upper surface and the lower surface of the first silicon wafer, the inner side of the first silicon wafer, the outer surface of the part except the joint part with the preset length away from the two ends of the coaxial core body, the interiors of the fifth through holes, the interiors of the first through holes and the second through holes on the second substrate.
4. The method of claim 2, wherein the first through holes, the second through holes, the third through holes, the fourth through holes, and the fifth through holes are circular, rectangular, or square, and the hole wall is perpendicular to the ground plane or has an inclination angle with the ground plane.
5. The method for manufacturing a micro delay line chip of a micro coaxial structure according to claim 1, wherein the width and depth of the first groove and the second groove are determined according to the frequency of the transmission signal of the coaxial core;
the etching depth of the first groove and the second groove is adjusted according to the etching process time, and the groove wall is perpendicular to the ground plane or an included angle is formed between the groove wall and the ground plane.
6. The method for manufacturing the micro delay line chip of the micro coaxial structure according to claim 1 or 5, wherein the second recess comprises a transfer recess for disposing the transfer support structure and a third recess except for the corresponding recess of the transfer support structure; the side length of the switching groove in the direction vertical to the signal transmission direction is larger than that of the third groove in the direction vertical to the signal transmission direction.
7. The method for manufacturing a micro delay line chip of a micro coaxial structure according to claim 3, further comprising:
electroplating a second metal layer on the lower surface of the first substrate, the groove wall of the first groove and the interiors of the first through holes on the first substrate, wherein the lower surface of the first substrate is the surface where the first groove is located;
and electroplating a third metal layer on the upper surface of the third substrate, the preset position of the lower surface of the third substrate, the preset position of the upper surface of the transfer support structure, the inside of the first through holes, the inside of the second through holes, the inside of the third through holes and the inside of the fourth through holes on the third substrate, wherein the preset position of the lower surface of the third substrate is an area except for the corresponding area of the transfer support structure, the preset position of the upper surface of the transfer support structure is the position around the third through holes, and the upper surface of the third substrate is the surface where the second groove is located.
8. The method of claim 7, wherein the electroplating a second metal layer on the bottom surface of the first substrate, on the walls of the first recess, and inside the first vias on the first substrate comprises:
preparing a seed layer on the lower surface of the first substrate, the groove wall of the first groove and the insides of the first through holes on the first substrate by adopting a sputtering process;
coating photoresist on the seed layer, transferring a preset pattern onto the photoresist, and photoetching according to the preset pattern;
electroplating the photoetching area on the photoresist to thicken the pattern of the exposed area;
removing the photoresist outside the electroplating area;
and removing the seed layer to form a second metal layer comprising the circuit structure.
9. The method for manufacturing the micro delay line chip of the micro coaxial structure according to claim 1, wherein the preparing of the bonding pad on the lower surface of the third substrate comprises:
depositing a dielectric layer on the lower surface of the third substrate in the region corresponding to the switching support structure;
and preparing the bonding pad on the dielectric layer by adopting a chemical deposition, sputtering, evaporation or electroplating mode.
10. The method for manufacturing the micro delay line chip of the micro coaxial structure according to claim 7, wherein the first metal layer, the second metal layer and the third metal layer are made of the same metal.
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