CN111883579B - Junction-free field effect transistor and manufacturing method thereof - Google Patents
Junction-free field effect transistor and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
A junction-free field effect transistor comprising a junction-free nanowire comprising a source region, a channel region and a drain region defined sequentially along an axis direction thereof; a gate dielectric layer is fully covered on the peripheral surface of the channel region, and a gate electrode layer is fully covered on the peripheral surface of the gate dielectric layer; because the source dielectric layer and the drain dielectric layer of the junction-free field effect transistor are respectively positioned on the end face of the source region and the end face of the drain region, when the device works, the contact position of metal and semiconductor body silicon is closer to the channel, so that the source-drain resistance is reduced, the on-state current of the device is greatly increased, the fluctuation of the electrical characteristics of the device caused by edge roughness is further suppressed, and the stability of the electrical characteristics of the device is improved.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit application devices, in particular to a junction-free field effect transistor and a manufacturing method thereof.
Background
MOS devices follow 'Moore' law, feature sizes are continuously scaled down, and defects of MOS field effect transistor devices based on PN junctions are more and more obvious: for example, in order to reduce the size of the device, the source-drain distance of the device is continuously shortened, source-drain punch-through is caused, short channel effect is generated, the gate control capability of the device is deteriorated, and the performance and reliability of the device are seriously degraded; in the prior art, a method for manufacturing an ultra-steep PN junction is proposed to prevent source-drain punch-through so as to avoid short channel effect, but because doping atoms are difficult to statistically distribute and are easy to diffuse, the ultra-steep PN junction is extremely difficult to manufacture in a nano scale range, so that the method has high manufacturing cost and low practicability.
In order to overcome the difficult surmounting obstacle of the junction field effect transistor device in the nanoscale range, a junction-free nanowire field effect transistor is provided. There are two types of nanowire field effect transistor structures that are commonly used at present, one is a traditional doped type device without junction; the other is a junction-free device based on a charge-plasma structure.
The first conventional junction-free device relies on heavily doping the inside of the source and drain regions, and uses the gate bias voltage to change the electric field strength perpendicular to the conductive channel, so that majority carriers in the channel are accumulated or exhausted, and the channel conductance is modulated to control the channel current. The working principle of the traditional doped junction-free device is closely related to the doping concentration, so that the traditional doped junction-free device is very easily influenced by the fluctuation of the doping process, the doping concentration is inconsistent, the stability of the electrical performance of the structural device is influenced, and the application of the structural device in a circuit is limited.
The second type of non-junction device based on the charge-plasma structure eliminates the conventional doping-based working mode of the doped non-junction device, and the structure of the non-junction device based on the charge-plasma structure comprises a non-junction nanowire which is defined as a source region, a channel region and a drain region along the non-junction nanowire; the outer surfaces of the source region and the drain region are fully covered with a source drain metal layer, and a source drain dielectric layer is arranged between the source region and the drain region and between the source drain metal layer and the drain metal layer, and the working principle of the device is as follows: the type of the transistor is regulated by controlling work functions of the source-drain metal layer and the gate metal layer, carriers are induced in the source-drain region through the source-drain metal layer, the metal layer responsible for inducing the carriers is separated from bulk silicon (i.e. the junction-free nanowire) by a source-drain medium, and a carrier passage is formed at the position, which is not covered by the source-drain medium layer, on the surface of the source-drain region, so that the device works. Because the bulk silicon doping concentration of the device is very low, the device not only inhibits the influence of a doping process, but also can achieve the required function, and therefore, the junction-free device based on the charge-plasma structure becomes the main stream structure of the junction-free nanowire field effect transistor.
However, the related research results show that the on-state current of the current non-junction device based on the charge-plasma structure is smaller, and the electrical property difference is large due to different individuals, so that the stability of the electrical property of the device needs to be improved.
Disclosure of Invention
The invention provides a junction-free field effect transistor and a manufacturing method thereof, which can improve the stability of the electrical characteristics of a device.
According to a first aspect, an embodiment provides a junction-free field effect transistor, comprising:
The device comprises a non-junction nanowire, a first electrode and a second electrode, wherein the non-junction nanowire comprises a source region, a channel region and a drain region which are sequentially defined along the axis direction of the non-junction nanowire;
A gate dielectric layer is fully covered on the peripheral surface of the channel region, and a gate electrode layer is fully covered on the peripheral surface of the gate dielectric layer;
An active dielectric layer and a source electrode layer are sequentially formed on the outer surface of the source region, the source dielectric layer is formed on the end face of the source region, and the source electrode layer is formed on the outer peripheral surface of the source region and the source dielectric layer and completely covers the outer surface of the source region and the source dielectric layer;
the outer surface of the drain region is sequentially provided with a drain dielectric layer and a drain electrode layer, the drain dielectric layer is formed on the end face of the drain region, and the drain electrode layer is formed on the outer peripheral surface of the drain region and the drain dielectric layer and completely covers the outer surface of the drain region and the drain dielectric layer.
Optionally, an isolation layer is arranged between the source electrode layer and the gate electrode layer; an isolation layer is provided between the drain electrode layer and the gate electrode layer.
Optionally, the source region, the channel region and the drain region are axisymmetric.
Optionally, the channel region is in a shape of a cylinder or a prism, and the source region and the drain region are in a shape of a cylinder, a prism or a truncated cone, wherein at the joint of the source region and the channel region, the cross-sectional shape of the source region is the same as the cross-sectional shape of the channel region; at the junction of the drain region and the channel region, the cross-sectional shape of the drain region is the same as the cross-sectional shape of the channel region.
According to a second aspect, there is provided in one embodiment a method of manufacturing a junction-free field effect transistor, the method comprising: forming a junction-free nanowire, and sequentially defining an active region, a channel region and a drain region along the axis direction of the junction-free nanowire;
forming a dielectric layer, wherein the dielectric layer comprises a gate dielectric layer, a source dielectric layer and a leakage dielectric layer, the gate dielectric layer covers the peripheral surface of the channel region, the source dielectric layer is formed on the end face of the source region, and the leakage dielectric layer is formed on the end face of the drain region;
A gate electrode layer formed on an outer peripheral surface of the gate dielectric layer, a source electrode layer formed on a source dielectric layer surface and an outer surface of the source region not covered with the source dielectric layer, and a drain electrode layer formed on a drain dielectric layer surface and an outer surface of the drain region not covered with the drain dielectric layer are formed.
Optionally, forming the source dielectric layer and the drain dielectric layer includes: depositing an initial source dielectric layer on the outer surface of the source region, and depositing an initial leakage dielectric layer on the outer surface of the drain region;
forming a patterned photoresist;
and etching the source dielectric layer on the outer peripheral surface of the source region and the leakage dielectric on the outer peripheral surface of the drain region by taking the patterned photoresist as a mask, and reserving the source dielectric layer on the end surface of the source region and the leakage dielectric layer on the end surface of the drain region.
Optionally, before the forming of the knotless nanowire, the method further includes:
providing a silicon substrate, and performing a preliminary doping process and an annealing process on the silicon substrate;
Etching the silicon substrate with preset thickness to form a knotless nanowire, wherein the channel region of the knotless nanowire is cylindrical or prismatic in shape, and the source region and the drain region are cylindrical, prismatic or circular truncated cone in shape, wherein the cross section shape of the source region is the same as the cross section shape of the channel region at the joint of the source region and the channel region; at the junction of the drain region and the channel region, the cross-sectional shape of the drain region is the same as the cross-sectional shape of the channel region.
Optionally, after the forming of the knotless nanowire, the method further includes: and forming side wall isolation layers on two sides of the gate dielectric layer through a thermal oxidation process.
Optionally, the gate dielectric layer is formed by a dry oxygen oxidation process.
Optionally, the gate dielectric layer material is silicon dioxide; the source dielectric layer and the drain dielectric layer are made of hafnium oxide.
According to the junction-free field effect transistor and the manufacturing method thereof, the source dielectric layer and the drain dielectric layer of the junction-free field effect transistor are respectively positioned on the end face of the source region and the end face of the drain region, so that when the device works, the contact position of metal and semiconductor body silicon is closer to a channel, the source-drain resistance is reduced, the on-state current of the device is greatly increased, the fluctuation influence of the electrical characteristics of the device caused by edge roughness is weakened, and the stability of the electrical characteristics of the device is improved.
Drawings
Fig. 1 is a schematic diagram of a junction-free field effect transistor according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for fabricating a junction-free field effect transistor according to an embodiment of the present application;
fig. 3-7 are schematic diagrams illustrating a method for manufacturing a junction-free nanowire field effect transistor according to an embodiment of the present application;
FIG. 8A is a diagram illustrating a comparison of on-state current characteristics of a junction-less field effect transistor according to an embodiment of the present application and a prior art;
FIG. 8B is a schematic diagram illustrating a comparison of sub-threshold swing characteristics of a junction-less field effect transistor according to an embodiment of the present application and a prior art;
FIG. 8C is a graph showing the comparison of the off-state current of a junction-free field effect transistor according to an embodiment of the present application with the off-state current of the prior art;
Fig. 8D is a schematic diagram illustrating comparison between threshold voltage characteristics of a junction-free field effect transistor according to an embodiment of the present application and threshold voltage characteristics of a prior art.
Detailed Description
The application will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, related operations of the present application have not been shown or described in the specification in order to avoid obscuring the core portions of the present application, and may be unnecessary to persons skilled in the art from a detailed description of the related operations, which may be presented in the description and general knowledge of one skilled in the art.
Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated.
As known from the background art, the electrical performance of the junction-free device based on the charge-plasma structure in the prior art is found to be greatly different in use and test, and the stability of the electrical characteristics of the device is not high, so that the practicability of the existing junction-free device based on the charge-plasma structure is lower.
It has been found that, in any structure of semiconductor device, there must be photolithography, etching or deposition process in the manufacturing process, and these process techniques may cause the surface of the conductive channel or the surface of some dielectric materials to be not smooth, and this non-smooth may cause rough edges in the device. The electrical performance of the semiconductor device is unstable due to the influence of the edge roughness, however, the edge roughness is unavoidable in the semiconductor fabrication, and the stability of the electrical performance of the semiconductor device can be improved by reducing the sensitivity of the semiconductor device to the edge roughness through research.
The invention provides a junction-free field effect transistor based on a charge-plasma structure, which is characterized in that a source dielectric layer and a drain dielectric layer are respectively arranged on the end face of a source region and the end face of a drain region, so that when the device works, the contact position of metal and semiconductor body silicon is closer to a channel, the movement distance of generated carriers is reduced, the resistance between the source and the drain is reduced, the on-state current of the device can be greatly increased, the fluctuation of edge roughness on the electrical characteristics of the device can be ignored, the sensitivity of the semiconductor device on the edge roughness is reduced, and the electrical characteristics of the semiconductor device are more stable.
Referring to fig. 1, a junction-free field effect transistor of the present embodiment includes a junction-free nanowire 100, where the junction-free nanowire 100 includes a source region 101, a channel region 102, and a drain region 103 sequentially defined along an axis direction thereof; a gate dielectric layer 202 entirely covering the outer peripheral surface of the channel region 102, and a gate electrode layer 302 entirely covering the outer peripheral surface of the gate dielectric layer; an active dielectric layer 201 and a source electrode layer 301 are sequentially formed on the outer surface of the source region 101, the source dielectric layer 201 is formed on the end surface of the source region 101, and the source electrode layer 301 is formed on the outer peripheral surface of the source region 101 and the source dielectric layer 201 and entirely covers the outer surface of the source region 101 and the source dielectric layer 201; the outer surface of the drain region 103 is sequentially formed with a drain dielectric layer 203 and a drain electrode layer 303, the drain dielectric layer 203 is formed on the end surface of the drain region 103, and the drain electrode layer 303 is formed on the outer peripheral surface of the drain region 103 and the drain dielectric layer 203 and entirely covers the outer surface of the drain region 103 and the drain dielectric layer 203.
In this embodiment, the junction-free nanowire 100 may be understood as a strip-shaped single crystal silicon rod of a transistor on an SOI substrate, which may include a source region 101, a channel region 102, and a drain region 103. In some embodiments, the material of the junction-free nanowires 100 may be germanium, silicon, gallium arsenide, gallium phosphide, or the like.
In the junction-free nanowire field effect transistor provided in this embodiment, since the source dielectric layer 201 and the drain dielectric layer 203 are respectively located at the end face of the source region 101 and the end face of the drain region 103, when the device is in operation, the positions of the source electrode layer 301 and the drain electrode layer 303, which are responsible for inducing carriers, in contact with the junction-free nanowire 100 (bulk silicon of the semiconductor) are closer to the channel region 102, so that the resistance between the source and the drain is reduced, the on-state current of the semiconductor device is greatly increased, and the fluctuation of the electrical characteristics of the semiconductor device caused by the rough edge is further suppressed, that is, the sensitivity of the semiconductor device to the edge roughness is reduced, and the electrical characteristics of the semiconductor device are more stable.
In this embodiment, an isolation layer is disposed between the source electrode layer 303 and the gate electrode layer 302; an isolation layer is provided between the drain electrode layer 301 and the gate electrode layer 302.
In this embodiment, the source region 101, the channel region 102 and the drain region 103 are axisymmetric.
In this embodiment, the source region 101, the drain region 103 and the channel region 102 are all cylindrical in shape, and the cross-sectional area of the source region 101 and the cross-sectional area of the channel region 102 are the same at the junction of the source region 101 and the channel region 102; at the junction of the drain region 103 and the channel region 102, the cross-sectional shape of the drain region 103 is the same size as the cross-sectional area of the channel region 102.
In some embodiments, the shape of the channel region 102 may be a cylinder or a polygon, and the shape of the source region 101 and the drain region 103 may be a cylinder, a prism, or a truncated cone, where, at the connection between the source region 101 and the channel region 102, the cross-sectional shape of the source region 101 and the cross-sectional shape of the channel region 102 are the same; at the junction of the drain region 103 and the channel region 102, the cross-sectional shape of the drain region 103 is the same as the cross-sectional shape of the channel region 102.
The application also provides a method for manufacturing the junction-free nanowire field effect transistor, please refer to fig. 2 in combination, fig. 2 is a flowchart of a method for manufacturing the junction-free nanowire field effect transistor according to the embodiment. The method comprises the following steps:
In step S1, a junction-free nanowire 100 is formed, and an active region 101, a channel region 102 and a drain region 103 are sequentially defined along an axis direction of the junction-free nanowire.
Process of forming the junction-free nanowire 100 referring to fig. 3 to 4, a silicon substrate 11 is first provided, and the silicon substrate 11 may be subjected to a preliminary doping process and an annealing process in some embodiments. The preliminary doping concentration may be such that the channel region 102 of the device has a certain doping, for example, the doping concentration is less than 1×10 19cm-3, and the electrical performance of the device may be improved by reducing the resistivity of the junction-free nanowire 100 through the preliminary doping process.
Referring to fig. 4, the silicon substrate 11 is etched to a predetermined thickness, and the junction-free nanowire 100 is formed.
In some embodiments, the shape of the channel region 102 may be a cylinder or a prism, the shape of the source region 101 and the drain region 103 may be a cylinder, a prism, or a truncated cone, and, at the junction of the source region 101 and the channel region 102, the cross-sectional shape of the source region 101 is the same as the cross-sectional shape of the channel region 102; at the junction of the drain region 103 and the channel region 102, the cross-sectional shape of the drain region 103 is the same as the cross-sectional shape of the channel region 102.
In step S2, a dielectric layer is formed, and the dielectric layer includes a gate dielectric layer 202, a source dielectric layer 201, and a drain dielectric layer 203, wherein the gate dielectric layer 202 is covered on the outer peripheral surface of the channel region 102, the source dielectric layer 201 is formed on the end face of the source region 101, and the drain dielectric layer 203 is formed on the end face of the drain region 103.
In this embodiment, the step of forming the source dielectric layer 201 and the drain dielectric layer 203 includes:
Referring to fig. 5, an initial source dielectric layer 211 is deposited on the outer surface of the source region 101 and an initial drain dielectric layer 213 is deposited on the outer surface of the drain region 103;
and forming a patterned photoresist, wherein the patterned photoresist can be negative photoresist or positive photoresist.
Referring to fig. 6, with the patterned photoresist as a mask, a portion of the initial source dielectric layer on the outer peripheral surface of the source region 101 and a portion of the initial drain dielectric on the outer peripheral surface of the drain region 102 are etched away, so as to form a source dielectric layer 201 on the end surface of the source region 101 and a drain dielectric layer 203 on the end surface of the drain region 103.
The gate dielectric layer 202, the source dielectric layer 301, and the drain dielectric layer 303 are oxides.
In this embodiment, the gate dielectric layer 202 is formed by a dry-oxygen oxidation method, the material of the gate dielectric layer 202 is silicon dioxide, and the material of the source dielectric layer 301 and the drain dielectric layer 303 is hafnium dioxide.
In this embodiment, the source dielectric layer 201 and the drain dielectric layer 203 are formed after the gate dielectric layer 202 is formed, and in other embodiments, the source dielectric layer 201 and the drain dielectric layer 203 may be formed before the gate dielectric layer 202 is formed.
Note that before forming the initial source dielectric layer 211 and the initial drain dielectric layer 213, the sidewall spacers 400 need to be formed on both sides of the reserved gate electrode layer. In this embodiment, after the junction-free nanowires are formed, the sidewall spacers 400 are formed on both sides of the gate dielectric layer 202 by a thermal oxidation process.
In step S3, a gate electrode layer 302, a source electrode layer 301, and a drain electrode layer 303 are formed. Referring to fig. 7, the gate electrode layer 302 is formed on the outer circumferential surface of the gate dielectric layer 202, the source electrode layer 301 is formed on the surface of the source dielectric layer 201 and the outer surface of the source region 101 not covered with the source dielectric layer 201, and the drain electrode layer 303 is formed on the surface of the drain dielectric layer 203 and the outer surface of the drain region 103 not covered with the drain dielectric layer 203.
In this embodiment, the gate electrode layer 302, the source electrode layer 301, and the drain electrode layer 303 are formed by a deposition method.
After the non-junction nanowire field effect transistor with the structure is adopted, the inventor discovers that the on-state current of the non-junction nanowire field effect transistor is greatly improved through testing, and in addition, the influence of the edge roughness of the source-drain part on the device characteristic is reduced. Based on the above-mentioned non-junction nanowire field effect transistor and the manufacturing method thereof, a comparison graph of the electrical performance of the non-junction nanowire field effect transistor of the present application and the Charge-plasma non-junction nanowire field effect transistor in the prior art is also provided.
In this embodiment, the junction-free nanowire field effect transistor of the present application may be referred to as a terminal-side type Charge-plasma nanowire field effect transistor, and by fixing parameters of the prior art Charge-plasma junction-free nanowire field effect transistor structure and the terminal-side type Charge-plasma nanowire field effect transistor of the present application, the fixed parameters include: both devices were 5×10 17cm-3 silicon substrate material with doping concentration, i.e. the doping concentration of the channel region was 5×10 17cm-3, the device width diameter was 8nm, the thickness of the source and drain dielectric layers was 2nm, and the material was hafnium oxide. The work function of the gate electrode layer was 4.77eV, and the work functions of the source electrode layer and the drain electrode layer were 3.9eV.
It should be noted that the junction-free nanowire field effect transistor is obtained based on Sentaurus TCAD software simulation research.
In this embodiment, 50 groups of conventional Charge-plasma junction-free nanowire field effect transistors with edge roughness considered are randomly generated by using a gaussian model, and are simulated to obtain corresponding transfer characteristic curves, and meanwhile, corresponding end-face type Charge-plasma nanowire field effect transistors of the present application are generated according to the same 50 groups of edge roughness morphologies corresponding to the conventional Charge-plasma junction-free nanowire field effect transistors, and are simulated to obtain corresponding transfer characteristic curves. By comparing the transfer characteristic curves of the conventional Charge-plasma junction-free nanowire field effect transistor and the end-face Charge-plasma nanowire field effect transistor, it is known that the electrical characteristics of the conventional Charge-plasma junction-free nanowire field effect transistor and the end-face Charge-plasma nanowire field effect transistor have fluctuations due to the existence of edge roughness.
Referring to fig. 8A-8D, in this embodiment, the fluctuation of the electrical characteristics of the conventional double-gate Charge-Plasma nanowire field effect transistor and the end-face Charge-Plasma nanowire field effect transistor are extracted from the simulation result, and a fluctuation distribution diagram of the electrical characteristics is drawn. FIG. 8A is a graph showing the comparison of on-state current characteristics of an end-face Charge-Plasma nanowire field effect transistor and a conventional Charge-Plasma nanowire field effect transistor; FIG. 8B is a schematic diagram showing the subthreshold swing characteristics of an end-face Charge-Plasma nanowire field effect transistor versus a conventional Charge-Plasma nanowire field effect transistor; FIG. 8C is a graph showing the comparison of the off-state current characteristics of an end-face Charge-Plasma nanowire field effect transistor and a double-gate Charge-Plasma nanowire field effect transistor; fig. 8D is a schematic diagram showing the comparison of threshold voltage characteristics of the end-face Charge-Plasma nanowire field effect transistor and the conventional Charge-Plasma nanowire field effect transistor. The influence of the edge roughness on the device needs to be quantified, in this embodiment, the quantification mode is that the standard deviation delta is divided by the average value mu to represent the influence on the fluctuation of the electrical characteristics of the device, and the influence on the fluctuation of the electrical characteristics of the device includes the influence on the electrical characteristics such as on-state current, subthreshold swing, leakage current, threshold voltage and the like; for example, in the present embodiment, in the conventional device, the average value μ=1.32e-4A of the on-state current at the same edge roughness, the influence of the fluctuation of the on-state current characteristics of the conventional device is the ratio of the standard deviation of the on-state current to the average value, i.e., δ/μ=31.97%; in the end face device of the present application, the average value at the same edge roughness was μ=2.84E-4A, and the influence on the on-state current characteristic fluctuation of the end face device was δ/μ=21.59%. It can be seen that under the condition of the same edge roughness, the on-state current of the end face device is larger, and the influence on the on-state current characteristic fluctuation of the end face device is smaller. By combining fig. 8A-8D, it can be known that the end-face Charge-Plasma nanowire field effect transistor provided by the application can maintain good characteristics of subthreshold swing, leakage current and threshold voltage, so that performance deterioration of the device in the size reduction process is avoided, and meanwhile, on-state current of the device is improved. The end face Charge-Plasma nanowire field effect transistor can better reduce on-state current fluctuation caused by rough edges, and better improve the stability of the transistor.
The foregoing description of the invention has been presented for purposes of illustration and description, and is not intended to be limiting. Several simple deductions, modifications or substitutions may also be made by a person skilled in the art to which the invention pertains, based on the idea of the invention.
Claims (10)
1. A junction-free field effect transistor, comprising:
The device comprises a non-junction nanowire, a first electrode and a second electrode, wherein the non-junction nanowire comprises a source region, a channel region and a drain region which are sequentially defined along the axis direction of the non-junction nanowire;
A gate dielectric layer is fully covered on the peripheral surface of the channel region, and a gate electrode layer is fully covered on the peripheral surface of the gate dielectric layer;
The outer surface of the source region is sequentially provided with an active dielectric layer and a source electrode layer, the source dielectric layer is only formed on the end surface of the source region, and the source electrode layer is formed on the outer peripheral surface of the source region and the source dielectric layer and completely covers the outer surface of the source region and the source dielectric layer;
the outer surface of the drain region is sequentially provided with a drain dielectric layer and a drain electrode layer, the drain dielectric layer is only formed on the end face of the drain region, and the drain electrode layer is formed on the outer peripheral surface of the drain region and the drain dielectric layer and completely covers the outer surface of the drain region and the drain dielectric layer.
2. The junction-free field effect transistor of claim 1 wherein an isolation layer is provided between the source electrode layer and the gate electrode layer; an isolation layer is provided between the drain electrode layer and the gate electrode layer.
3. The junction-free field effect transistor of claim 1 wherein the source region, channel region and drain region are axisymmetric.
4. The junction-free field effect transistor of claim 3 wherein the channel region is cylindrical or prismatic in shape and the source and drain regions are cylindrical, prismatic or frustoconical in shape, wherein the cross-sectional shape of the source region and the cross-sectional shape of the channel region are the same at the junction of the source region and the channel region; at the junction of the drain region and the channel region, the cross-sectional shape of the drain region is the same as the cross-sectional shape of the channel region.
5. A method of fabricating a junction-less field effect transistor, the method comprising:
Forming a junction-free nanowire, and sequentially defining a source region, a channel region and a drain region along the axis direction of the junction-free nanowire;
Forming a dielectric layer including a gate dielectric layer, a source dielectric layer and a drain dielectric layer, wherein the gate dielectric layer covers an outer peripheral surface of the channel region, the source dielectric layer is formed only on an end face of the source region, and the drain dielectric layer is formed only on an end face of the drain region;
A gate electrode layer formed on an outer peripheral surface of the gate dielectric layer, a source electrode layer formed on a source dielectric layer surface and an outer surface of the source region not covered with the source dielectric layer, and a drain electrode layer formed on a drain dielectric layer surface and an outer surface of the drain region not covered with the drain dielectric layer are formed.
6. The method of manufacturing of claim 5, wherein forming the source dielectric layer and the drain dielectric layer comprises: depositing an initial source dielectric layer on the outer surface of the source region, and depositing an initial leakage dielectric layer on the outer surface of the drain region;
forming a patterned photoresist;
and etching the source dielectric layer on the outer peripheral surface of the source region and the leakage dielectric on the outer peripheral surface of the drain region by taking the patterned photoresist as a mask, and reserving the source dielectric layer on the end surface of the source region and the leakage dielectric layer on the end surface of the drain region.
7. The method of manufacturing of claim 5, wherein prior to forming the junction-free nanowires, further comprising:
providing a silicon substrate, and performing a preliminary doping process and an annealing process on the silicon substrate;
Etching the silicon substrate with preset thickness to form a knotless nanowire, wherein the channel region of the knotless nanowire is cylindrical or prismatic in shape, and the source region and the drain region are cylindrical, prismatic or circular truncated cone in shape, wherein the cross section shape of the source region is the same as the cross section shape of the channel region at the joint of the source region and the channel region; at the junction of the drain region and the channel region, the cross-sectional shape of the drain region is the same as the cross-sectional shape of the channel region.
8. The method of manufacturing of claim 5, further comprising, after the forming of the junction-free nanowires:
and forming side wall isolation layers on two sides of the gate dielectric layer through a thermal oxidation process.
9. The method of manufacturing of claim 5, wherein the gate dielectric layer is formed by a dry oxygen oxidation process.
10. The method of manufacturing of claim 5, wherein the gate dielectric layer material is silicon dioxide; the source dielectric layer and the drain dielectric layer are made of hafnium oxide.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102004043902A1 (en) * | 2004-09-10 | 2006-03-16 | Infineon Technologies Ag | Field effect transistor for dynamic random access memory cell, has gate dielectric layer with terminal dielectric layer having thickness greater than gate dielectric layer-thickness |
| CN104638014A (en) * | 2015-02-10 | 2015-05-20 | 清华大学 | Junction-free multi-doped field effect transistor |
| CN107068734A (en) * | 2017-01-24 | 2017-08-18 | 北京大学深圳研究生院 | One kind is without junction field effect transistor |
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| WO2018094205A1 (en) * | 2016-11-18 | 2018-05-24 | Acorn Technologies, Inc. | Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102004043902A1 (en) * | 2004-09-10 | 2006-03-16 | Infineon Technologies Ag | Field effect transistor for dynamic random access memory cell, has gate dielectric layer with terminal dielectric layer having thickness greater than gate dielectric layer-thickness |
| CN104638014A (en) * | 2015-02-10 | 2015-05-20 | 清华大学 | Junction-free multi-doped field effect transistor |
| CN107068734A (en) * | 2017-01-24 | 2017-08-18 | 北京大学深圳研究生院 | One kind is without junction field effect transistor |
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