CN111883579A - Junction-free field effect transistor and manufacturing method thereof - Google Patents
Junction-free field effect transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN111883579A CN111883579A CN202010796589.6A CN202010796589A CN111883579A CN 111883579 A CN111883579 A CN 111883579A CN 202010796589 A CN202010796589 A CN 202010796589A CN 111883579 A CN111883579 A CN 111883579A
- Authority
- CN
- China
- Prior art keywords
- dielectric layer
- source
- region
- drain
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 239000002070 nanowire Substances 0.000 claims abstract description 67
- 230000005669 field effect Effects 0.000 claims abstract description 46
- 230000002093 peripheral effect Effects 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 16
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000000969 carrier Substances 0.000 description 4
- 238000011160 research Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A junctionless field effect transistor comprises a junctionless nanowire, wherein the junctionless nanowire comprises a source region, a channel region and a drain region which are sequentially defined along the axis direction of the junctionless nanowire; the peripheral surface surrounding the channel region is completely covered with a gate dielectric layer, and the peripheral surface surrounding the gate dielectric layer is completely covered with a gate electrode layer; because the source dielectric layer and the leakage dielectric layer of the JFET are respectively positioned on the end face of the source region and the end face of the drain region, when the device works, the position where the metal is in contact with the bulk silicon of the semiconductor is closer to the channel, so that the source-drain resistance is reduced, the on-state current of the device is greatly increased, the fluctuation of the electrical characteristics of the device caused by edge roughness is further inhibited, and the stability of the electrical characteristics of the device is improved.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit application devices, in particular to a junction-free field effect transistor and a manufacturing method thereof.
Background
MOS devices follow the Moore's law, the characteristic dimension is continuously scaled down in proportion, and the defects of MOS field effect transistor devices based on PN junctions are more and more obvious: for example, in order to reduce the size of the device, the source-drain distance of the device is continuously shortened, so that the source-drain punch-through is caused, a short channel effect is generated, the gate control capability of the device is poor, and the performance and reliability of the device are seriously degraded; the method for manufacturing the ultra-steep PN junction provided in the prior art prevents source and drain from penetrating through so as to avoid a short channel effect, but is extremely difficult to manufacture the ultra-steep PN junction in a nanoscale range due to the fact that doping atoms are difficult to statistically distribute, the doping atoms are easy to diffuse and the like, and the method is high in manufacturing cost and low in practicability.
In order to overcome the obstacle of the junction field effect transistor device in the nanometer scale range which is difficult to overcome, a junction-free nanowire field effect transistor is provided. At present, two types of commonly used junction-free nanowire field effect transistor structures are provided, wherein one type is a traditional doped junction-free device; the other is a junction-free device based on a charge-plasma structure.
The first conventional junction-free device relies on heavy doping in the source and drain regions, and changes the electric field intensity perpendicular to the conductive channel by using the gate bias voltage, so that the majority carriers in the channel are accumulated or depleted, thereby modulating the channel conductance to control the channel current. The working principle of the conventional doping type junction-free device is closely related to the doping concentration, so that the conventional doping type junction-free device is very easily influenced by the fluctuation of the doping process, the doping concentration is inconsistent, the stability of the electrical performance of the structural device is influenced, and the application of the structural device in a circuit is limited.
The structure of the second type of the non-junction device based on the charge-plasma structure eliminates the doping-based working mode of the traditional doping type non-junction device, and the structure of the non-junction device based on the charge-plasma structure comprises a non-junction nanowire which is defined as a source region, a channel region and a drain region along the axis of the non-junction nanowire; the outer surfaces of the source region and the drain region are fully covered with a source drain metal layer, and a source drain dielectric layer is arranged between the source region and the drain region and the source drain metal, and the working principle of the device is as follows: the type of the transistor is adjusted by controlling the work functions of the source drain metal layer and the grid metal layer, current carriers are induced in the source drain region through the source drain metal layer, the metal layer responsible for inducing the current carriers is separated from bulk silicon (namely, the junctionless nanowire) by the source drain dielectric, and a current carrier passage is formed at the position, which is not covered by the source drain dielectric layer, on the surface of the source drain region, so that the device works. Because the bulk silicon doping concentration of the device is very low, the device not only inhibits the influence of a doping process, but also can achieve the required function, and therefore, the junctionless device based on the charge-plasma structure becomes the mainstream structure of the junctionless nanowire field effect transistor.
However, the related research results show that the on-state current of the existing junction-free device based on the charge-plasma structure is small, the electrical performance of the device is greatly different due to different individuals, and the stability of the electrical characteristics of the device needs to be improved.
Disclosure of Invention
The invention provides a junction-free field effect transistor and a manufacturing method thereof, which can improve the stability of the electrical characteristics of a device.
According to a first aspect, there is provided in an embodiment a junction-less field effect transistor comprising:
the junction-free nanowire comprises a source region, a channel region and a drain region which are sequentially defined along the axis direction of the junction-free nanowire;
the peripheral surface surrounding the channel region is completely covered with a gate dielectric layer, and the peripheral surface surrounding the gate dielectric layer is completely covered with a gate electrode layer;
an active dielectric layer and a source electrode layer are sequentially formed on the outer surface of the source region, the source dielectric layer is formed on the end face of the source region, and the source electrode layer is formed on the outer peripheral surface of the source region and the source dielectric layer and completely covers the outer surface of the source region and the source dielectric layer;
and a leakage dielectric layer and a drain electrode layer are sequentially formed on the outer surface of the drain region, the leakage dielectric layer is formed on the end face of the drain region, and the drain electrode layer is formed on the peripheral surface of the drain region and the leakage dielectric layer and completely covers the outer surface of the drain region and the leakage dielectric layer.
Optionally, an isolation layer is arranged between the source electrode layer and the gate electrode layer; an isolation layer is arranged between the drain electrode layer and the gate electrode layer.
Optionally, the source region, the channel region and the drain region are axisymmetric.
Optionally, the channel region is cylindrical or prismatic, and the source region and the drain region are cylindrical, prismatic or circular truncated cone in shape, wherein at a joint of the source region and the channel region, a cross-sectional shape of the source region is the same as a cross-sectional shape of the channel region; and at the joint of the drain region and the channel region, the cross-sectional shape of the drain region is the same as that of the channel region.
According to a second aspect, an embodiment provides a method of manufacturing a junction-less field effect transistor, the method comprising: forming a junction-free nanowire, and sequentially defining an active region, a channel region and a drain region along the axis direction of the junction-free nanowire;
forming a dielectric layer, wherein the dielectric layer comprises a gate dielectric layer, a source dielectric layer and a leakage dielectric layer, the gate dielectric layer covers the peripheral surface surrounding the channel region, the source dielectric layer is formed on the end face of the source region, and the leakage dielectric layer is formed on the end face of the drain region;
and forming a gate electrode layer, a source electrode layer and a drain electrode layer, wherein the gate electrode layer is formed on the peripheral surface surrounding the gate dielectric layer, the source electrode layer is formed on the surface of the source dielectric layer and the outer surface of the source region not covered by the source dielectric layer, and the drain electrode layer is formed on the surface of the drain dielectric layer and the outer surface of the drain region not covered by the drain dielectric layer.
Optionally, the forming the source dielectric layer and the drain dielectric layer includes: depositing an initial source dielectric layer on the outer surface of the source region, and depositing an initial leakage dielectric layer on the outer surface of the drain region;
forming a patterned photoresist;
and etching the source dielectric layer on the peripheral surface of the source region and the leakage dielectric layer on the peripheral surface of the drain region by taking the patterned photoresist as a mask, and reserving the source dielectric layer on the end surface of the source region and the leakage dielectric layer on the end surface of the drain region.
Optionally, before the forming of the junction-free nanowire, the method further includes:
providing a silicon substrate, and carrying out a preliminary doping process and an annealing process on the silicon substrate;
etching the silicon substrate with a preset thickness to form a junction-free nanowire, wherein the channel region of the junction-free nanowire is cylindrical or prismatic, and the source region and the drain region are cylindrical, prismatic or circular truncated cone, and the cross section of the source region is the same as that of the channel region at the joint of the source region and the channel region; and at the joint of the drain region and the channel region, the cross-sectional shape of the drain region is the same as that of the channel region.
Optionally, after the forming of the junction-free nanowire, the method further includes: and forming side wall isolation layers on two sides of the gate dielectric layer through a thermal oxidation process.
Optionally, the gate dielectric layer is formed by dry oxygen oxidation.
Optionally, the gate dielectric layer material is silicon dioxide; the source dielectric layer and the leakage dielectric layer are made of hafnium oxide.
According to the junctionless field effect transistor and the manufacturing method thereof, the source dielectric layer and the leakage dielectric layer of the junctionless field effect transistor are respectively positioned on the end face of the source region and the end face of the drain region, so that when the device works, the position where the metal is contacted with the bulk silicon of the semiconductor is closer to the channel, the source resistance and the drain resistance are reduced, the on-state current of the device is greatly increased, the fluctuation influence of the electrical characteristics of the device caused by edge roughness is weakened, and the stability of the electrical characteristics of the device is improved.
Drawings
Fig. 1 is a schematic diagram of a jfet structure according to an embodiment of the present disclosure;
fig. 2 is a flow chart of a method for manufacturing a jfet according to an embodiment of the present disclosure;
fig. 3-7 are schematic diagrams illustrating a method for fabricating a junction-free nanowire field effect transistor according to an embodiment of the present application;
FIG. 8A is a comparison of the on-state current characteristics of a JFET according to an embodiment of the present application with those of the prior art;
fig. 8B is a schematic diagram comparing the characteristics of a jfet according to an embodiment of the present application with the characteristics of a sub-threshold swing of the prior art;
FIG. 8C is a comparison of off-state current for a JFET according to an embodiment of the present application;
fig. 8D is a comparison diagram of threshold voltage characteristics of a jfet according to an embodiment of the present application compared to the prior art.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
As can be seen from the background art, in the using and testing processes, the electrical performance difference of the junction-free device based on the charge-plasma structure in the prior art is large, and the stability of the electrical characteristics of the device is not high, so that the practicability of the junction-free device based on the charge-plasma structure in the prior art is low.
It has been found that, in any semiconductor device, there are photolithography, etching or deposition processes, which may result in the surface of the conductive channel or the surface of some dielectric material being rough, and the rough edges of the device may be caused by the rough surfaces. The electrical performance of the semiconductor device is unstable due to the influence of the edge roughness, however, the edge roughness is inevitable in the semiconductor manufacturing, and the research shows that the electrical performance stability of the semiconductor device can be improved by reducing the sensitivity of the semiconductor device to the edge roughness.
The invention provides a junctionless field effect transistor based on a charge-plasma structure, which is characterized in that a source dielectric layer and a leakage dielectric layer are respectively arranged on the end face of a source region and the end face of a drain region, so that when a device works, the contact position of metal and semiconductor bulk silicon is closer to a channel, the moving distance of a generated current carrier is reduced, the resistance between the source and the drain is reduced, the on-state current of the device can be greatly increased, the fluctuation of edge roughness on the electrical characteristics of the device can be ignored, the sensitivity of the semiconductor device on the edge roughness is reduced, and the electrical characteristics of the semiconductor device are more stable.
Referring to fig. 1, a junctionless fet of the present embodiment includes a junctionless nanowire 100, where the junctionless nanowire 100 includes a source region 101, a channel region 102 and a drain region 103 defined in sequence along an axial direction thereof; the gate dielectric layer 202 covers the peripheral surface of the channel region 102, and the gate electrode layer 302 covers the peripheral surface of the gate dielectric layer; an active dielectric layer 201 and a source electrode layer 301 are sequentially formed on the outer surface of the source region 101, the source dielectric layer 201 is formed on the end face of the source region 101, and the source electrode layer 301 is formed on the outer peripheral surface of the source region 101 and the source dielectric layer 201 and completely covers the outer surface of the source region 101 and the source dielectric layer 201; a leakage dielectric layer 203 and a drain electrode layer 303 are sequentially formed on the outer surface of the drain region 103, the leakage dielectric layer 203 is formed on the end face of the drain region 103, and the drain electrode layer 303 is formed on the outer peripheral surface of the drain region 103 and the leakage dielectric layer 203 and completely covers the outer surface of the drain region 103 and the leakage dielectric layer 203.
In this embodiment, the junction-free nanowire 100 may be understood as a single-crystal silicon bar of a transistor on an SOI substrate, which may include a source region 101, a channel region 102, and a drain region 103. In some embodiments, the material of the junction-free nanowire 100 may be germanium, silicon, gallium arsenide, gallium phosphide, or the like.
In the junction-free nanowire field effect transistor provided by this embodiment, the source dielectric layer 201 and the drain dielectric layer 203 are respectively located at the end face of the source region 101 and the end face of the drain region 103, so that when the device operates, the contact position between the source electrode layer 301 and the drain electrode layer 303, which are responsible for inducing carriers, and the junction-free nanowire 100 (bulk silicon of a semiconductor) is closer to the channel region 102, and therefore, the resistance between the source and the drain is reduced, the on-state current of the semiconductor device is greatly increased, and the fluctuation of the electrical characteristics of the semiconductor device due to the rough edge is further suppressed, that is, the sensitivity of the semiconductor device to the edge roughness is reduced, and the electrical characteristics of the semiconductor device are more stable.
In this embodiment, an isolation layer is provided between the source electrode layer 303 and the gate electrode layer 302; an isolation layer is provided between the drain electrode layer 301 and the gate electrode layer 302.
In this embodiment, the source region 101, the channel region 102, and the drain region 103 are axisymmetric.
In this embodiment, the source region 101, the drain region 103, and the channel region 102 are all cylindrical in shape, and at the joint between the source region 101 and the channel region 102, the cross-sectional area of the source region 101 is the same as the cross-sectional area of the channel region 102; at the junction of the drain region 103 and the channel region 102, the cross-sectional shape of the drain region 103 and the cross-sectional area of the channel region 102 are the same.
In some embodiments, the channel region 102 may have a cylindrical or polygonal shape, and the source region 101 and the drain region 103 have a cylindrical, prismatic or circular truncated cone shape, wherein the cross-sectional shape of the source region 101 and the cross-sectional shape of the channel region 102 are the same at the junction of the source region 101 and the channel region 102; at the junction of the drain region 103 and the channel region 102, the cross-sectional shape of the drain region 103 is the same as the cross-sectional shape of the channel region 102.
Please refer to fig. 2 in combination, and fig. 2 is a flowchart illustrating a method for manufacturing a junction-free nanowire field effect transistor according to this embodiment. The method comprises the following steps:
step S1, forming a junction-free nanowire 100, and sequentially defining an active region 101, a channel region 102, and a drain region 103 along an axial direction of the junction-free nanowire.
Process of forming junction-free nanowires 100 referring to fig. 3-4, a silicon substrate 11 is first provided, and in some embodiments, a preliminary doping process and an annealing process may be performed on the silicon substrate 11. The concentration of the preliminary doping is such that the device has a certain doping in the channel region 102, e.g. a doping concentration of less than 1 x 1019cm-3The initial doping process can reduce the resistivity of the junction-free nanowire 100, and can improve the electrical performance of the device.
Referring to fig. 4, the silicon substrate 11 is etched to a predetermined thickness to form the junction-less nanowire 100.
In some embodiments, the channel region 102 may have a cylindrical or prismatic shape, the source region 101 and the drain region 103 may have a cylindrical, prismatic or truncated cone shape, and the cross-sectional shape of the source region 101 and the cross-sectional shape of the channel region 102 are the same at the junction of the source region 101 and the channel region 102; at the junction of the drain region 103 and the channel region 102, the cross-sectional shape of the drain region 103 is the same as the cross-sectional shape of the channel region 102.
Step S2, forming a dielectric layer, where the dielectric layer includes a gate dielectric layer 202, a source dielectric layer 201, and a leakage dielectric layer 203, where the gate dielectric layer 202 covers the outer peripheral surface of the channel region 102, the source dielectric layer 201 is formed on the end surface of the source region 101, and the leakage dielectric layer 203 is formed on the end surface of the drain region 103.
In this embodiment, the step of forming the source dielectric layer 201 and the drain dielectric layer 203 includes:
referring to fig. 5, an initial source dielectric layer 211 is deposited on the outer surface of the source region 101, and an initial drain dielectric layer 213 is deposited on the outer surface of the drain region 103;
and forming a patterned photoresist, wherein the patterned photoresist can be a negative photoresist or a positive photoresist.
Referring to fig. 6, using the patterned photoresist as a mask, a portion of the initial source dielectric layer on the outer circumferential surface of the source region 101 and a portion of the initial leakage dielectric layer on the outer circumferential surface of the drain region 102 are etched away to form a source dielectric layer 201 on the end surface of the source region 101 and a leakage dielectric layer 203 on the end surface of the drain region 103.
The gate dielectric layer 202, the source dielectric layer 301 and the drain dielectric layer 303 are oxides.
In this embodiment, the gate dielectric layer 202 is formed by a dry oxygen oxidation method, the gate dielectric layer 202 is made of silicon dioxide, and the source dielectric layer 301 and the drain dielectric layer 303 are made of hafnium oxide.
In this embodiment, the source dielectric layer 201 and the drain dielectric layer 203 are formed after the gate dielectric layer 202 is formed, but in other embodiments, the source dielectric layer 201 and the drain dielectric layer 203 may be formed before the gate dielectric layer 202 is formed.
It should be noted that before forming the initial source dielectric layer 211 and the initial drain dielectric layer 213, sidewall spacers 400 need to be formed on both sides of the reserved gate electrode layer. In this embodiment, after the junction-free nanowire is formed, the sidewall spacers 400 are formed on two sides of the gate dielectric layer 202 by a thermal oxidation process.
In step S3, the gate electrode layer 302, the source electrode layer 301, and the drain electrode layer 303 are formed. Referring to fig. 7, the gate electrode layer 302 is formed on the outer peripheral surface of the gate dielectric layer 202, the source electrode layer 301 is formed on the surface of the source dielectric layer 201 and the outer surface of the source region 101 not covered by the source dielectric layer 201, and the drain electrode layer 303 is formed on the surface of the drain dielectric layer 203 and the outer surface of the drain region 103 not covered by the drain dielectric layer 203.
In this embodiment, the gate electrode layer 302, the source electrode layer 301, and the drain electrode layer 303 are formed by deposition.
After the non-junction nanowire field effect transistor with the structure is adopted, through tests, the inventor finds that the on-state current of the non-junction nanowire field effect transistor is greatly improved, and in addition, the influence of the edge roughness of a source and drain part on the device characteristics is reduced. Based on the junction-free nanowire field effect transistor and the manufacturing method thereof, a comparison graph of the electrical performance of the junction-free nanowire field effect transistor and the Charge-plasma junction-free nanowire field effect transistor in the prior art is also provided.
In this embodiment, the junction-less nanowire field effect transistor of the present application may be referred to as an end-type Charge-plasma nanowire field effect transistor, and the fixed parameters include, by fixing parameters of a Charge-plasma junction-less nanowire field effect transistor structure in the prior art and parameters of an end-type Charge-plasma nanowire field effect transistor of the present application: both devices were doped at a concentration of 5X 1017cm-3The doping concentration of the silicon substrate material, i.e. the channel region, is 5 x 1017cm-3The width diameter of the device is 8nm, the thicknesses of the source dielectric layer and the leakage dielectric layer are 2nm, and the material is hafnium oxide. The gate electrode layer had a work function of 4.77eV, and the source electrode layer and the drain electrode layer had a work function of 3.9 eV.
It should be noted that the junction-free nanowire field effect transistor in the invention is obtained based on the Sentaurus TCAD software simulation research.
In this embodiment, more than or equal to 50 groups of conventional Charge-plasma junctionless nanowire field effect transistors considering the edge roughness are randomly generated by using a gaussian model and are simulated to obtain a corresponding transfer characteristic curve, and meanwhile, corresponding end-face type Charge-plasma nanowire field effect transistors in the present application are generated according to more than or equal to 50 groups of corresponding edge roughness features and are simulated to obtain a corresponding transfer characteristic curve. By comparing the transfer characteristic graphs of the conventional Charge-plasma junctionless nanowire field effect transistor and the end-type Charge-plasma nanowire field effect transistor, it can be known that the electrical characteristics of the conventional Charge-plasma junctionless nanowire field effect transistor and the end-type Charge-plasma nanowire field effect transistor are fluctuated due to the edge roughness.
Referring to fig. 8A to 8D, in the present embodiment, fluctuation conditions of the electrical characteristics of the conventional dual-gate Charge-Plasma nanowire field effect transistor and the end-face Charge-Plasma nanowire field effect transistor are extracted from the simulation result, and a fluctuation distribution diagram of the electrical characteristics is drawn. FIG. 8A is a schematic comparison of on-state current characteristics of an end-face Charge-Plasma nanowire field effect transistor and a conventional Charge-Plasma nanowire field effect transistor; FIG. 8B is a schematic diagram comparing the subthreshold swing characteristics of an end-face Charge-Plasma nanowire field effect transistor with a conventional Charge-Plasma nanowire field effect transistor; FIG. 8C is a schematic diagram showing the comparison of the off-state current characteristics of a face-Charge-Plasma nanowire FET and a dual-gate Charge-Plasma nanowire FET; fig. 8D is a graph illustrating the comparison of the threshold voltage characteristics of the end-face Charge-Plasma nanowire field effect transistor and the conventional Charge-Plasma nanowire field effect transistor. In this embodiment, the quantization mode is to divide the standard deviation by the average value μ to represent the influence on the fluctuation of the electrical characteristics of the device, and the influence on the fluctuation of the electrical characteristics of the device includes the influence on the electrical characteristics such as on-state current, subthreshold swing, leakage current, threshold voltage, and the like; for example, in the present embodiment, in the conventional device, the average value μ of the on-state current is 1.32E-4A for the same edge roughness, and the influence on the fluctuation of the on-state current characteristics of the conventional device is the ratio of the standard deviation of the on-state current to the average value, that is,/μ is 31.97%; in the end-face device of the present application, the average value of μ is 2.84E-4A for the same edge roughness, and the influence of the fluctuation in the on-state current characteristics of the end-face device is 21.59%. It can be seen that, under the condition of the same edge roughness, the on-state current of the end-face device is larger, and the influence on the fluctuation of the on-state current characteristic of the end-face device is smaller. As can be seen from fig. 8A to 8D, the end-face Charge-Plasma nanowire field effect transistor provided in the present invention can maintain good sub-threshold swing, leakage current, and threshold voltage characteristics, thereby avoiding performance degradation of the device during size reduction, and improving on-state current of the device. Namely, the end face Charge-Plasma nanowire field effect transistor can better reduce the fluctuation of on-state current caused by edge roughness and better improve the stability of the transistor.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A junctionless field effect transistor, comprising:
the junction-free nanowire comprises a source region, a channel region and a drain region which are sequentially defined along the axis direction of the junction-free nanowire;
the peripheral surface surrounding the channel region is completely covered with a gate dielectric layer, and the peripheral surface surrounding the gate dielectric layer is completely covered with a gate electrode layer;
an active dielectric layer and a source electrode layer are sequentially formed on the outer surface of the source region, the source dielectric layer is formed on the end face of the source region, and the source electrode layer is formed on the outer peripheral surface of the source region and the source dielectric layer and completely covers the outer surface of the source region and the source dielectric layer;
and a leakage dielectric layer and a drain electrode layer are sequentially formed on the outer surface of the drain region, the leakage dielectric layer is formed on the end face of the drain region, and the drain electrode layer is formed on the peripheral surface of the drain region and the leakage dielectric layer and completely covers the outer surface of the drain region and the leakage dielectric layer.
2. The junction-less field effect transistor according to claim 1, wherein an isolation layer is provided between the source electrode layer and the gate electrode layer; an isolation layer is arranged between the drain electrode layer and the gate electrode layer.
3. The junctionless field effect transistor of claim 1, wherein the source region, the channel region, and the drain region are axisymmetric.
4. The jfet of claim 3 wherein the channel region is cylindrical or prismatic in shape and the source and drain regions are cylindrical, prismatic or frustoconical in shape, wherein the source region has a cross-sectional shape that is the same as the cross-sectional shape of the channel region at the junction of the source and channel regions; and at the joint of the drain region and the channel region, the cross-sectional shape of the drain region is the same as that of the channel region.
5. A method of fabricating a junction-less field effect transistor, the method comprising:
forming a junction-free nanowire, and sequentially defining an active region, a channel region and a drain region along the axis direction of the junction-free nanowire;
forming a dielectric layer, wherein the dielectric layer comprises a gate dielectric layer, a source dielectric layer and a leakage dielectric layer, the gate dielectric layer covers the peripheral surface surrounding the channel region, the source dielectric layer is formed on the end face of the source region, and the leakage dielectric layer is formed on the end face of the drain region;
and forming a gate electrode layer, a source electrode layer and a drain electrode layer, wherein the gate electrode layer is formed on the peripheral surface surrounding the gate dielectric layer, the source electrode layer is formed on the surface of the source dielectric layer and the outer surface of the source region not covered by the source dielectric layer, and the drain electrode layer is formed on the surface of the drain dielectric layer and the outer surface of the drain region not covered by the drain dielectric layer.
6. The method of manufacturing of claim 5, wherein forming the source dielectric layer and the drain dielectric layer comprises: depositing an initial source dielectric layer on the outer surface of the source region, and depositing an initial leakage dielectric layer on the outer surface of the drain region;
forming a patterned photoresist;
and etching the source dielectric layer on the peripheral surface of the source region and the leakage dielectric layer on the peripheral surface of the drain region by taking the patterned photoresist as a mask, and reserving the source dielectric layer on the end surface of the source region and the leakage dielectric layer on the end surface of the drain region.
7. The method of manufacturing of claim 5, wherein prior to forming the junction-free nanowire, further comprising:
providing a silicon substrate, and carrying out a preliminary doping process and an annealing process on the silicon substrate;
etching the silicon substrate with a preset thickness to form a junction-free nanowire, wherein the channel region of the junction-free nanowire is cylindrical or prismatic, and the source region and the drain region are cylindrical, prismatic or circular truncated cone, and the cross section of the source region is the same as that of the channel region at the joint of the source region and the channel region; and at the joint of the drain region and the channel region, the cross-sectional shape of the drain region is the same as that of the channel region.
8. The method of manufacturing of claim 5, wherein after the forming of the junction-free nanowire, further comprising:
and forming side wall isolation layers on two sides of the gate dielectric layer through a thermal oxidation process.
9. The manufacturing method according to claim 5, wherein the gate dielectric layer is formed by a dry oxygen oxidation method.
10. The method of manufacturing of claim 5, wherein the gate dielectric layer material is silicon dioxide; the source dielectric layer and the leakage dielectric layer are made of hafnium oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010796589.6A CN111883579B (en) | 2020-08-10 | 2020-08-10 | Junction-free field effect transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010796589.6A CN111883579B (en) | 2020-08-10 | 2020-08-10 | Junction-free field effect transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111883579A true CN111883579A (en) | 2020-11-03 |
| CN111883579B CN111883579B (en) | 2024-06-11 |
Family
ID=73210458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010796589.6A Active CN111883579B (en) | 2020-08-10 | 2020-08-10 | Junction-free field effect transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111883579B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004043902A1 (en) * | 2004-09-10 | 2006-03-16 | Infineon Technologies Ag | Field effect transistor for dynamic random access memory cell, has gate dielectric layer with terminal dielectric layer having thickness greater than gate dielectric layer-thickness |
| CN104638014A (en) * | 2015-02-10 | 2015-05-20 | 清华大学 | Junction-free multi-doped field effect transistor |
| CN107068734A (en) * | 2017-01-24 | 2017-08-18 | 北京大学深圳研究生院 | One kind is without junction field effect transistor |
| US20180145184A1 (en) * | 2016-11-18 | 2018-05-24 | Acorn Technologies, Inc. | Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height |
-
2020
- 2020-08-10 CN CN202010796589.6A patent/CN111883579B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004043902A1 (en) * | 2004-09-10 | 2006-03-16 | Infineon Technologies Ag | Field effect transistor for dynamic random access memory cell, has gate dielectric layer with terminal dielectric layer having thickness greater than gate dielectric layer-thickness |
| CN104638014A (en) * | 2015-02-10 | 2015-05-20 | 清华大学 | Junction-free multi-doped field effect transistor |
| US20180145184A1 (en) * | 2016-11-18 | 2018-05-24 | Acorn Technologies, Inc. | Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height |
| CN107068734A (en) * | 2017-01-24 | 2017-08-18 | 北京大学深圳研究生院 | One kind is without junction field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111883579B (en) | 2024-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bangsaruntip et al. | High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling | |
| US6252284B1 (en) | Planarized silicon fin device | |
| US9153657B2 (en) | Semiconductor devices comprising a fin | |
| KR100545161B1 (en) | Semiconductor device | |
| US9040364B2 (en) | Carbon nanotube devices with unzipped low-resistance contacts | |
| US9905421B2 (en) | Improving channel strain and controlling lateral epitaxial growth of the source and drain in FinFET devices | |
| US9660054B2 (en) | Tunneling field effect transistor (TFET) with ultra shallow pockets formed by asymmetric ion implantation and method of making same | |
| KR20150005584A (en) | A Method of Fabricating Tunnel Transistors with Abrupt Junctions | |
| Song et al. | Ultra-high aspect ratio InP junctionless FinFETs by a novel wet etching method | |
| WO2012159424A1 (en) | Wet etching-based method for producing silicon nanowire field effect transistor | |
| KR20100098516A (en) | A hetero-structured, inverted-t field effect transistor | |
| Liu et al. | Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates | |
| CN107068734B (en) | Junction-free field effect transistor | |
| US5432366A (en) | P-I-N MOSFET for ULSI applications | |
| US7235436B1 (en) | Method for doping structures in FinFET devices | |
| US10361284B2 (en) | Method for vertical gate-last process | |
| US20150303254A1 (en) | Semiconductor structure and a method for processing a carrier | |
| US9166025B1 (en) | Methods of forming a nanowire device with a gate-all-around-channel configuration and the resulting nanowire device | |
| US20070187758A1 (en) | SB-MOSFET (Schottky barrier metal-oxide-semiconductor field effect transistor) with low barrier height and fabricating method thereof | |
| CN111883579B (en) | Junction-free field effect transistor and manufacturing method thereof | |
| TWI628703B (en) | Gate-all-around complementary nanowire device with iii-v quantum well transistor, germanium junctionless transistor and method for making the same | |
| KR101881068B1 (en) | Reconfigurable field effect transistor and method for manufacturing reconfigurable field effect transistor | |
| CN113169221B (en) | Junction-free nanowire field effect transistor and manufacturing method thereof | |
| WO2022052045A1 (en) | Negative-capacitance junction-less nanowire field effect transistor and manufacturing method therefor | |
| US9142674B2 (en) | FINFET devices having a body contact and methods of forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |