CN111883482A - Manufacturing method of display substrate, display substrate and display device - Google Patents

Manufacturing method of display substrate, display substrate and display device Download PDF

Info

Publication number
CN111883482A
CN111883482A CN202010685703.8A CN202010685703A CN111883482A CN 111883482 A CN111883482 A CN 111883482A CN 202010685703 A CN202010685703 A CN 202010685703A CN 111883482 A CN111883482 A CN 111883482A
Authority
CN
China
Prior art keywords
layer
type
photoresist layer
insulating
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010685703.8A
Other languages
Chinese (zh)
Inventor
朱亚威
曹鑫
金兴植
王子峰
樊浩原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Mianyang BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Mianyang BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Mianyang BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202010685703.8A priority Critical patent/CN111883482A/en
Publication of CN111883482A publication Critical patent/CN111883482A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The invention discloses a manufacturing method of a display substrate, the display substrate and a display device.

Description

Manufacturing method of display substrate, display substrate and display device
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of a display substrate, the display substrate and a display device.
Background
The Low Temperature Polysilicon Oxide (LTPO) substrate is a novel display substrate, has the advantages of a Low Temperature Polysilicon (LTPS) substrate and an Oxide (Oxide) substrate, and is a main development direction of future display substrates. The LTPS substrate refers to a display substrate in which a Thin Film Transistor (TFT) in a display unit is an LTPS TFT, the oxide substrate refers to a display substrate in which a TFT in a display unit is an oxide TFT, each display unit in the LTPO substrate refers to a display substrate in which an LTPS TFT and an oxide TFT are included, and the display unit is also referred to as a subpixel.
However, in the process of manufacturing the LTPO substrate in the prior art, the manufacturing process of the LTPO substrate is complicated and the manufacturing cost is high because the manufacturing of each film layer needs to be processed by a one-step patterning process.
Disclosure of Invention
The manufacturing method of the display substrate, the display substrate and the display device provided by the embodiment of the invention can simplify the manufacturing process of the display substrate and reduce the manufacturing cost.
Therefore, an embodiment of the present invention provides a method for manufacturing a display substrate, including:
sequentially forming a first active layer, a first insulating structure, a second active layer, a second insulating layer and a source drain metal layer on a substrate; wherein the content of the first and second substances,
before the source-drain metal layer is formed, forming a first type of through hole penetrating through the second insulating layer and a second type of through hole penetrating through the first insulating structure and the second insulating layer simultaneously through a one-time composition process; the first type of via hole is used for overlapping the source and drain metal layer and the second type of active layer, and the second type of via hole is used for overlapping the source and drain metal layer and the first type of active layer.
Optionally, in the manufacturing method provided in the embodiment of the present invention, the forming a first type of via hole penetrating through the second insulating layer and a second type of via hole simultaneously penetrating through the first insulating structure and the second insulating layer by a single patterning process specifically includes:
forming a photoresist layer on the second insulating layer;
exposing and developing the photoresist layer to form a first completely removed region of the photoresist layer, a partially reserved region of the photoresist layer and a completely reserved region of the photoresist layer; the first completely removed area of the photoresist layer corresponds to the second type of through holes, and the partial reserved area of the photoresist layer corresponds to the first type of through holes;
removing the second insulating layer and part of the first insulating structure corresponding to the first completely removed area of the photoresist layer;
thinning the photoresist layer, wherein the photoresist layer in the partial reserved area of the photoresist layer is completely removed, and partial photoresist layer is reserved in the full reserved area of the photoresist layer;
removing the residual first insulating structure corresponding to the first completely removed region of the photoresist layer and the second insulating layer corresponding to the partially reserved region of the photoresist layer;
and stripping the residual photoresist layer.
Optionally, in the manufacturing method provided in the embodiment of the present invention, the display substrate includes a bending region, and the bending region corresponds to the second completely removed region of the photoresist layer;
and removing the second insulating layer and part of the first insulating structure corresponding to the bending region while removing the second insulating layer and part of the first insulating structure corresponding to the first completely removed region of the photoresist layer.
Optionally, in the manufacturing method provided in this embodiment of the present invention, while the remaining first insulating structure corresponding to the first completely removed region of the photoresist layer and the second insulating layer corresponding to the partially remaining region of the photoresist layer are removed, the remaining first insulating structure corresponding to the bent region is removed.
Optionally, in the above manufacturing method provided in an embodiment of the present invention, the thinning the photoresist layer includes:
and thinning the photoresist layer through an ashing process.
Optionally, in the manufacturing method provided in the embodiment of the present invention, the first insulating structure includes a first gate insulating layer, a first interlayer dielectric layer, and a first buffer layer, which are sequentially stacked between the first type active layer and the second type active layer, and the second insulating layer is a second interlayer dielectric layer located on a side of the second type active layer away from the substrate.
Optionally, in the manufacturing method provided in the embodiment of the present invention, after forming the first gate insulating layer and before forming the first interlayer dielectric layer, the method further includes: forming a first grid;
after the second type active layer is formed and before the second interlayer dielectric layer is formed, the method further comprises the following steps: forming a second gate insulating layer and a second gate electrode; the pattern of the second gate insulating layer is the same as the pattern of the second gate electrode.
Optionally, in the manufacturing method provided by the embodiment of the present invention, the first type of active layer is a polysilicon active layer, and the second type of active layer is an oxide active layer;
before forming the first active layer on the substrate, the method further includes: a second buffer layer is formed on the substrate base plate.
Correspondingly, the embodiment of the invention also provides a display substrate which is formed by adopting the manufacturing method provided by the embodiment of the invention.
Correspondingly, the embodiment of the invention also provides a display device which comprises the display substrate provided by the embodiment of the invention.
The embodiment of the invention has the following beneficial effects:
according to the manufacturing method of the display substrate, the display substrate and the display device, the first type of through holes and the second type of through holes are formed through the once composition process, so that compared with the process that the two types of through holes are formed through the twice composition processes in the prior art, the manufacturing process of the display substrate can be reduced by the once composition process, the manufacturing process of the display substrate is simplified, and the manufacturing cost is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present invention;
fig. 2-8 are schematic structural diagrams illustrating a method for manufacturing a display substrate according to an embodiment of the invention after performing each step;
fig. 9 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the invention;
fig. 10 is a schematic structural diagram of a display substrate according to an embodiment of the invention;
fig. 11 is a schematic top view illustrating a portion of a film layer of the display substrate shown in fig. 10.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a method for manufacturing a display substrate, a display substrate and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings.
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The display substrate is a main component of a display device, and includes a substrate and a display unit including a Thin Film Transistor (TFT) disposed on the substrate. The LTPS substrate refers to a display substrate in which TFTs in the display unit are LTPS TFTs, and the oxide substrate refers to a display substrate in which TFTs in the display unit are oxide TFTs. The mobility of the polysilicon active layer is high, so that the leakage current (Ioff) of the LTPS TFT is high, the power consumption of the LTPS substrate under low-frequency driving is high, a static black picture is difficult to well maintain, and the picture quality is poor; also, in order to better develop gray scales, it is necessary to make a channel of a Driving Thin Film Transistor (DTFT) long in the LTPS substrate, so that it is difficult to realize high resolution of the LTPS substrate, which means the number of pixels disposed Per Inch (Pixel Per Inch, PPI); in addition, the poly active layer has a large Hysteresis (hystersis), and thus the LTPS substrate is likely to have a problem of image sticking. The mobility of the oxide active layer is low, so that the leakage current of the oxide TFT is low, the power consumption of the oxide substrate under low-frequency driving is low, a static black picture can be well kept, and the picture quality is improved; in addition, in the oxide substrate, the gray scale can be better expanded without making the channel of the DTFT very long, and high PPI is realized; in addition, the hysteresis of the oxide active layer is small, and the problem of image retention of the oxide substrate is not easy to occur; further, the uniformity of the oxide TFT is better than that of the LTPSTFT.
From the above description, it can be seen that the oxide process can well compensate for some of the deficiencies of the LTPS process. However, the LTPS process and the oxide process have respective advantages and disadvantages, and therefore, the combination of the LTPS process and the oxide process is a very competitive process scheme, the combination of the LTPS process and the oxide process is the LTPO process, and the LTPO process is likely to be applied to the development of high-end products in the future.
The LTPO process-based display substrate is an LTPO substrate in which each display cell includes an LTPSTFT and an oxide TFT. However, in the process of manufacturing the LTPO substrate in the prior art, the manufacturing of each film layer needs to be processed by a patterning process, so the manufacturing process of the LTPO substrate is complicated, and the manufacturing cost is high.
In order to solve the problems of complex manufacturing process and high manufacturing cost of the LTPO substrate, an embodiment of the present invention provides a manufacturing method of a display substrate, where the display substrate may be an LTPO substrate, and the manufacturing method includes:
as shown in fig. 1, a first type active layer 2, a first insulating structure 3, a second type active layer 4, a second insulating layer 5 and a source drain metal layer 6 are sequentially formed on a substrate 1; wherein the content of the first and second substances,
before forming the source drain metal layer 6, forming a first type via hole V1 penetrating through the second insulating layer 5 and a second type via hole V2 penetrating through the first insulating structure 3 and the second insulating layer 5 simultaneously through a one-step patterning process; the first-type via hole V1 is used for overlapping the source-drain metal layer 6 with the second-type active layer 4, and the second-type via hole V2 is used for overlapping the source-drain metal layer 6 with the first-type active layer 2.
According to the manufacturing method of the display substrate provided by the embodiment of the invention, the first type via hole V1 and the second type via hole V2 are formed through one-time composition process, so that compared with the process that the two types of via holes are formed through two-time composition processes respectively in the prior art, the manufacturing process of the display substrate can reduce one-time composition process, the manufacturing process of the display substrate is simplified, and the manufacturing cost is reduced.
Specifically, as shown in fig. 1, the source-drain metal layer 6 includes a first source electrode 61, a first drain electrode 62, a second source electrode 63, and a second drain electrode 64, the first source electrode 61 and the first drain electrode 62 are electrically connected to the first type active layer 2 through the second type via V2, and the second source electrode 63 and the second drain electrode 64 are electrically connected to the second type active layer 4 through the first type via V1.
In specific implementation, in the above manufacturing method provided in the embodiment of the present invention, as shown in fig. 2, fig. 2 is a schematic diagram of a specific film structure corresponding to fig. 1, the first insulating structure 3 includes a first gate insulating layer 7, a first interlayer dielectric layer 8, and a first buffer layer 9, which are sequentially stacked between the first type active layer 2 and the second type active layer 4, and the second insulating layer 5 is a second interlayer dielectric layer (5) located on a side of the second type active layer 4 away from the substrate 1.
In specific implementation, in the above manufacturing method provided by the embodiment of the present invention, as shown in fig. 2, after forming the first gate insulating layer 7 and before forming the first interlayer dielectric layer 8, the method further includes: forming a first gate 10;
after forming the second-type active layer 4 and before forming the second interlayer dielectric layer 5, the method further comprises: forming a second gate insulating layer 11 and a second gate electrode 12; the pattern of the second gate insulating layer 11 is the same as that of the second gate electrode 12.
In specific implementation, in the above manufacturing method provided by the embodiment of the present invention, as shown in fig. 2, before forming the first type active layer 2 on the substrate base plate 1, the method further includes: a second buffer layer 13 is formed on the base substrate 1.
In specific implementation, in the above manufacturing method provided by the embodiment of the present invention, as shown in fig. 2, before forming the second buffer layer 13 on the substrate base plate 1, the method further includes: a first barrier layer 14 is formed on the base substrate 1.
In specific implementation, in the above manufacturing method provided in the embodiment of the present invention, the substrate generally has an alternating structure of a flexible substrate and a barrier layer, the flexible substrate may be a PI layer, and the barrier layer may be made of an inorganic material such as SiOx, Al2O3, or SiOxNx, for example, the substrate includes a first flexible substrate, a second barrier layer, and a second flexible substrate that are stacked.
The following describes the steps of forming the first type via V1 and the second type via V2 in detail by using specific embodiments:
in specific implementation, in the above manufacturing method provided in the embodiment of the present invention, the forming of the first type via hole V1 penetrating through the second insulating layer (the second interlayer dielectric layer 5) and the second type via hole V2 penetrating through the first insulating structure (i.e., the first gate insulating layer 7, the first interlayer dielectric layer 8, and the first buffer layer 9) and the second insulating layer (i.e., the second interlayer dielectric layer 5) at the same time by using a single patterning process may specifically include:
as shown in fig. 3, a first blocking layer 14, a second buffer layer 13, a first type active layer 2, a first gate insulating layer 7, a first gate 10, a first interlayer dielectric layer 8, a first buffer layer 9, a second type active layer 4, a second gate insulating layer 11, a second gate 12, and a second interlayer dielectric layer 5 are sequentially formed on a substrate 1, and the materials and the manufacturing processes of these layers are the same as those of the prior art and will not be described in detail herein.
The method steps for forming the first type via hole V1 and the second type via hole V2 on the substrate base plate 1 with the second interlayer dielectric layer 5 shown in fig. 3, as shown in fig. 9, specifically include:
s901, forming a photoresist layer on the second insulating layer;
specifically, as shown in fig. 4, a photoresist layer 15 is formed on the second insulating layer (second interlayer dielectric layer 5).
S902, exposing and developing the photoresist layer to form a first completely removed region of the photoresist layer, a partially reserved region of the photoresist layer and a completely reserved region of the photoresist layer; the first completely removed area of the photoresist layer corresponds to the second type of through holes, and the partial reserved area of the photoresist layer corresponds to the first type of through holes;
specifically, as shown in fig. 5, the photoresist layer 15 is exposed and developed using a Half-Tone mask (Half-Tone technology) or a Gray-Tone mask (Gray-Tone technology), so as to form a photoresist layer first completely removed region 01, a photoresist layer partially remaining region 02, and a photoresist layer completely remaining region 03; the photoresist layer first completely removed region 01 corresponds to the second type of via V2 and the photoresist layer partially remaining region 02 corresponds to the first type of via V1.
S903, removing the second insulating layer and part of the first insulating structure corresponding to the first completely removed area of the photoresist layer;
specifically, as shown in fig. 6, the second insulating layer (i.e., the second interlayer dielectric layer 5) and a portion of the first insulating structure 3 corresponding to the first completely removed region 01 of the photoresist layer are removed; specifically, since a part of the first insulating structure to be remained and the second interlayer dielectric layer 5 need to be etched together subsequently, the thickness of the first insulating structure to be remained can be determined according to the thickness of the second interlayer dielectric layer 5, and then the etching time and the etching rate are adjusted to etch the first insulating structure with a certain thickness to be etched away, for example, the first insulating structure is etched until only the first gate insulating layer 7 is remained, and the first interlayer dielectric layer 8 and the first buffer layer 9 are etched away.
S904, thinning the photoresist layer, wherein the photoresist layer in the partial reserved area of the photoresist layer is completely removed, and a partial photoresist layer is reserved in the full reserved area of the photoresist layer;
specifically, as shown in fig. 7, the photoresist layer 15 is thinned, wherein the photoresist layer in the photoresist layer partially remaining region 02 is completely removed, and a portion of the photoresist layer remains in the photoresist layer completely remaining region 03.
S905, removing the residual first insulating structure corresponding to the first completely removed area of the photoresist layer and the second insulating layer corresponding to the partial photoresist remaining area;
specifically, as shown in fig. 8, the remaining first insulating structure (i.e., the first gate insulating layer 7) corresponding to the first completely removed region 01 of the photoresist layer and the second insulating structure (i.e., the second interlayer dielectric layer 5) corresponding to the partially remaining region 02 of the photoresist layer are removed.
S906, stripping the residual photoresist layer;
specifically, as shown in fig. 2, the remaining photoresist layer is stripped, i.e., the first type via V1 and the second type via V2 are formed.
In summary, through the manufacturing steps shown in fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8, and fig. 2, the first type via hole V1 and the second type via hole V2 can be formed through a single patterning process, so that compared with the prior art in which two types of via holes are formed through two patterning processes, the manufacturing process of the display substrate in the present invention can reduce the single patterning process, simplify the manufacturing process of the display substrate, and reduce the manufacturing cost.
Specifically, as shown in fig. 10, after the first-type via hole V1 and the second-type via hole V2 are formed, the source-drain metal layer 6 is formed, the source-drain metal layer 6 includes a first source electrode 61, a first drain electrode 62, a second source electrode 63, and a second drain electrode 64, the first source electrode 61 and the first drain electrode 62 are electrically connected to the first-type active layer 2 through the second-type via hole V2, and the second source electrode 63 and the second drain electrode 64 are electrically connected to the second-type active layer 4 through the first-type via hole V1.
In a specific implementation, as shown in fig. 10, the first type active layer 2 may be a polysilicon active layer, for example, the first type active layer 2 may be an LTPS active layer, and when the first type active layer 2 is an LTPS active layer, the first type active layer 2, the first gate insulating layer 7, the first gate electrode 10, and the first source electrode 61 and the first drain electrode 62 constitute an LTPS TFT; the second-type active layer 4 may be an oxide active layer, for example, the second-type active layer 4 may be an IGZO active layer, an Indium Tin Zinc Oxide (ITZO) active layer, or the like, and when the second-type active layer 4 is an oxide active layer, the second-type active layer 4, the second gate insulating layer 11, the second gate electrode 12, and the second source and drain electrodes 63 and 64 constitute an oxide TFT.
At present, with the use requirement of a user, a flexible display becomes a mainstream of the development of the display at present, therefore, when the display substrate provided in the embodiment of the present invention is a flexible display substrate, as shown in fig. 2 to 8, the display substrate includes a display area AA and a bending area BA located at one side of the display area AA, the first type via hole V1 and the second type via hole V2 are located in the display area AA, since the bending area BA is bent by the user, since most of the materials of the first insulating structure 3 and the second insulating layer 5 are inorganic materials, which are brittle and easy to break, the insulating layer located in the bending area BA is generally etched away, in order to further simplify the manufacturing process of the display substrate and reduce the manufacturing cost, when the photoresist layer 15 is exposed and developed by using a half-tone mask in the step of manufacturing the structure of fig. 5, simultaneously forming a second completely removed area 04 of the photoresist layer, wherein the bending area BA corresponds to the second completely removed area 04 of the photoresist layer, as shown in fig. 5;
as shown in fig. 6, while the second insulating layer (i.e., the second interlayer dielectric layer 5) and a part of the first insulating structure (the first interlayer dielectric layer 8 and the first buffer layer 9 are etched) corresponding to the first completely removed region 01 of the photoresist layer are removed, the second insulating layer (i.e., the second interlayer dielectric layer 5) and a part of the first insulating structure (the first interlayer dielectric layer 8 and the first buffer layer 9 are etched) corresponding to the bending region BA are removed, that is, the first gate insulating layer 7 is remained in the bending region BA.
In specific implementation, in the manufacturing method provided by the embodiment of the invention, as shown in fig. 8, while the remaining first insulating structure (i.e., the first gate insulating layer 7) corresponding to the first completely removed region 01 of the photoresist layer and the second insulating structure (i.e., the second interlayer dielectric layer 5) corresponding to the partial photoresist remaining region 02 (shown in fig. 5) are removed, the remaining first insulating structure (i.e., the first gate insulating layer 7) corresponding to the bending region BA is removed.
Therefore, when the first-type via hole V1 and the second-type via hole V2 are formed through a single patterning process, the insulating layer of the bending area BA is etched away, so that the manufacturing process of the display substrate can be further simplified, and the manufacturing cost is reduced.
In specific implementation, in the above manufacturing method provided by the embodiment of the present invention, as shown in fig. 7, the thinning the photoresist layer includes:
and thinning the photoresist layer through an ashing process. Specifically, the photoresist layer in the structure shown in fig. 6 is subjected to an Ashing (Ashing) etching process to remove the photoresist in the photoresist partial retention region 02 and to remove a portion of the photoresist in the photoresist full retention region 03.
Based on the same inventive concept, an embodiment of the present invention further provides a display substrate, as shown in fig. 10, the display substrate is formed by using the manufacturing method of the display substrate provided by the embodiment of the present invention.
Specifically, as shown in fig. 11, fig. 11 is a schematic top view structure diagram of a part of the film layer in the display substrate shown in fig. 10, where the LTPS TFT indicates that the first-type active layer 2 is overlapped with the source-drain metal layer through the second-type via hole V2, the Oxide TFT indicates that the second-type active layer 4 is overlapped with the source-drain metal layer through the first-type via hole V1, and orthographic projections of the first-type active layer 2 and the second-type active layer 4 are not overlapped.
In specific implementation, the display substrate provided in the embodiment of the present invention may be an Organic Light Emitting Diode (OLED) display substrate, and the display substrate further includes, on the basis of the structure shown in fig. 10: the flat layer, the anode, the pixel defining layer and the spacer layer are sequentially stacked on the source drain metal layer 6, and the anode is connected with the source drain metal layer through a through hole penetrating through the flat layer. In addition, the display substrate may further include an organic light emitting layer and a cathode, which are not described in detail herein.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display substrate provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The display device can be implemented in the embodiments of the display substrate, and repeated descriptions are omitted.
According to the manufacturing method of the display substrate, the display substrate and the display device, the first type of through holes and the second type of through holes are formed through the once composition process, so that compared with the process that the two types of through holes are formed through the twice composition processes in the prior art, the manufacturing process of the display substrate can be reduced by the once composition process, the manufacturing process of the display substrate is simplified, and the manufacturing cost is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A method for manufacturing a display substrate is characterized by comprising the following steps:
sequentially forming a first active layer, a first insulating structure, a second active layer, a second insulating layer and a source drain metal layer on a substrate; wherein the content of the first and second substances,
before the source-drain metal layer is formed, forming a first type of through hole penetrating through the second insulating layer and a second type of through hole penetrating through the first insulating structure and the second insulating layer simultaneously through a one-time composition process; the first type of via hole is used for overlapping the source and drain metal layer and the second type of active layer, and the second type of via hole is used for overlapping the source and drain metal layer and the first type of active layer.
2. The method according to claim 1, wherein the forming of the first type of via hole penetrating through the second insulating layer and the second type of via hole penetrating through the first insulating structure and the second insulating layer simultaneously by a single patterning process specifically includes:
forming a photoresist layer on the second insulating layer;
exposing and developing the photoresist layer to form a first completely removed region of the photoresist layer, a partially reserved region of the photoresist layer and a completely reserved region of the photoresist layer; the first completely removed area of the photoresist layer corresponds to the second type of through holes, and the partial reserved area of the photoresist layer corresponds to the first type of through holes;
removing the second insulating layer and part of the first insulating structure corresponding to the first completely removed area of the photoresist layer;
thinning the photoresist layer, wherein the photoresist layer in the partial reserved area of the photoresist layer is completely removed, and partial photoresist layer is reserved in the full reserved area of the photoresist layer;
removing the residual first insulating structure corresponding to the first completely removed region of the photoresist layer and the second insulating layer corresponding to the partially reserved region of the photoresist layer;
and stripping the residual photoresist layer.
3. The method according to claim 2, wherein the display substrate comprises a bending region corresponding to the second completely removed region of the photoresist layer;
and removing the second insulating layer and part of the first insulating structure corresponding to the bending region while removing the second insulating layer and part of the first insulating structure corresponding to the first completely removed region of the photoresist layer.
4. The method according to claim 3, wherein the removing of the remaining first insulating structure corresponding to the first completely removed region of the photoresist layer and the removing of the second insulating layer corresponding to the partially remaining region of the photoresist layer are performed while removing the remaining first insulating structure corresponding to the bending region.
5. The method of claim 2, wherein said thinning said photoresist layer comprises:
and thinning the photoresist layer through an ashing process.
6. The method according to claim 1, wherein the first insulating structure includes a first gate insulating layer, a first interlayer dielectric layer and a first buffer layer sequentially stacked between the first type active layer and the second type active layer, and the second insulating layer is a second interlayer dielectric layer located on a side of the second type active layer away from the substrate.
7. The method of claim 6, further comprising, after forming the first gate insulating layer and before forming the first interlayer dielectric layer: forming a first grid;
after the second type active layer is formed and before the second interlayer dielectric layer is formed, the method further comprises the following steps: forming a second gate insulating layer and a second gate electrode; the pattern of the second gate insulating layer is the same as the pattern of the second gate electrode.
8. The method of any of claims 1-7, wherein the first type of active layer is a polysilicon active layer and the second type of active layer is an oxide active layer;
before forming the first active layer on the substrate, the method further includes: a second buffer layer is formed on the substrate base plate.
9. A display substrate formed by the manufacturing method according to any one of claims 1 to 8.
10. A display device comprising the display substrate according to claim 9.
CN202010685703.8A 2020-07-16 2020-07-16 Manufacturing method of display substrate, display substrate and display device Pending CN111883482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010685703.8A CN111883482A (en) 2020-07-16 2020-07-16 Manufacturing method of display substrate, display substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010685703.8A CN111883482A (en) 2020-07-16 2020-07-16 Manufacturing method of display substrate, display substrate and display device

Publications (1)

Publication Number Publication Date
CN111883482A true CN111883482A (en) 2020-11-03

Family

ID=73155694

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010685703.8A Pending CN111883482A (en) 2020-07-16 2020-07-16 Manufacturing method of display substrate, display substrate and display device

Country Status (1)

Country Link
CN (1) CN111883482A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876334A (en) * 2017-03-10 2017-06-20 京东方科技集团股份有限公司 The manufacture method and array base palte of array base palte
CN108376672A (en) * 2018-03-15 2018-08-07 京东方科技集团股份有限公司 Array substrate and preparation method thereof and display device
CN109273409A (en) * 2018-08-24 2019-01-25 京东方科技集团股份有限公司 A kind of display panel, its production method and display device
CN110098201A (en) * 2019-05-16 2019-08-06 合肥京东方光电科技有限公司 Transistor device and its manufacturing method, display base plate, display device
CN110556386A (en) * 2019-09-05 2019-12-10 京东方科技集团股份有限公司 Driving backboard, manufacturing method thereof and display panel

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876334A (en) * 2017-03-10 2017-06-20 京东方科技集团股份有限公司 The manufacture method and array base palte of array base palte
CN108376672A (en) * 2018-03-15 2018-08-07 京东方科技集团股份有限公司 Array substrate and preparation method thereof and display device
CN109273409A (en) * 2018-08-24 2019-01-25 京东方科技集团股份有限公司 A kind of display panel, its production method and display device
CN110098201A (en) * 2019-05-16 2019-08-06 合肥京东方光电科技有限公司 Transistor device and its manufacturing method, display base plate, display device
CN110556386A (en) * 2019-09-05 2019-12-10 京东方科技集团股份有限公司 Driving backboard, manufacturing method thereof and display panel

Similar Documents

Publication Publication Date Title
CN109300840B (en) Display substrate, manufacturing method thereof and display device
US9412760B1 (en) Array substrate and manufacturing method thereof, and display device
US9761731B2 (en) Thin film transistor and its manufacturing method, array substrate and its manufacturing method, and display device
CN108538860B (en) Manufacturing method of top gate type amorphous silicon TFT substrate
US11961850B2 (en) Display substrate, manufacturing method thereof, and display device
US10622483B2 (en) Thin film transistor, array substrate and display device
US20160276376A1 (en) Array substrate, method for fabricating the same, and display device
US10115832B2 (en) Thin film transistor, method for manufacturing the same, array substrate and display device
US9761617B2 (en) Method for manufacturing array substrate, array substrate and display device
WO2018176829A1 (en) Thin film transistor and display substrate, fabrication method thereof, and display device
US20180292696A1 (en) Array substrate, manufacturing method thereof, display panel and display device
US10930518B2 (en) OLED substrate and manufacturing method thereof, display device and manufacturing method thereof
WO2017193667A1 (en) Thin film transistor and manufacturing method therefor, array substrate and manufacturing method therefor, and display apparatus
US9899532B2 (en) Thin-film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display apparatus
US20190165006A1 (en) Thin film transistor, manufacturing method therefor, array substrate and display device
US20180277685A1 (en) Thin film transistor and manufacturing method of the same, array substrate and display device
WO2019061289A1 (en) Array substrate, display apparatus, and method of fabricating array substrate
US10205029B2 (en) Thin film transistor, manufacturing method thereof, and display device
US20180151749A1 (en) Thin Film Transistor, Array Substrate and Methods for Manufacturing and Driving the same and Display Device
US20200312892A1 (en) Display substrate, manufacturing method thereof, and display device
US10134765B2 (en) Oxide semiconductor TFT array substrate and method for manufacturing the same
CN107134497B (en) Thin film transistor, manufacturing method thereof and display substrate
US10763283B2 (en) Array substrate, manufacturing method thereof, display panel and manufacturing method thereof
US8329517B2 (en) Pixel structure and method for manufacturing the same
CN111883482A (en) Manufacturing method of display substrate, display substrate and display device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination