CN111865306B - Real-time clock time-base frequency divider and real-time clock adjusting method - Google Patents
Real-time clock time-base frequency divider and real-time clock adjusting method Download PDFInfo
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- CN111865306B CN111865306B CN202010675952.9A CN202010675952A CN111865306B CN 111865306 B CN111865306 B CN 111865306B CN 202010675952 A CN202010675952 A CN 202010675952A CN 111865306 B CN111865306 B CN 111865306B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/1803—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop the counter or frequency divider being connected to a cycle or pulse swallowing circuit
Abstract
The invention discloses a real-time clock time-base frequency divider and a real-time clock adjusting method, wherein the time-base frequency divider comprises: the clock timing register, the combinational logic circuit, the frequency division counting circuit and the second counter; the clock adjusting value register is used for storing the adjusting value and transmitting the adjusting value to the combinational logic circuit when the real-time clock adjusting is started; the combinational logic circuit is used for receiving the calibration value and the count value of the second counter, calculating the number of basic calibration time length units in the current one second according to the calibration value and the count value, generating the calibration count value according to the calculation result and transmitting the calibration count value to the frequency division counting circuit; the frequency division counting circuit is used for counting the 32768Hz clock source signal according to the received calculation result and outputting a 1Hz pulse signal to the second counter; the second counter transmits a count value to the combinational logic circuit and increments the count value by 1 upon receiving a 1Hz pulse signal. The embodiment of the invention can improve the adjustment precision.
Description
Technical Field
The invention relates to the technical field of real-time clock adjustment, in particular to a real-time clock time-base frequency divider and a real-time clock adjustment method.
Background
The core of a real-time clock (RTC) is a frequency divider chain composed of 15D flip-flops, a clock signal of 1Hz is obtained by dividing a clock source of 32768Hz generated by an external crystal oscillator or an internal RC oscillator, and then time information such as time, month, day, hour, minute and second is obtained by accumulating the number of clock pulses of 1 Hz. The basic function of the RTC is to provide time information to a Micro Control Unit (MCU), and after the system is powered down, the standby battery on or off the chip supplies power to continuously keep the operation of the on-chip clock. The RTC may also extend diversified functions such as multi-way timing, calendar functions, alarm clock functions, programmable square wave output, event time recording, system power control, buffering data, etc.
In the prior art, the RTC module typically employs a clock source of 32768 Hz. The counter inside the RTC starts counting from 0 and increments by 1 each time the rising edge of the clock source arrives. When the counter counts to 16384, the output of the RTC flips; when the counter reaches 32768, the output of the RTC is again inverted, and the counter is reset to zero, so that a square wave signal output of 1Hz is generated. The conventional calibration method for RTC is to change the target counting value of the counter, so as to advance or retard the turning time of the square wave signal. For example, by increasing the target value of the counter to zero by 1, i.e., from 32768 to 32769, the instant of the even-numbered flip of the square wave signal is delayed (1/32768) by approximately 30.5176 μ s. Therefore, the minimum adjustable time length of the conventional tuning method is 30.5176 μ s, i.e., the theoretical error is ± 15.2588 ppm.
The calibration method has the advantages that the calibration precision is still low, the theoretical error is +/-15.2588 ppm, namely, the error is +/-1.318 seconds every day, and the error is +/-481.2 seconds every 365 days, so that the calibration precision needs to be further improved.
Disclosure of Invention
The embodiment of the invention provides a real-time clock time-base frequency divider and a real-time clock adjusting method, which can improve the adjusting precision.
An embodiment of the present invention provides a real-time clock time-base frequency divider, including: the clock timing register, the combinational logic circuit, the frequency division counting circuit and the second counter; wherein the second counter is a 7-bit second counter with a counting period of 128 seconds;
the clock adjusting value register is used for storing an adjusting value and transmitting the adjusting value to the combinational logic circuit when the real-time clock adjusting is started; the calibration value is 12 bits of data, the highest bit of the calibration value is used for indicating the increase or decrease of the counting target value, the upper 4 bits of data except the highest bit are used for indicating the number of basic calibration time length units which need to be calibrated in each second in a calibration period of 128 seconds, and the lower 7 bits of the calibration value are used for indicating the number of seconds which need to additionally increase or decrease one basic calibration time length unit in a calibration period of 128 seconds;
the combinational logic circuit is configured to receive the calibration value and the count value of the second counter, calculate the number of basic calibration time units in the clock source signal within one second after calibration according to the calibration value and the count value, generate a calibration count value according to the calculation result, and transmit the calibration count value to the frequency division counting circuit;
the frequency division counting circuit is used for counting a 32768Hz clock source signal according to the received adjusting and calibrating counting value and outputting a 1Hz pulse signal to the second counter; wherein, the frequency division counting circuit includes: a synchronous prescaler counter, a two-stage asynchronous frequency divider, and a millisecond counter; the synchronous prescaler is used for counting 32768Hz clock source signals according to the received adjusting and counting values and outputting 256Hz pulse signals to the two-stage asynchronous prescaler; the two-stage asynchronous frequency divider is used for dividing the 256Hz pulse signal into a 64Hz clock source signal and then transmitting the 64Hz clock source signal to a millisecond counter; the millisecond counter is used for outputting a 1Hz pulse signal to the second counter according to the 64Hz clock source signal;
and the second counter is used for transmitting a counting value to the combinational logic circuit and adding 1 to the counting value when the 1Hz pulse signal is received.
Further, the frequency division counting circuit includes: a synchronous prescaler, a two-stage asynchronous frequency divider and a millisecond counter;
the synchronous prescaler is used for counting 32768Hz clock source signals according to the received adjusting and counting values and outputting 256Hz pulse signals to the two-stage asynchronous prescaler;
the two-stage asynchronous frequency divider is used for dividing the 256Hz pulse signal into a 64Hz clock source signal and then transmitting the 64Hz clock source signal to a millisecond counter;
and the millisecond counter is used for outputting a 1Hz pulse signal to the second counter according to the 64Hz clock source signal.
Further, the clock calibration value register is a 12-bit register; the synchronous prescaler is an 8-bit counter; the millisecond counter is a 6-bit counter.
On the basis of the above embodiment of the present invention, another embodiment of the present invention provides a method for adjusting a real-time clock; the method comprises the following steps: a clock source signal of 32768Hz and an adjustment value are input to the time-base frequency divider of the rtc according to any of the above embodiments of the present invention, so that the time-base frequency divider adjusts the output 1Hz clock signal according to the adjustment value with 128 seconds as an adjustment period.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a real-time clock time-base frequency divider and a real-time clock adjusting method, wherein the real-time clock time-base frequency divider consists of a clock adjusting value register, a combinational logic circuit, a frequency division counting circuit and a second counter, the second counter is a 7-bit second counter with a counting period of 128 seconds, the adjusting period of the whole time-base frequency divider is set to be 128 seconds by adopting the second counter with a counting period of 128 seconds, and the clock adjusting value register transmits the stored adjusting value to the combinational logic circuit during adjusting. The calibration value is 12 bits of data, the highest bit indicates the increase and decrease of the counting target value, the upper 4 bits of data except the highest bit are used for indicating the number of basic calibration time length units needing calibration in each second in 128s, and the lower 7 bits of data are used for indicating the number of seconds needing to add/reduce one basic calibration time length unit in 128 s. After receiving the calibration value and the count value of the counter, the combinational logic circuit calculates the number of basic calibration time length units in the clock source signal within one second after calibration, then generates a calibration count value and transmits the calibration count value to the frequency division counting circuit; the frequency division counting circuit calibrates and counts the clock source signal according to the calibration count value, and then outputs a 1Hz pulse signal to the counter; the second counter outputs a count value to the combinational logic circuit at the start of calibration, and increments the count value by 1 every time a 1Hz pulse signal is received. When the count value of the second counter reaches 128, the second counter is reset to zero, thereby completing the calibration of one calibration period. In the embodiment disclosed in the present invention, a second counter is used to set the tuning period of the real-time clock to 128 seconds, and (1/32768) s ≈ 30.5176 μ s (30.5 μ s for short) is used as a basic tuning duration unit, so that at most ± 2047 basic tuning duration units can be tuned in each tuning period, and thus the maximum tuning precision is (1/32768) s/128s ≈ 0.238419ppm, and the maximum tuning range is ± 2047 ≈ 0.238419ppm ± 488.043 ppm. The adjustment precision is improved.
Drawings
Fig. 1 is a schematic structural diagram of a time-base divider of a real-time clock according to an embodiment of the present invention.
Fig. 2 is a waveform diagram after calibration value updating according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, a real-time clock time-base divider according to an embodiment of the present invention includes: the clock timing register, the combinational logic circuit, the frequency division counting circuit and the second counter; wherein the second counter is a 7-bit second counter with a counting period of 128 seconds;
the clock adjusting value register is used for storing an adjusting value and transmitting the adjusting value to the combinational logic circuit when the real-time clock adjusting is started; the calibration value is 12 bits of data, the highest bit of the calibration value is used for indicating the increase or decrease of the counting target value, the upper 4 bits of data except the highest bit are used for indicating the number of basic calibration time length units which need to be calibrated in each second in a calibration period of 128 seconds, and the lower 7 bits of the calibration value are used for indicating the number of seconds which need to additionally increase or decrease one basic calibration time length unit in a calibration period of 128 seconds;
the combinational logic circuit is used for receiving the calibration value and the count value of the second counter, generating a calibration count value according to the calibration value and the count value and the calculation result, and transmitting the calibration count value to the frequency division counting circuit;
the frequency division counting circuit is used for counting a 32768Hz clock source signal according to the received adjusting and calibrating counting value and outputting a 1Hz pulse signal to the second counter;
and the second counter is used for transmitting a counting value to the combinational logic circuit and adding 1 to the counting value when the 1Hz pulse signal is received.
In a preferred embodiment, the divide-by-count circuit includes: a synchronous prescaler counter, a two-stage asynchronous frequency divider, and a millisecond counter;
the synchronous prescaler is used for counting 32768Hz clock source signals according to the received adjusting and counting values and outputting 256Hz pulse signals to the two-stage asynchronous prescaler;
the two-stage asynchronous frequency divider is used for dividing the 256Hz pulse signal into a 64Hz clock source signal and then transmitting the 64Hz clock source signal to a millisecond counter;
and the millisecond counter is used for outputting a 1Hz pulse signal to the second counter according to the 64Hz clock source signal.
In a preferred embodiment, the clock alignment value register is a 12-bit register; the synchronous pre-frequency-dividing counter is an 8-bit counter; the millisecond counter is a 6-bit counter.
The technical solution of the present invention is further described below:
in the invention, 128s is taken as an adjusting period, s (1/32768) s ≈ 30.5176 μ s (30.5 μ s for short) is taken as a basic adjusting time duration unit, and at most +/-2047 basic adjusting time duration units can be adjusted in each adjusting period, so that the highest adjusting precision is (1/32768) s/128s ≈ 0.238419ppm, and the maximum adjusting range is +/-2047 ≈ 0.238419ppm ≈ 488.043 ppm.
The alignment value (ADJUST) is stored in a 12-bit clock alignment value register, as shown in table 1, where the most significant bit is the Sign bit (Sign) indicating an increase or decrease in the count target value, 0 indicating an increase, and 1 indicating a decrease; the remaining 11 bits represent the absolute value of the increase or decrease. In order to improve the average precision per second and avoid larger inter-second transition, a practice of averagely distributing the adjustment amount (i.e. the time length required to be increased and decreased) of 128s to within each second is adopted, and the method is realized by dividing an increased and decreased absolute value of 11 bits into a public value (C) with 4 higher bits and a private value (D) with 7 lower bits, wherein the public value represents the number of basic adjustment time length units (30.5 mu s) requiring adjustment within each second in 128s, and the private value represents the number of seconds requiring additional/less than 1 and 30.5 mu s in 128 s.
TABLE 1
| ADJUST[11] | ADJUST[10:7] | ADJUST[6:0] |
| Sign | Common Value(C) | Differential Value(D) |
The formula of the calibration value can be expressed as
Adjustment＝(C*128+D)*(30.5176/128)ppm
Assuming that the clock needs to be increased by 0.238ppm, i.e., 128s cycles are increased by only 1 30.5 μ s, then 12' b0_0000_0000001 is written to ADJUST, i.e., the public value is 0 and the private value is 1, indicating that only 1 30.5 μ s needs to be added to 1s of 128 s.
Assuming that 488ppm needs to be increased, i.e. 2047 times of 30.5 μ s are increased in 128s period, 12' b0_1111_1111111 is written into ADJUST, i.e. the public value is 15 and the private value is 127, which means 15 times of 30.5 μ s are added in 128s per second, and 1 more 30.5 μ s is added in 127 s.
Further examples and expressions of the alignment values are shown in table 2.
TABLE 2
By setting the calibration value in the above way, the second period of smooth calibration can be obtained, the length difference between two adjacent seconds is only 30.5ppm at most, and the second period jitter caused by the over-concentrated introduction of the calibration quantity can be avoided. In addition, since only 16 basic calibration duration units are added/subtracted at most every second, this means that the bit width of the synchronous counting prescaler can be set to be small, theoretically, only 8 bits are needed (normal counting range: 0-127, expandable counting range: 0-143 during calibration, upper limit of final value: 143, lower limit: 111). A synchronous pulse signal output, typically 256Hz, is obtained from a prescaler, and a 64Hz RTC operating clock is subsequently obtained by asynchronous frequency division. Reducing the synchronous clock load can reduce power consumption and enhance the anti-electromagnetic interference performance.
To avoid timing conflicts, ADJUST should be updated and clock alignment started after the second interrupt occurs. For example, add 1 clock cycle of 32768Hz at the end of each second, as shown in fig. 2, for ADJUST (12' b0 — 0001 — 0000000).
The specific adjustment steps are as follows:
(1) the clock calibration value register is configured by software, and a signed calibration value (ADJUST) is written in and output to the combinational logic circuit.
For example, the written tuning values are: 12' b0_1111_ 1111111.
(2) The combinational logic circuit calculates how many basic calibration duration units (30.5 μ s) exist in the current second after calibration according to the calibration value (ADJUST in fig. 1) and the value of the second counter (count128 in fig. 1), then generates a calibration count value according to the calculation result, and outputs the calibration count value (adj _ cnt in fig. 1) to the synchronous pre-frequency-dividing counter.
Specifically, also taking the example of ADJUST as 12'b0_1111_1111111, 12' b0_1111_1111111 indicates that 15 additional 30.5 μ s are needed at the end of each second within 128s, and an additional 1 additional 30.5 μ s is needed at the end of 127 s. That is, when the value of the second counter is 0 to 126, the calculated result is that 32768+15+1 is 32784 basic calibration time length units in the current second; when the value of the second counter is 127, the result is that 32768+15 — 32783 basic calibration time length units exist in the current second. Since the up/down calibration operation of 30.5 μ s only occurs at the end of each second during the actual calibration process, and the synchronous prescaler needs to output a 256Hz pulse signal (f256) in the present invention, the combinational logic circuit generates and outputs a calibration count value (adj _ cnt) according to the calculation result after calculating how many basic calibration time length units are in each second, where adj _ cnt refers to how many basic calibration time length units are in each 1/256 s. When the value of the second counter is 0-126 and the end of a second is not reached, the adj _ cnt output by the combinational logic circuit is 127 (since the count is from 0, the adj _ cnt is 127, which means that there are 128 basic timing duration units in 1/256s at present); when the second counter value is 0-126 and the end of one second is reached, adj _ cnt is 127+15+ 1-143 (adjustment is needed when the end of one second is reached, i.e., adjustment is performed in the last 1/256 s); similarly, when the value of the second counter is 127 and the end of one second is not reached, adj _ cnt is 127, and when the value of the second counter is 127 and the end of one second is reached, adj _ cnt is 127+15 — 142.
(3) And the 8-bit synchronous prescaler counts the rising edge of the 32768Hz clock source according to the adj _ cnt and outputs a 256Hz pulse signal (f256) to the multistage asynchronous frequency division circuit. When the received calibration count value is 127, it indicates that the end of one second is not reached at this time, calibration is not needed, and the counting range of the synchronous prescaler is 0-127; if the received calibration count value is not 127, it indicates that calibration is required at the end of one second, for example, if the received calibration count value is 143, it indicates that calibration is required at the end of one second, and the count range of the synchronous prescaler is 0-143.
(4) The two-stage asynchronous frequency divider circuit divides the 256Hz pulse signal (f256) into a 64Hz clock (RTC _ clk), which is output to a register related to timing, such as a millisecond counter or a second counter, as an operating clock of the RTC.
(5) The millisecond counter outputs a 1Hz clock (ltbc _1Hz) to an external circuit according to rtc _ clk, and outputs a 1Hz pulse signal (sec _ tick) to the second counter.
(6) The second counter (count128), which increments by 1 each time the sec _ tick arrives, records the second in the 128s calibration cycle of the current second, which is compared in the combinational logic circuit with the private value (ADJUST [6:0]) to determine if the current second requires an additional/subtraction of 1 by 30.5 μ s. The second counter will return to zero when it reaches 128, indicating that the current calibration cycle is over and the next calibration cycle is on.
On the basis of the above embodiments, the present invention correspondingly provides a method for adjusting a real-time clock, which includes: a clock source signal of 32768Hz and an adjustment value are input to the time-base frequency divider of the real-time clock described in any one of the above embodiments of the present invention, so that the time-base frequency divider adjusts the output 1Hz clock signal according to the adjustment value with 128 seconds as an adjustment period.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (3)
1. A real time clock time base divider, comprising: the clock timing register, the combinational logic circuit, the frequency division counting circuit and the second counter; wherein the second counter is a 7-bit second counter with a counting period of 128 seconds;
the clock adjusting value register is used for storing an adjusting value and transmitting the adjusting value to the combinational logic circuit when the real-time clock adjusting is started; the calibration value is 12 bits of data, the highest bit of the calibration value is used for indicating the increase or decrease of the counting target value, the upper 4 bits of data except the highest bit are used for indicating the number of basic calibration time length units which need to be calibrated in each second in a calibration period of 128 seconds, and the lower 7 bits of the calibration value are used for indicating the number of seconds which need to additionally increase or decrease one basic calibration time length unit in a calibration period of 128 seconds;
the combinational logic circuit is configured to receive the calibration value and the count value of the second counter, calculate the number of basic calibration duration units in the clock source signal within a current second according to the calibration value and the count value, generate a calibration count value according to a calculation result, and transmit the calibration count value to the frequency division counting circuit;
the frequency division counting circuit is used for counting a 32768Hz clock source signal according to the received adjusting and calibrating counting value and outputting a 1Hz pulse signal to the second counter; wherein, the frequency division counting circuit includes: a synchronous prescaler counter, a two-stage asynchronous frequency divider, and a millisecond counter; the synchronous pre-frequency divider counter is used for counting 32768Hz clock source signals according to the received adjusting and counting values and outputting 256Hz pulse signals to the two-stage asynchronous frequency dividers; the two-stage asynchronous frequency divider is used for dividing the 256Hz pulse signal into a 64Hz clock source signal and then transmitting the 64Hz clock source signal to a millisecond counter; the millisecond counter is used for outputting a 1Hz pulse signal to the second counter according to the 64Hz clock source signal;
and the second counter is used for transmitting a counting value to the combinational logic circuit and adding 1 to the counting value when the 1Hz pulse signal is received.
2. The real time clock time-base divider of claim 1, wherein said clock alignment value register is a 12-bit register; the synchronous prescaler is an 8-bit counter; the millisecond counter is a 6-bit counter.
3. A real-time clock adjusting method is characterized by comprising the following steps: inputting a 32768Hz clock source signal and a calibration value into the rtc time-base divider according to any of claims 1-2, so that the time-base divider calibrates the output 1Hz clock signal with 128 seconds as a calibration period according to the calibration value.
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