CN111865302A

CN111865302A - High-resistance phase discriminator group ring phase-locked loop capable of fully automatically locking working state

Info

Publication number: CN111865302A
Application number: CN201910357732.9A
Authority: CN
Inventors: 张伟林
Original assignee: Individual
Current assignee: Individual
Priority date: 2019-04-30
Filing date: 2019-04-30
Publication date: 2020-10-30

Abstract

The invention relates to a high-resistance phase discriminator group ring phase-locked loop capable of locking a working state in a full-automatic mode. Fig. 1 is a block diagram of an internal circuit of a high-resistance digital phase detector according to the present invention, and the operation principle is as follows: adding another input signal after the initial state, if the output level of the high-impedance state is not in the level window comparator, because the output of the identifier 5 is '1', cp has counting pulse input, and adjusting the output level value of the DAC until the output of the identifier 5 is '0'; at this time, the output level value of the DAC is kept at a fixed value because cp has no counting pulse input, and finally, the high-impedance state output level is locked in a synchronous working state in [ V2, V1] through the adjustment of LF. On the contrary, when the high-impedance output level is in the level window comparator, because the output of the identifier 5 is '0', the count pulse is not input directly cp, and the high-impedance output level is maintained in the synchronous working state within [ V2, V1] through LF adjustment.

Description

High-resistance phase discriminator group ring phase-locked loop capable of fully automatically locking working state

Technical Field

The invention provides a design scheme of an IC (integrated circuit) or module internal circuit containing a full-automatic locking working state control link circuit aiming at various high-resistance digital phase detectors of different types and purposes.

The theory of the invention does not exist in the existing publications and books, and the theory is related to the section of 'theory and application of PLL design' written by the inventor himself, for example, 4.3 section 'analysis of LF charging and discharging process of loop filter', and provides a phase-locked loop formula with a brand-new concept and full-automatic locking working state.

Background

The technology is to the patent application number: 2015106451273A high-resistance digital phase detector for full-automatic locking operation is mainly suitable for matching the phase-locked loop of edge type phase detector with the phase-locked loops of all high-resistance type phase detector including level type.

The edge type phase discriminator has the working characteristics that the initial state of actual work is positioned on the position of a power supply, the traction process belongs to single direction, and only single pulse output exists in the working period of each phase discriminator. The level type phase discriminator different from the edge type phase discriminator has the working characteristics that the initial state of actual work is positioned near Vcc/2, and the paired bidirectional pulse output is realized in each phase discriminator working period of the whole traction process.

Disclosure of Invention

The technology matched with the newly added technology of the level type phase discriminator of the technical object comprises the following technologies in the patent application part of high-resistance type digital phase discriminator in a full-automatic locking working state:

LPF technology of high-efficiency filtering and time-lag characteristic of LF output;

b. a technique of recognizing an initial operating state of a phase discriminator;

c. counter count state control techniques.

Definitions and explanations

The high-resistance digital phase discriminator is a signal waveform which is processed by the phase discriminator and meets the specification requirement of the input signal of the general digital integrated circuit, namely, a signal form with two state values of H and L is provided, the output specification of the phase discriminator also meets the specification requirement of the output signal of the general digital integrated circuit, the output signal not only has two state values of H and L, but also has a signal form with high-resistance output, namely, the level of the output signal depends on the structure of an external circuit at the output end, and the output impedance is high, namely, shielding output. The relationship between the input and output signals of the phase detector is taken as an object phase detector suitable for the technology of the present piece, such as the following patent application number: 2015106979265 related signal relation example conforming to the design definition of the phase detector in the orthogonalized high impedance digital phase detector is shown in fig. 1.

In this patent application, two input (end) signal signs in the phase discriminator are Wr and Wc, and the output (end) signal sign is PD_O. In the initial state of the phase discriminator in which Wr has signal Wc and no signal in figure 1, its actual working potential is near Vcc/2, and the output signal in one phase discriminator output period belongs to bidirectional paired signal, belonging to object discrimination to be processed by said invented techniqueThe working state of the phase discriminator is completely different from that of a high-resistance digital phase discriminator with full-automatic locking working state.

Drawings

Fig. 1 is an exemplary diagram of the relationship of the correlated signals in a definition of a case of an orthogonalizing phase detector design.

The test method is that two ends of two series resistors are respectively connected with two ends of a power supply of the phase detector, wherein a point is connected with an output (end) PDo of the phase detector and serves as an output end of a test circuit, and the method is the connection method of the output end of the phase detector under the test method.

Fig. 2 is a block diagram of an internal principle circuit of the high-resistance digital phase detector in the full-automatic locking working state, and the content of each identified device is used as the standard.

FIG. 3 is a block diagram of an internal principle circuit in this document

a. Identification 1, i.e. PD: the phase detector, as the stipulation in "the structure principle scheme of the high-resistance type digital phase detector of standardized design", there is an INH signal former, this signal needs to be used as a control signal in the phase detector of the invention.

b. Identification 2, or gate of IC 6: wr, Wc signal synthesizer, WrWc =00, outputs "0", and the rest outputs "1".

c. Identification 21, and gate of IC 21: wr, Wc signal synthesizer, WrWc =11, outputs "1", and the rest outputs "0".

d. Identity 3 and gate of IC 7: the counter triggers the digital switch, and when the output of IC8, i.e., flag 4, is "1", the switch is turned on, and when the output is "0", the switch is turned off, and the normal state is "1".

e. Identity 4 and gate of IC 8: the counter triggers the control signal of the digital switch to form a digital switch; when the signal of the digital switch control end is 1, the switch is switched on, when the signal is 0, the switch is switched off, and the normal state is 1. The control end signal of the switch is directly an INH signal if the INH is an effective shielding control signal, and if the INH is an effective shielding control signalINHIf the control signal is effectively shielded, the signal is output in a reversed phase mode; the input signal of the switch is the output signal of the inverting terminal of the D trigger with the identifier 23Q。

f. Identification 5, i.e. CP: the counter has the length N and the initial count P and can continuously output P and N]Address code, wherein N-P =2^MM in (1) is the number of DAC bits marked as 6, and has an increasing and decreasing value, i.e., +/-min, the control terminal is the external input terminal Z, Z =1 is an increasing formula, and Z =0 is a decreasing formula.

g. Identification 6, DAC: n-bit digital-to-analog converter, output voltage V_refIs composed of V_refL,V_refHDetermined by two set levels.

h. IC9 of flags 8 and 9, IC10 and nand gate of flag 10 constitute a level window comparator: two thresholds V1, V2(V1> V2) of the window comparator are determined by external input signals, and when the output level of LF is in the window, "L" is output, otherwise, "H" is output.

i. Identity 7 i.e. IC 12: the reference level adjustable potential compressor is used for outputting the output level of the DAC; the compression output is performed on the output level of LF, and the compression ratio is determined by the resistance ratio of R4/R3.

j. Identification 11, inverter IC 13: the phase discriminator belongs to INH effective type, does not need inverter direct connection, and belongs toINHThe active version does not require an inverter.

k. The label 22 is a router prototype HC 4053: the '0' is connected with the output of the IC21 and the gate, the '0' is connected with the ground, the 'COM' is connected with the clock input end of the D trigger of the identifier 23 in common, the 'a' is a control end, the output of the IC21 and the gate is connected with the clock end of the D trigger when the 'a = 0', and the clock end of the D trigger loads a ground signal when the 'a = 1'.

The flag 23 is a rising edge type D flip-flop: the reset end R (= H) is connected with the output of the horizontal window comparator, namely the output of the IC11, if the output is H, the counting is allowed, because the D flip-flop is output by the reversed end after being reset QAnd "H", according to the regulation. If the output is L, the D trigger works normally.

Other identified devices are illustrated below:

buffers of IC1, IC 2: IC1 is an input signal Wr and IC2 is a buffer for input signal Wc.

Inverter of ic4 (without window type): an active integration type LF is constituted by the internal resistor R1, the external resistor R2, and the capacitor C1.

Follower of ic5: the output value of the active integration type LF is output to the outside.

Inverter of ic3 (without window type): for use in forming an internal VCO.

external passive type of lpf, ports L1, L2: if the phase detector is in an edge type, the phase detector can be in short circuit, but an RC type LPF is recommended to be connected; if the phase detector is in a level type, LPFs of an LC (front) and an RC (rear) are connected, and the inertia LPFs are recommended to be added.

Other ports of the IC chip are illustrated as follows:

a. the 4 ports of the power supply class are respectively a digital-analog power supply Vcc and a Vcca, and one analog digital GND.

2 phase detector input signal ports of wr, Wc.

In, OUT for 2 ports of the internal VCO.

R2, resistance and capacitance access port of the active integration type LF of RC.

The compressor of r3 is referenced to the resistive access port.

Lfout's LF follows the output port.

And g, a VCO control end input signal port of VCOin.

h.V_refThe DAC output upper limit value setting port.

V1, V2 window comparators upper V1 and lower V2 set the ports.

j.Z the counter increments the setting control terminal.

L1, L2.

Description of newly added content

Sense of setting up the counter up and down

The default counter of the high-resistance digital phase detector in the full-automatic locking working state is an incremental type, and only can be suitable for a phase-locked loop working mode that the actual potential of the initial state of the phase detector is L, and the phase-locked loop working mode that the actual potential of the initial state of the phase detector is H and other phase-locked loops between power supply potentials can also be corresponding to the new setting of the end.

Significance of external passive LPF setting

The new design of the external passive LPF is an indispensable condition in the application of the level type phase discriminator group ring phase-locked loop.

Control of stop counting mode of counter

Taking the application of the phase detector in fig. 1 as an example, WrWc = "10", that is, the actual output potential of the LPF in the initial state is near the midpoint voltage of the power supply, and the actual output potential already belongs to the set potentials V1, V2 of the level window comparator, that is, the window comparator output is "L", which is the operating condition for stopping counting in the "high-resistance digital phase detector in the fully-automatic locked operating state". However, in this device, no matter the chip is initially powered on, or the phase-locked loop is switched between the initial state and the operating state, the D flip-flop forming the identifier 23 is reset, after reset, the counter is allowed to continue operating because the inverted output terminal of the flip-flop is "H", while the input of the state phase detector remains unchanged, i.e., the output of the IC21 always remains "L", and the inverted output terminal of the flip-flop also remains "H" because no rising edge signal arrives at the clock terminal of the flip-flop.

If the phase-locked loop works normally, if the actual output potential of the LPF is not within the set potentials V1 and V2 of the level window comparator, the counter counts normally after the trigger is reset. When the actual output potential of the LPF is within the set potentials V1 and V2 of the level window comparator, the output of the window comparator is inverted from "H" to "L", the flip-flop stops resetting, but the inverted output terminal of the flip-flop continues to maintain "H" unchanged until WrWc = "11" arrives, the "H" output of the IC21 is sent to the clock terminal of the flip-flop through the "0" port of the identifier 22 two-way selector, then the inverted output terminal of the flip-flop is changed to "L" to stop counting of the counter, and meanwhile, the non-inverted output terminal of the flip-flop is changed to "H" as the control terminal of the two-way selector is changed to "H", under the action of the ground signal of the "1" terminal of the two-way selector, the clock terminal input of the flip-flop is effectively maintained to be "0", that is, the inverted output.

Even if the output of the level window comparator is 0 for several times before the counter actually stops counting, the counter can be ensured to stop counting until the working condition of the counter is effectively destroyed, and the mode of closing the middle values of the setting potentials V1 and V2 is a more favorable phase-locked loop working mode.

In summary, a design scheme of the full-automatic locking operating state IC of the high-resistance phase detector group loop phase-locked loop, which is more suitable for the requirements of the phase detector in the structural principle scheme of the standardized design high-resistance digital phase detector of patent application No. 2015106449019, is a suitable scheme.

Claims

1. A full-automatic phase-locked loop locking state entering technology is applicable to an object phase discriminator according to the following patent application numbers: 2015106448849, the high impedance state control signal INH and the phase difference detection signal a generated by the structural principle scheme of the standardized design high impedance type digital phase discriminator are provided to the patent application number: 2015106448849 Standard interface Circuit of high resistance digital phase discriminator output stage and patent application No.: 2017104018440 Standard interface Circuit of non-FET switch class of output stage of high resistance phase discriminator forms a matched output interface circuit, which meets the requirement of the object phase discriminator on the full-mode working condition, and comprises: an active integral loop filter LF is internally arranged, the LF output is highly inert LPF, the LF output is used as a monitoring window to be externally output after passing through a Buffer, a windowless inverter is reserved for an external VCO, a level shift compressor, a high-resistance potential line OK judger, an M-bit digital-to-analog converter DAC, and a mode N (-P =' 2) ^M") a counter CP, a CP clock control switch, a counter counting state determiner (hereinafter simply referred to as a determiner); this technology is to patent application number: 2015106451273A high-resistance digital phase detector with full-automatic locking working state is upgraded, the object phase detector incorporates a level phase detector to make a new technology meeting the requirement of the full-mode working state, and the specific new technical form comprises:

a, an external setting end of a newly added counting mode changes the original counting in an increasing mode into a bidirectional counting mode capable of increasing and decreasing;

b, inserting a high inertia LPF which can be connected to the output of the LF into the original path of the LF output through an external resistor loaded on the negative end of the level shift compressor to meet the control requirement of the level type high-resistance phase discriminator;

c, changing the mode that the original high-resistance potential line OK judger is directly connected with the CP clock control switch into a judger, wherein the output of the original high-resistance potential line OK judger is used as the input signal of a newly-added judger to be connected to the reset end of the judger, the other two input signals are the input signals of the object phase discriminator, the output signal of the judger is connected with the CP clock control switch, and the interior of the judger is formed into an AND gate, a two-way selector and a D trigger; if the 'H' signal of the requirement count starts the decision device to reset and outputs the 'H' state signal, namely the counter is allowed to count and work, and the reset state of the decision device is used as the normal and initial state working mode of the decision device; if the L-state signal which requires the counting stop arrives, the normal state of the determiner is stopped, but whether the determiner sends out the L-state signal is determined by the relationship of the two phase discriminator input signals of the determiner, the output of the AND gate which is connected into the two phase discriminator input signals when the phase discriminator works in the initial state is always in the L-state, and the D trigger cannot be started to work, the output of the determiner maintains the H-state signal unchanged, if the two phase discriminator input signals are the HH-state signal, the AND gate sends out an H-state signal which is connected into the clock end of the D trigger through the one-way conducting switch which is the common end of the 0 end of the two-way selector, because a rising edge signal is received, the negative phase end of the D trigger which is taken as the output end of the determiner is inverted into the L-state signal to output, namely, the counting working mode of the counter is stopped, and the positive phase end of the D trigger which is taken as the control end signal of the two-way selector is inverted, the switch on which is the common end of the '1' end of the two-way selector is switched on, the decision device is positioned in the 'L' state signal output and is not changed until the decision device is reset again.