CN111863807B - Single-chip heterogeneous integrated Casode structure field effect transistor based on source field plate and manufacturing method - Google Patents

Single-chip heterogeneous integrated Casode structure field effect transistor based on source field plate and manufacturing method Download PDF

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CN111863807B
CN111863807B CN202010747894.6A CN202010747894A CN111863807B CN 111863807 B CN111863807 B CN 111863807B CN 202010747894 A CN202010747894 A CN 202010747894A CN 111863807 B CN111863807 B CN 111863807B
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source
sin
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metal
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CN111863807A (en
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张春福
张苇杭
武毅畅
张家祺
杨国放
陈大正
张进成
郝跃
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Xidian University
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention discloses a source field plate-based monolithic heterogeneous integrated Casode structure field effect transistor, which mainly solves the problem of poor breakdown characteristic of the existing Casode structure field effect transistor. It comprises the following steps: the GaN-based semiconductor device comprises a substrate (1), a GaN buffer layer (2), an AlGaN barrier layer (3) and a SiN isolation layer (4), wherein an isolation groove (17) is engraved in the middle of the SiN isolation layer; one side of the isolation groove is printed with a Si active layer (5) to prepare a Si metal oxide semiconductor field effect transistor; and a second source electrode (6), a second gate electrode (7) and a second drain electrode (8) are transversely and sequentially arranged on the other side of the isolation groove, a passivation layer (16) is arranged on the area between the source electrode and the drain electrode, and an active field plate (9) is deposited on the passivation layer and the second source electrode to form the GaN high electron mobility transistor. The invention has remarkable breakdown characteristics and can be used as a power converter or an inverter of an automobile, aerospace and power station.

Description

Single-chip heterogeneous integrated Casode structure field effect transistor based on source field plate and manufacturing method
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a field effect transistor with a monolithic heterogeneous integrated Cascode structure and a manufacturing method thereof, which can be used as a power converter or an inverter of an automobile, an aerospace and a power station.
Technical Field
GaN materials have more excellent electrical properties than the first and second generation semiconductor materials. GaN is used as a wide forbidden band semiconductor material, has higher breakdown electric field strength, carrier mobility and saturation speed, and better thermal stability, so that the GaN is more suitable for being applied in the fields of high frequency, high voltage, high temperature and high power. Compared with a Si material power device, the GaN/GaN high electron mobility transistor based on the GaN material is easier to realize a heterostructure, generates high-concentration two-dimensional electron gas, has higher electron mobility and breakdown electric field, and is often used in the power electronic field and the microwave field.
Since depletion-mode devices cause instability of the circuit, much research has been conducted on enhancement-mode devices. The most common method for realizing the enhancement type GaN high electron mobility transistor device at present is to cascade a low-voltage enhancement type Si metal oxide semiconductor field effect transistor and a high-voltage depletion type GaN high electron mobility transistor device to form a Cascode structure, as shown in fig. 1. For a Casode structure, a low-voltage enhanced Si metal oxide semiconductor field effect transistor controls the on and off of a device, and when the grid voltage is forward voltage, the Casode structure transistor is turned on, so that the enhanced GaN high electron mobility transistor is realized. In recent years, si devices and GaN devices are successfully manufactured on a single substrate, so that single-chip heterogeneous integration of a field effect transistor with a Cascode structure is realized, but a plurality of problems still exist and need to be solved, wherein the key problem is that the breakdown voltage of the device is low. When the single-chip heterogeneous integrated field effect transistor with the Casode structure works under the high-voltage high-power condition, the high-voltage depletion type GaN high-electron mobility transistor bears a large drain-source bias voltage, electric field lines in a barrier layer of the high-voltage depletion type GaN high-electron mobility transistor are unevenly distributed, most of the electric field lines are concentrated to the edge of a grid electrode, so that the GaN high-electron mobility transistor can generate avalanche breakdown under the lower drain-source voltage, further the breakdown characteristic of the Casode structure field effect transistor is poor, and the application of the high-voltage depletion type GaN high-electron mobility transistor in the field of power devices is limited.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a source field plate-based field effect transistor with a monolithic heterogeneous integrated Casode structure and a manufacturing method thereof, so as to solve the problem of uneven electric field distribution in a barrier layer near a gate electrode of a GaN high electron mobility transistor in the current Casode structure, improve the breakdown characteristics of the field effect transistor with the monolithic heterogeneous integrated Casode structure and enlarge the application range of devices.
In order to achieve the above object, the source field plate-based field effect transistor of the present invention comprises, from bottom to top: the GaN buffer layer is etched in the middle of the SiN isolation layer; an Si active layer is arranged on the SiN isolation layer at one side of the isolation groove, a first source electrode and a first drain electrode are arranged at two sides of the Si active layer, a gate dielectric layer is arranged between the source electrode and the drain electrode, and a first gate electrode is arranged on the gate dielectric layer to form an Si metal oxide semiconductor field effect transistor; the AlGaN barrier layer on the other side of the isolation groove is transversely and sequentially provided with a second source electrode, a second gate electrode and a second drain electrode, a passivation layer is arranged above the area between the source electrode and the drain electrode, and a GaN high electron mobility transistor is formed, and the AlGaN high electron mobility transistor is characterized in that: and an active field plate is deposited above the second source electrode and the passivation layer, and the source field plate and the second source electrode form a contact field plate structure so as to improve the electric field distribution of the edge of the second gate electrode and improve the breakdown characteristic of the field effect transistor with the Casode structure.
Further, the first drain electrode and the second source electrode are electrically connected through a first metal interconnection strip; the first source electrode and the second gate electrode are electrically connected through a second metal interconnection bar.
Further, the source field plate, the first metal interconnection strip and the second metal interconnection strip are all made of the same metal material; the gate dielectric layer between the first source electrode and the first drain electrode and the passivation layer on the region between the second source electrode and the second drain electrode are made of the same oxide material.
Further, the thicknesses of the source field plate, the first metal interconnection strip and the second metal interconnection strip are all 200-300nm; the thickness of the passivation layer above the region between the first source electrode and the first drain electrode and the second source electrode is 20-30nm.
Further, the thicknesses of the second source electrode and the second drain electrode are 262nm; the thickness of the second gate electrode is 150-270nm; the effective length of the source field plate is 2.5-3.5 mu m.
Further, the thickness of the Si active layer is 100-200nm; the thickness of the first gate electrode is 100-200nm; the thickness of the first source electrode and the first drain electrode is 30-100nm;
further, the substrate is made of sapphire or silicon carbide or silicon, and the thickness of the substrate is 400-500 mu m; the thickness of the GaN buffer layer is 1-2 mu m; the thickness of the AlGaN barrier layer is 20-30nm; the thickness of the SiN isolation layer is 150-200nm;
in order to achieve the above object, the method for manufacturing a source field plate-based monolithic heterogeneous integrated Cascode structure field effect transistor according to the present invention is characterized by comprising the steps of:
1) Preparing a SiN/AlGaN/GaN/substrate:
sequentially extending a GaN buffer layer and an AlGaN barrier layer on a substrate by adopting a metal organic chemical vapor deposition and atomic layer deposition process;
depositing an SiN isolation layer on the AlGaN barrier layer to obtain a SiN/AlGaN/GaN/substrate;
2) Forming a monocrystalline silicon film island on the SOI wafer by adopting photoetching and reactive ion etching processes;
3) Placing the sample obtained in the step 2) into 49% HF solution by adopting a wet etching process, and etching away the buried oxide layer which is not covered by the monocrystalline silicon film island;
4) Adopting a photoetching process to manufacture anchor points at the edges of the monocrystalline silicon thin film so as to prevent the displacement and falling of the monocrystalline silicon thin film after the buried oxide layer is completely etched in the follow-up process;
5) A wet etching process is adopted, a sample with an anchor point is put into 49% HF solution, and the buried oxide layer is completely etched, so that the monocrystalline silicon film falls on the substrate of the SOI wafer;
6) Transferring the monocrystalline silicon film obtained in the step 5) onto a SiN/AlGaN/GaN/substrate by adopting a transfer printing technology;
7) Etching 300-350nm deep isolation grooves on the sample obtained in the step 6) by adopting photoetching and reactive ion etching processes, and respectively forming Si/SiN/AlGaN/GaN islands and SiN/AlGaN/GaN islands at two sides of the isolation grooves;
8) The ion implantation process is adopted, and the implantation dosage is 5 multiplied by 10 on the monocrystalline silicon film of Si/SiN/AlGaN/GaN island 15 cm -2 Phosphorus ions with the energy of 30keV are annealed for 60s in a nitrogen atmosphere at the temperature of 1000 ℃ to activate impurities, so that an N-type heavily doped source drain region is formed;
9) Etching SiN of a source region and a drain region on the SiN/AlGaN/GaN island by adopting a reactive ion etching and electron beam evaporation process, sequentially depositing 22nm thick titanium metal, 140nm thick aluminum metal, 55nm thick nickel metal and 45nm thick gold metal on the source region and the drain region to form a source electrode and a drain electrode of the GaN high electron mobility transistor, and annealing for 30s in a nitrogen atmosphere at 875 ℃ to enable the source electrode and the drain electrode to form ohmic contact with an AlGaN barrier layer;
10 Etching SiN of a gate region on the SiN/AlGaN/GaN island by adopting a reactive ion etching and electron beam evaporation process, and sequentially depositing nickel metal with the thickness of 50-70nm and gold metal with the thickness of 100-200nm on the gate region to form a gate electrode of the GaN high electron mobility transistor;
11 Depositing an oxide film with the thickness of 20-30nm on the whole sample by adopting an atomic layer deposition process under the temperature condition of 300 ℃ and the nitrogen atmosphere to form a gate dielectric layer of the Si metal oxide semiconductor field effect transistor and a passivation layer of the GaN high electron mobility transistor;
12 Sputtering tantalum nitride with the thickness of 100-200nm on the oxide film above the undoped monocrystalline silicon film by adopting a magnetron sputtering process to form a gate electrode of the Si metal oxide semiconductor field effect transistor;
13 Etching oxide films on the monocrystalline silicon film source and drain regions by adopting wet etching and electron beam evaporation processes, depositing nickel metal with the thickness of 30-100nm to form source and drain electrodes of the Si metal oxide semiconductor field effect transistor, and annealing for 1min in a nitrogen atmosphere with the temperature of 400 ℃ to enable the source and drain electrodes and the heavily doped source and drain regions to form ohmic contact;
14 Etching all the oxide film covered on the source and drain electrodes of the GaN high electron mobility transistor by using HF solution with the concentration of 5%, and partially etching the oxide film covered on the gate electrode so as to expose the gate, source and drain electrodes of the GaN high electron mobility transistor outside;
15 Manufacturing a source field plate and a metal interconnection line:
15a) Manufacturing a photoresist mask on the surface of the device obtained in the step 14) by adopting photoetching, electron beam evaporation and technology, wherein the photoresist mask forms a source field plate pattern with the effective length of 2.5-3.5 mu m above a source electrode and a passivation layer of a GaN high electron mobility transistor, and forms a metal interconnection pattern between the two devices
15b) And depositing a layer of metal film with the thickness of 200-300nm on the photoresist mask, stripping redundant metal by using an organic solvent so as to enable a source electrode of the GaN high electron mobility transistor to be directly connected with the metal film to form a source field plate, and simultaneously forming metal interconnection between a drain electrode of the Si device and a source electrode of the GaN device and between the source electrode of the Si device and a gate electrode of the GaN device respectively to finish the manufacture of the whole device.
Compared with the prior art, the GaN high electron mobility transistor in the single-chip heterogeneous integrated Casode structure field effect transistor has the source field plate structure, so that the electric field distribution near the gate electrode is improved, the breakdown characteristic of the single-chip heterogeneous integrated Casode structure field effect transistor is improved, and the application range of the single-chip heterogeneous integrated Casode structure field effect transistor is expanded.
Drawings
FIG. 1 is a schematic circuit diagram of a field effect transistor of a prior art Cascode configuration;
FIG. 2 is a schematic cross-sectional structure of a source field plate-based monolithic heterogeneous integrated Cascode structure field effect transistor of the present invention;
FIG. 3 is a top view of FIG. 2;
fig. 4 is a schematic flow chart of fabricating a Cascode fet based on a source field plate according to the present invention.
Detailed Description
Embodiments of the present invention are described below with reference to the accompanying drawings.
Referring to fig. 2 and 3, the present invention is a source field plate based monolithically hetero-integrated Cascode structure field effect transistor comprising, from bottom to top, a substrate 1, a GaN buffer layer 2, an AlGaN barrier layer 3 and a SiN isolation layer 4. An isolation groove 17 is engraved in the middle of the SiN isolation layer 4, penetrates through the AlGaN barrier layer 3 and is deep to the GaN buffer layer 2 so as to cut off two-dimensional electron gas and prevent electric leakage between devices. The substrate material can be sapphire or silicon carbide or silicon substrate with the thickness of 400-500 mu m; the thickness of the GaN buffer layer 2 is 1-2 mu m; the thickness of the AlGaN barrier layer 3 is 20-30nm; the SiN isolating layer 4 has a thickness of 150-200nm.
The isolation groove 17 is printed with an Si active layer 5 on the SiN isolation layer 4 on one side, and a first source electrode 10 and a first drain electrode 13 are arranged on two sides of the Si active layer 5; a gate dielectric layer 11 is arranged between the first source electrode 10 and the first drain electrode 13; a gate electrode 12 is provided on the gate dielectric layer 11 to constitute a Si metal oxide semiconductor field effect transistor. Wherein the thickness of the Si active layer 5 is 100-200nm; the thickness of the first gate electrode 12 is 100-200nm; the thickness of the first source electrode 10 and the first drain electrode 13 is 30-100nm; the thickness of the gate dielectric layer 11 is 20-30nm.
The second source electrode 6, the second gate electrode 7 and the second drain electrode 8 are transversely and sequentially arranged on the AlGaN barrier layer 3 on the other side of the isolation groove 17, a passivation layer 16 is arranged above the area between the second gate electrode 7 and the second drain electrode 8, and an active field plate 9 is deposited above the passivation layer 16 and the second source electrode 6 to form the GaN high electron mobility transistor. Wherein the thickness of the second source electrode 6 and the second drain electrode 8 is 262nm; the thickness of the second gate electrode 7 is 150-270nm, the thickness of the passivation layer 16 is 20-30nm, the thickness of the source field plate 9 is 200-300nm, and the effective length of the source field plate 9 is 2.5-3.5 μm.
The first drain electrode 13 and the second source electrode 6 are electrically connected by a first metal interconnection strip 14, and the thickness of the first metal interconnection strip 14 is 200-300nm.
The first source electrode 10 and the second gate electrode 7 are electrically connected by a second metal interconnection bar 15, and the thickness of the second metal interconnection bar 15 is the same as the thickness of the first metal interconnection bar 14.
Referring to fig. 4, the following three embodiments are given for the method of fabricating a Cascode fet based on monolithic heterogeneous integration.
Example 1: and preparing a single-chip heterogeneous integrated Casode structure field effect transistor based on a source field plate on a sapphire substrate, wherein the thickness of the single-crystal silicon film is 200nm.
And step 1, preparing a SiN/AlGaN/GaN/sapphire substrate.
Sequentially extending a GaN buffer layer and an AlGaN barrier layer on a sapphire substrate by adopting a metal organic chemical vapor deposition and atomic layer deposition process;
and depositing a SiN isolation layer on the AlGaN barrier layer to obtain a SiN/AlGaN/GaN/sapphire substrate, as shown in (p) of FIG. 4.
And 2, forming single crystal silicon film island isolation on the SOI wafer.
Selecting an SOI wafer with a single crystal silicon film thickness of 200nm and a buried oxide layer thickness of 200nm, as shown in FIG. 4 (a);
a single crystal silicon thin film island is etched on the upper part of the SOI wafer by using a photolithography process and a reactive ion etching process, as shown in fig. 4 (b).
And 3, partially etching the exposed buried oxide layer.
And (3) placing the SOI wafer etched with the single crystal silicon film island into 49% HF solution for 15min by adopting a wet etching process, and etching the buried oxide layer which is not covered by the single crystal silicon film island, as shown in fig. 4 (c).
And 4, manufacturing a photoresist anchor point.
And (3) adopting a photoetching process to manufacture anchor points at the edges of the monocrystalline silicon film on the SOI wafer so as to prevent the monocrystalline silicon film from shifting and falling off after the buried oxide layer is completely etched later, as shown in fig. 4 (d).
And 5, completely etching the whole buried oxide layer to release the monocrystalline silicon film.
The SOI wafer with the anchor point is put into 49% HF solution for 2 hours by wet etching process, and the buried oxide layer is completely etched, so that the monocrystalline silicon film falls on the substrate of the SOI wafer, as shown in FIG. 4 (e).
Step 6, transferring the monocrystalline silicon film onto the SiN/AlGaN/GaN/sapphire substrate, as shown in FIG. 4 (f).
Transferring a 200nm monocrystalline silicon film on an SOI wafer onto a SiN/AlGaN/GaN/sapphire substrate with a SiN isolation layer thickness of 200nm, an AlGaN barrier layer thickness of 30nm, a GaN buffer layer thickness of 2 μm and a sapphire substrate thickness of 500 μm by adopting a transfer printing technology, wherein the method is concretely realized as follows:
firstly, sequentially placing SiN/AlGaN/GaN/sapphire substrate in acetone, absolute ethyl alcohol and deionized water, respectively ultrasonically cleaning for 10min, and blow-drying by a nitrogen gun;
then, the solid polydimethylsiloxane PDMS is attached to the SOI wafer etched with the buried oxide layer, and then the solid polydimethylsiloxane PDMS and the SOI wafer etched with the buried oxide layer are separated at a speed of 10cm/s, and as the polydimethylsiloxane PDMS is an elastic and viscous object, the surface adhesion force is in direct proportion to the separation speed, the solid polydimethylsiloxane PDMS can be quickly separated, so that the PDMS has larger adhesion force, and the monocrystalline silicon film is adhered to the polydimethylsiloxane PDMS;
then, the solid polydimethylsiloxane PDMS adhered with the monocrystalline silicon film is attached to the SiN/AlGaN/GaN/sapphire substrate, and then the solid polydimethylsiloxane PDMS and the SiN/AlGaN/GaN/sapphire substrate are separated at a speed of 1mm/s, and the separating speed is low, so that the polydimethylsiloxane PDMS has the effect that the adhesion force to the monocrystalline silicon film is smaller than that of the monocrystalline silicon film and the SiN/AlGaN/GaN/sapphire substrate, and therefore the silicon film can be obtained by the SiN/AlGaN/GaN/sapphire substrate, and the transfer printing of the silicon film is completed.
And 7, manufacturing island isolation of the Si metal oxide semiconductor field effect transistor and the GaN high electron mobility transistor.
And (3) performing isolation groove etching on the SiN/AlGaN/GaN/sapphire substrate with the transferred monocrystalline silicon film by adopting photoetching and reactive ion etching processes to cut off two-dimensional electron gas, and respectively forming Si/SiN/AlGaN/GaN islands and SiN/AlGaN/GaN islands at two sides of the isolation groove, as shown in fig. 4 (g).
And 8, manufacturing a source region and a drain region of the Si metal oxide semiconductor field effect transistor.
The ion implantation process is adopted, and the implantation dosage is 5 multiplied by 10 on the single crystal silicon film of Si/SiN/AlGaN/GaN island 15 cm -2 Phosphorus ions with energy of 30 keV; and then annealing for 60s in a nitrogen atmosphere at 1000 ℃ by utilizing a rapid thermal annealing process, and activating impurities to form an N-type heavily doped source-drain region, as shown in fig. 4 (h).
And 9, manufacturing a source electrode and a drain electrode of the GaN high electron mobility transistor device.
And etching SiN of a source region and a drain region on the SiN/AlGaN/GaN island by adopting a reactive ion etching and electron beam evaporation process, sequentially depositing 22nm thick titanium metal, 140nm thick aluminum metal, 55nm thick nickel metal and 45nm thick gold metal on the source region and the drain region to form a source electrode and a drain electrode of the GaN high electron mobility transistor, and annealing for 30s in a nitrogen atmosphere at 875 ℃ to enable the source electrode and the drain electrode to form ohmic contact with AlGaN. As shown in fig. 4 (i).
Step 10, fabricating a gate electrode of a GaN high electron mobility transistor device.
SiN in a gate region on the SiN/AlGaN/GaN island is etched by adopting a reactive ion etching and electron beam evaporation process, and nickel metal with the thickness of 50nm and gold metal with the thickness of 150nm are sequentially deposited on the gate region to form a gate electrode of the GaN high electron mobility transistor, as shown in (j) of fig. 4.
And 11, manufacturing a gate dielectric layer of the Si metal oxide semiconductor field effect transistor device and a passivation layer of the GaN high electron mobility transistor.
An atomic layer deposition process is adopted to deposit 30nm thick aluminum oxide on the whole sample at 300 ℃ under the condition of nitrogen atmosphere, and the aluminum oxide is used as a gate dielectric layer of a Si metal oxide semiconductor field effect transistor device and a passivation layer of a GaN high electron mobility transistor, as shown in fig. 4 (k).
And step 12, manufacturing a gate electrode of the Si metal oxide semiconductor field effect transistor device.
A magnetron sputtering process is used to sputter tantalum nitride 200nm thick on an aluminum oxide film over an undoped monocrystalline silicon film as the gate electrode of a Si mosfet device, as shown in fig. 4 (l).
And 13, manufacturing a source electrode and a drain electrode of the Si metal oxide semiconductor field effect transistor device.
Etching the aluminum oxide on the monocrystalline silicon film source/drain region by adopting wet etching and electron beam evaporation processes, and depositing nickel metal with the thickness of 60nm to form a source/drain electrode of the Si metal oxide semiconductor field effect transistor; and annealing for 1min in nitrogen atmosphere at 400 ℃ to enable the source electrode and the drain electrode to form ohmic contact with the heavily doped source region, as shown in fig. 4 (m).
Step 14, electrode opening.
And etching the oxide film covered on the source and drain electrodes of the GaN high electron mobility transistor completely by using an HF solution with the concentration of 5% by adopting a wet etching process, and partially etching the oxide film covered on the gate electrode so as to expose the gate, source and drain electrodes of the GaN high electron mobility transistor outside.
And step 15, manufacturing a source field plate and a metal interconnection line.
Firstly, adopting photoetching, electron beam evaporation and a process to manufacture a photoresist mask on the surface of the device obtained in the step 14), and forming a source field plate pattern with the effective length of 2.5 mu m on a source electrode and a passivation layer of a GaN high electron mobility transistor by using the photoresist mask, and forming a metal interconnection pattern between the two devices;
then, a 300nm thick aluminum metal film is deposited on the photoresist mask, and then the acetone solution is used for stripping the redundant metal, so that the source electrode of the GaN high electron mobility transistor is directly connected with the metal film to form a source field plate, and meanwhile metal interconnection is respectively formed between the drain electrode of the Si device and the source electrode of the GaN device and between the source electrode of the Si device and the gate electrode of the GaN device, and the whole device is manufactured, as shown in (o) of fig. 4.
Example 2: a single-chip heterogeneous integrated Cascode structure field effect transistor based on a source field plate with a single crystal silicon film thickness of 100nm is prepared on a silicon carbide substrate.
And step A, preparing a SiN/AlGaN/GaN/silicon carbide substrate.
Sequentially extending a GaN buffer layer and an AlGaN barrier layer on a silicon carbide substrate by adopting a metal organic chemical vapor deposition and atomic layer deposition process; and depositing an SiN isolation layer on the AlGaN barrier layer to obtain the SiN/AlGaN/GaN/silicon carbide substrate, as shown in fig. 4 (p).
And B, forming single crystal silicon film island isolation on the SOI wafer.
Selecting an SOI wafer with a single crystal silicon film thickness of 100nm and a buried oxide layer thickness of 200nm, as shown in FIG. 4 (a);
a single crystal silicon thin film island is etched on the upper part of the SOI wafer by using a photolithography process and a reactive ion etching process, as shown in fig. 4 (b).
And C, partially etching the exposed buried oxide layer.
The implementation of this step is the same as that of step 3 of example 1, as shown in fig. 4 (c).
And D, manufacturing a photoresist anchor point.
The implementation of this step is the same as that of step 4 of example 1, as shown in fig. 4 (d).
And E, completely etching the whole buried oxide layer to release the monocrystalline silicon film.
The implementation of this step is the same as that of step 5 of example 1, as shown in fig. 4 (e).
Step F, transferring the monocrystalline silicon film onto the SiN/AlGaN/GaN/silicon carbide substrate, as shown in FIG. 4 (F).
Transfer printing 100nm monocrystalline silicon film on SOI wafer onto SiN/AlGaN/GaN/silicon carbide substrate with SiN isolation layer thickness 175nm, alGaN barrier layer thickness 25nm, gaN buffer layer thickness 1.5 μm, silicon carbide substrate thickness 450 μm by transfer printing technique, concretely realizing:
f1 Placing the SiN/AlGaN/GaN/silicon carbide substrate in acetone, absolute ethyl alcohol and deionized water in sequence, respectively ultrasonically cleaning for 10min, and drying by a nitrogen gun;
f2 Attaching the solid polydimethylsiloxane PDMS to the SOI wafer etched with the buried oxide layer, and separating the solid polydimethylsiloxane PDMS and the SOI wafer at a speed of 10cm/s, wherein the polydimethylsiloxane PDMS is an elastic adhesive object, and the surface adhesion force is in direct proportion to the separation speed, so that the PDMS has larger adhesion force due to the rapid separation, so that the monocrystalline silicon film is adhered to the polydimethylsiloxane PDMS;
f3 The solid polydimethylsiloxane PDMS adhered with the monocrystalline silicon film is attached to the SiN/AlGaN/GaN/silicon carbide substrate, and then the solid polydimethylsiloxane PDMS and the SiN/AlGaN/GaN/silicon carbide substrate are separated at the speed of 1mm/s, so that the silicon film is obtained by the SiN/AlGaN/GaN/silicon carbide substrate, and the transfer printing of the silicon film is completed.
And G, manufacturing island isolation of the Si metal oxide semiconductor field effect transistor and the GaN high electron mobility transistor.
And (3) performing isolation groove etching on the SiN/AlGaN/GaN/silicon carbide substrate with the transferred monocrystalline silicon film by adopting photoetching and reactive ion etching processes to cut off two-dimensional electron gas so as to form Si/SiN/AlGaN/GaN islands and SiN/AlGaN/GaN islands on two sides of the isolation groove respectively, as shown in fig. 4 (g).
And step H, manufacturing a source region and a drain region of the Si metal oxide semiconductor field effect transistor.
The implementation of this step is the same as that of step 8 of example 1, as shown in fig. 4 (h).
And step I, manufacturing a source electrode and a drain electrode of the GaN high electron mobility transistor device.
The implementation of this step is the same as step 9 of example 1, as shown in fig. 4 (i).
And step J, manufacturing a gate electrode of the GaN high electron mobility transistor device.
SiN in a gate region on the SiN/AlGaN/GaN island is etched by adopting a reactive ion etching and electron beam evaporation process, and nickel metal with the thickness of 55nm and gold metal with the thickness of 175nm are sequentially deposited on the gate region to form a gate electrode of the GaN high electron mobility transistor, as shown in (j) of fig. 4.
And step K, manufacturing a gate dielectric layer of the Si metal oxide semiconductor field effect transistor device and a passivation layer of the GaN high electron mobility transistor.
Depositing 25nm thick aluminum dioxide on the whole sample by adopting an atomic layer deposition process at the temperature of 300 ℃ and under the nitrogen atmosphere, wherein the aluminum dioxide is used as a gate dielectric layer of a Si metal oxide semiconductor field effect transistor device and a passivation layer of a GaN high electron mobility transistor, as shown in fig. 4 (k);
and step L, manufacturing a gate electrode of the Si metal oxide semiconductor field effect transistor device.
A 150nm thick tantalum nitride is sputtered on an aluminum oxide film over an undoped monocrystalline silicon film using a magnetron sputtering process as the gate electrode of a Si metal oxide semiconductor field effect transistor as shown in fig. 4 (l).
And M, manufacturing a source electrode and a drain electrode of the Si metal oxide semiconductor field effect transistor device.
And etching the aluminum oxide on the monocrystalline silicon film source/drain region by adopting wet etching and electron beam evaporation processes, depositing nickel metal with the thickness of 45nm to form a source/drain electrode of the Si metal oxide semiconductor field effect transistor, and annealing for 1min in a nitrogen atmosphere with the temperature of 400 ℃ to enable the source/drain electrode and the heavily doped source/drain region to form ohmic contact, as shown in fig. 4 (m).
And step N, opening holes on the electrode.
The implementation of this step is the same as step 14 of example 1, as shown in fig. 4 (n).
And step O, manufacturing a source field plate and a metal interconnection line.
O1) adopting photoetching, electron beam evaporation and a process to manufacture a photoresist mask on the surface of the device obtained in the step N, wherein the photoresist mask forms a source field plate pattern with the effective length of 3 mu m above a source electrode and a passivation layer of a GaN high electron mobility transistor, and forms a metal interconnection pattern between the two devices;
02 A 250nm thick aluminum metal film is deposited on the photoresist mask, and then the acetone solution is used for stripping the redundant metal, so that the source electrode of the GaN high electron mobility transistor is directly connected with the metal film to form a source field plate, and meanwhile, metal interconnection is respectively formed between the drain electrode of the Si device and the source electrode of the GaN device and between the source electrode of the Si device and the gate electrode of the GaN device, so that the whole device is manufactured, as shown in (o) of fig. 4.
Example 3: a single-chip heterogeneous integrated Casode structure field effect transistor based on a source field plate with a single crystal silicon film thickness of 150nm is prepared on a silicon substrate.
Step one, preparing a SiN/AlGaN/GaN/silicon substrate.
Sequentially extending a GaN buffer layer and an AlGaN barrier layer on a silicon substrate by adopting a metal organic chemical vapor deposition and atomic layer deposition process; and depositing an SiN isolation layer on the AlGaN barrier layer to obtain the SiN/AlGaN/GaN/silicon substrate, as shown in fig. 4 (p).
And step two, forming single crystal silicon film island isolation on the SOI wafer.
Selecting an SOI wafer with a single crystal silicon film thickness of 150nm and a buried oxide layer thickness of 200nm, as shown in FIG. 4 (a);
a single crystal silicon thin film island is etched on the upper part of the SOI wafer by using a photolithography process and a reactive ion etching process, as shown in fig. 4 (b).
And thirdly, partially etching the exposed buried oxide layer.
The implementation of this step is the same as that of step 3 of example 1, as shown in fig. 4 (c).
And step four, manufacturing a photoresist anchor point.
The implementation of this step is the same as that of step 4 of example 1, as shown in fig. 4 (d).
And fifthly, completely etching the whole buried oxide layer to release the monocrystalline silicon film.
The implementation of this step is the same as that of step 5 of example 1, as shown in fig. 4 (e).
Step six, transferring the monocrystalline silicon film onto the SiN/AlGaN/GaN/silicon substrate, as shown in FIG. 4 (f).
Transferring a 150nm monocrystalline silicon film on an SOI wafer onto a SiN/AlGaN/GaN/silicon substrate with 150nm SiN isolation layer thickness, 20nm AlGaN barrier layer thickness, 1 μm GaN buffer layer thickness and 400 μm silicon substrate thickness by adopting a transfer printing technology, wherein the method is concretely realized as follows:
6.1 Placing the SiN/AlGaN/GaN/silicon substrate in acetone, absolute ethyl alcohol and deionized water in sequence, respectively ultrasonically cleaning for 10min, and drying by a nitrogen gun;
6.2 Attaching the solid polydimethylsiloxane PDMS to the SOI wafer etched with the buried oxide layer, and separating the solid polydimethylsiloxane PDMS and the SOI wafer at a speed of 10cm/s, wherein the polydimethylsiloxane PDMS is an elastic adhesive object, and the surface adhesion force is in direct proportion to the separation speed, so that the PDMS has larger adhesion force due to the rapid separation, so that the monocrystalline silicon film is adhered to the polydimethylsiloxane PDMS;
6.3 The solid polydimethylsiloxane PDMS adhered with the monocrystalline silicon film is attached to the SiN/AlGaN/GaN/silicon substrate, and then the solid polydimethylsiloxane PDMS and the SiN/AlGaN/GaN/silicon substrate are separated at the speed of 1mm/s, so that the silicon film is adhered on the SiN/AlGaN/GaN/silicon substrate, and the transfer printing of the silicon film is completed.
And step seven, manufacturing island isolation of the Si metal oxide semiconductor field effect transistor and the GaN high electron mobility transistor.
And (3) performing isolation groove etching on the SiN/AlGaN/GaN/silicon substrate on which the monocrystalline silicon film is transferred by adopting photoetching and reactive ion etching processes to cut off two-dimensional electron gas, and respectively forming Si/SiN/AlGaN/GaN islands and SiN/AlGaN/GaN islands at two sides of the isolation groove, as shown in fig. 4 (g).
And step eight, manufacturing a source region and a drain region of the Si metal oxide semiconductor field effect transistor.
The implementation of this step is the same as that of step 8 of example 1, as shown in fig. 4 (h).
And step nine, manufacturing a source electrode and a drain electrode of the GaN high electron mobility transistor device.
The implementation of this step is the same as step 9 of example 1, as shown in fig. 4 (i).
And step ten, manufacturing a gate electrode of the GaN high electron mobility transistor device.
SiN in a gate region on the SiN/AlGaN/GaN island is etched by adopting a reactive ion etching and electron beam evaporation process, and nickel metal with the thickness of 50nm and gold metal with the thickness of 200nm are sequentially deposited on the gate region to form a gate electrode of the GaN high electron mobility transistor, as shown in (j) of fig. 4.
And step eleven, manufacturing a gate dielectric layer of the Si metal oxide semiconductor field effect transistor device and a passivation layer of the GaN high electron mobility transistor.
An atomic layer deposition process is adopted to deposit aluminum dioxide with the thickness of 20nm on the whole sample at the temperature of 300 ℃ and under the nitrogen atmosphere, and the aluminum dioxide is used as a gate dielectric layer of a Si metal oxide semiconductor field effect transistor device and a passivation layer of a GaN high electron mobility transistor, as shown in fig. 4 (k).
And step twelve, manufacturing a gate electrode of the Si metal oxide semiconductor field effect transistor device.
Tantalum nitride of 100nm thickness is sputtered on an aluminum oxide film over an undoped monocrystalline silicon film as the gate electrode of a Si metal oxide semiconductor field effect transistor using a magnetron sputtering process, as shown in fig. 4 (l).
And thirteenth step, manufacturing the source electrode and the drain electrode of the Si metal oxide semiconductor field effect transistor device.
And etching the aluminum oxide on the source and drain regions of the monocrystalline silicon thin film by adopting wet etching and electron beam evaporation processes, depositing nickel metal with the thickness of 30nm to form source and drain electrodes of the Si metal oxide semiconductor field effect transistor, and annealing for 1min in a nitrogen atmosphere with the temperature of 400 ℃ to enable the source and drain electrodes and the heavily doped source and drain regions to form ohmic contact, as shown in fig. 4 (m).
Fourteen, opening holes on the electrode.
The implementation of this step is the same as step 14 of example 1, as shown in fig. 4 (n).
And fifteen, manufacturing a source field plate and a metal interconnection line.
15.1 Manufacturing a photoresist mask on the surface of the device obtained in the fourteen steps by adopting photoetching, electron beam evaporation and a process, and forming a source field plate pattern with the effective length of 3.5 mu m on the source electrode and the passivation layer of the GaN high electron mobility transistor by using the photoresist mask, so as to form a metal interconnection pattern between the two devices;
15.2 A 200nm thick aluminum metal film is deposited on the photoresist mask, and the redundant metal is stripped by using acetone solution, so that the source electrode of the GaN high electron mobility transistor is directly connected with the metal film to form a source field plate, and meanwhile, metal interconnection is respectively formed between the drain electrode of the Si device and the source electrode of the GaN device and between the source electrode of the Si device and the gate electrode of the GaN device, and the whole device is manufactured, as shown in (o) of fig. 4.
The above description is only three specific examples of the invention and does not constitute any limitation of the invention, it will be apparent to those skilled in the art that various modifications and changes in form and details may be made without departing from the principles, construction of the invention, but these modifications and changes based on the idea of the invention are still within the scope of the claims of the invention.

Claims (6)

1. A manufacturing method of a single-chip heterogeneous integrated Casode structure field effect transistor based on a source field plate is characterized by comprising the following steps:
1) Preparing a SiN/AlGaN/GaN/substrate:
sequentially extending a GaN buffer layer and an AlGaN barrier layer on a substrate by adopting a metal organic chemical vapor deposition and atomic layer deposition process;
depositing an SiN isolation layer on the AlGaN barrier layer to obtain a SiN/AlGaN/GaN/substrate;
2) Forming a monocrystalline silicon film island on the SOI wafer by adopting photoetching and reactive ion etching processes;
3) Placing the sample obtained in the step 2) into 49% HF solution by adopting a wet etching process, and etching away the buried oxide layer which is not covered by the monocrystalline silicon film island;
4) Adopting a photoetching process to manufacture anchor points at the edges of the monocrystalline silicon thin film so as to prevent the displacement and falling of the monocrystalline silicon thin film after the buried oxide layer is completely etched in the follow-up process;
5) A wet etching process is adopted, a sample with an anchor point is put into 49% HF solution, and the buried oxide layer is completely etched, so that the monocrystalline silicon film falls on the substrate of the SOI wafer;
6) Transferring the monocrystalline silicon film obtained in the step 5) onto a SiN/AlGaN/GaN/substrate by adopting a transfer printing technology;
7) Etching 300-350nm deep isolation grooves on the sample obtained in the step 6) by adopting photoetching and reactive ion etching processes, and respectively forming Si/SiN/AlGaN/GaN islands and SiN/AlGaN/GaN islands at two sides of the isolation grooves;
8) The ion implantation process is adopted, and the implantation dosage is 5 multiplied by 10 on the monocrystalline silicon film of Si/SiN/AlGaN/GaN island 15 cm −2 Phosphorus ions with an energy of 30keV and a concentration of 1000 ◦ Annealing for 60s in the nitrogen atmosphere of C to activate impurities and form an N-type heavily doped source drain region;
9) Etching SiN of a source region and a drain region on the SiN/AlGaN/GaN island by adopting a reactive ion etching and electron beam evaporation process, depositing a metal lamination on the source region and the drain region to form a source electrode and a drain electrode of the GaN high electron mobility transistor, and annealing for 30s in a nitrogen atmosphere with the temperature of 875 ℃ to enable the source electrode and the drain electrode to form ohmic contact with the AlGaN barrier layer;
10 Etching SiN of a gate region on the SiN/AlGaN/GaN island by adopting a reactive ion etching and electron beam evaporation process, and sequentially depositing nickel metal with the thickness of 45-70nm and gold metal with the thickness of 100-200nm on the gate region to form a gate electrode of the GaN high electron mobility transistor;
11 Depositing an oxide film with the thickness of 20-30nm on the whole sample by adopting an atomic layer deposition process under the temperature condition of 300 ℃ and the nitrogen atmosphere to form a gate dielectric layer of the Si metal oxide semiconductor field effect transistor and a passivation layer of the GaN high electron mobility transistor;
12 Sputtering tantalum nitride with the thickness of 100-200nm on the oxide film above the undoped monocrystalline silicon film by adopting a magnetron sputtering process to form a gate electrode of the Si metal oxide semiconductor field effect transistor;
13 Etching oxide films on the monocrystalline silicon film source and drain regions by adopting wet etching and electron beam evaporation processes, depositing nickel metal with the thickness of 30-100nm to form source and drain electrodes of the Si metal oxide semiconductor field effect transistor, and annealing for 1min in a nitrogen atmosphere with the temperature of 400 ℃ to enable the source and drain electrodes and the heavily doped source and drain regions to form ohmic contact;
14 Etching all the oxide film covered on the source and drain electrodes of the GaN high electron mobility transistor by using HF solution with the concentration of 5%, and partially etching the oxide film covered on the gate electrode so as to expose the gate, source and drain electrodes of the GaN high electron mobility transistor outside;
15 Source field plate and metal interconnect) are fabricated:
15a) Manufacturing a photoresist mask on the surface of the device obtained in the step 14) by adopting photoetching, electron beam evaporation and a process, wherein the photoresist mask forms a source field plate pattern with the effective length of 2.5-3.5 mu m above a source electrode and a passivation layer of a GaN high electron mobility transistor, and forms a metal interconnection pattern between the two devices;
15b) And depositing a layer of metal film with the thickness of 200-300nm on the photoresist mask, stripping redundant metal by using an organic solvent so as to enable a source electrode of the GaN high electron mobility transistor to be directly connected with the metal film to form a source field plate, and simultaneously forming metal interconnection between a drain electrode of the Si device and a source electrode of the GaN device and between the source electrode of the Si device and a gate electrode of the GaN device respectively to finish the manufacture of the whole device.
2. The method of claim 8, wherein the implementation of 6) is as follows:
6a) Sequentially placing the SiN/AlGaN/GaN/substrate in acetone, absolute ethyl alcohol and deionized water, respectively ultrasonically cleaning for 10min, and blow-drying by a nitrogen gun;
6b) Attaching solid polydimethylsiloxane PDMS to the SOI wafer etched with the buried oxide layer, and separating the solid polydimethylsiloxane PDMS and the SOI wafer at a speed of 10cm/s to enable the monocrystalline silicon film to be adhered to the polydimethylsiloxane PDMS;
6c) And attaching the solid polydimethylsiloxane PDMS adhered with the monocrystalline silicon film to the SiN/AlGaN/GaN/substrate, and separating the solid polydimethylsiloxane PDMS from the SiN/AlGaN/GaN/substrate at a speed of 1mm/s to adhere the silicon film to the SiN/AlGaN/GaN/substrate, thereby completing transfer printing of the monocrystalline silicon film.
3. The method of claim 1, wherein the metal stack of 9) is, in order from bottom to top: titanium metal 22nm thick, aluminum metal 140nm thick, nickel metal 55nm thick, gold metal 45nm thick.
4. The method according to claim 1, characterized in that: the whole device comprises a substrate (1), a GaN buffer layer (2), an AlGaN barrier layer (3) and a SiN isolation layer (4) from bottom to top, wherein an isolation groove (17) which is deep to the GaN buffer layer (2) is engraved in the middle of the SiN isolation layer (4); an Si active layer (5) is arranged on the SiN isolation layer (4) at one side of the isolation groove (17), a first source electrode (10) and a first drain electrode (13) are arranged on two sides of the Si active layer (5), a gate dielectric layer (11) is arranged between the source electrode and the drain electrode, and a first gate electrode (12) is arranged on the gate dielectric layer (11) to form an Si metal oxide semiconductor field effect transistor; a second source electrode (6), a second gate electrode (7) and a second drain electrode (8) are transversely and sequentially arranged on the AlGaN barrier layer (3) at the other side of the isolation groove (17), and a passivation layer (16) is arranged above a region between the source electrode and the drain electrode to form a GaN high electron mobility transistor; an active field plate (9) is deposited above the second source electrode (6) and the passivation layer (16), and the source field plate (9) and the second source electrode (6) form a contact field plate structure so as to improve the fringe electric field distribution of the second gate electrode (7) and improve the breakdown characteristic of the field effect transistor with the Casode structure.
5. The method of claim 4, wherein: the first drain electrode (13) and the second source electrode (6) are electrically connected through a first metal interconnection strip (14);
the first source electrode (10) and the second gate electrode (7) are electrically connected by a second metal interconnection strip (15).
6. The method of claim 4, wherein: the source field plate (9), the first metal interconnection strips (14) and the second metal interconnection strips (15) are all made of the same metal material;
the gate dielectric layer (11) between the first source electrode (10) and the first drain electrode (13) and the passivation layer (16) on the area between the second source electrode (6) and the second drain electrode (8) are made of the same oxide material.
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