CN109786376B - Cascode structure GaN high electron mobility transistor based on monolithic heterogeneous integration and manufacturing method - Google Patents
Cascode structure GaN high electron mobility transistor based on monolithic heterogeneous integration and manufacturing method Download PDFInfo
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Abstract
The invention discloses a monolithic heterogeneous integration-based gallium nitride high-electron-mobility transistor with a Cascode structure, which mainly solves the problem that the existing gallium nitride high-electron-mobility transistor with the Cascode structure cannot be monolithically integrated. It includes: the GaN-based high-electron-mobility transistor comprises a substrate (1), a GaN buffer layer (2), an AlGaN barrier layer (3) and a Si active layer (4), wherein an isolation groove is formed in the middle of the AlGaN barrier layer (3) and used for electrically isolating a GaN high-electron-mobility transistor and a Si metal oxide semiconductor field effect transistor; and a Si active layer (4) is printed on the AlGaN barrier layer (3) on one side of the isolation groove to form a monolithic chip with silicon and gallium nitride heterointegrated. The invention enhances the reliability of the device, reduces the volume size of the micro system, improves the integration level of the chip, and can be used for the scene of power control and conversion of a power converter and an inverter.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a manufacturing method of a GaN high electron mobility transistor with a Cascode structure, which can be used as a power converter or a phase inverter of automobiles, aerospace and power stations.
Technical Field
In the background of the era of post moore's law, it has become very difficult to increase the degree of integration by means of conventional shrinking transistor dimensions. The current electronic systems are developing toward miniaturization, diversification and intellectualization, and finally form microsystems with functions of perception, communication, processing, transmission and the like. The core technology of microsystems is integration, and the integration technology is developing from planar integration to three-dimensional integration, from chip level to system integration with higher integration and complexity. In recent years, semiconductor process technology has been rapidly developed, and is embodied not only in conventional semiconductor processes such as radio frequency, analog, and mixed signal, but also in non-conventional semiconductor processes such as heterogeneous integration of systems. Heterogeneous integration is classified into hybrid integration and monolithic integration. Hybrid integration is an integration mode realized by bonding chips of different substrate materials through packaging, and represents a technology of three-dimensional chip stacking, which is similar to the concept of System In Package (SiP); the monolithic integration is to integrate devices with different functions on a single chip, so that the packaging of the chips is omitted, but the manufacturing difficulty of the process for realizing the monolithic integration by growing heterogeneous materials through an epitaxial method is higher, the quality of the epitaxial materials is limited by the lattice mismatch degree between the epitaxial materials and a substrate material, if the lattice mismatch degree is too high, a large number of defects can be generated in the epitaxial layers, even single crystals can not be grown, and the performance and the service life of the devices are influenced.
In the late 20 th century and 80 s, scientists have grown high-quality GaN and AlGaN on silicon carbide and sapphire substrates by inserting a gallium nitride buffer layer, and then GaN high-electron-mobility transistors have entered the rapid development period. GaN hemt devices have many advantages: the high-voltage-resistant and high-frequency-resistant power supply has the advantages of high working voltage and working frequency, low on resistance, small input and output capacitance and high radiation resistance and high temperature resistance. Due to the above advantages, GaN hemts are often used in power electronics and microwave fields, and enhancement GaN hemts also have advantages of reducing design cost and expanding application fields compared to depletion GaN hemts. For example, when designing a microwave high-power chip, the enhancement mode GaN hemt device does not need a power supply design with negative gate voltage because of having a positive threshold voltage, which greatly reduces the design cost of the chip; in addition, enhancement mode GaN hemts are turned on only at positive gate voltages and thus can be used in low power digital circuits. Because of the many advantages of enhancement mode GaN hemts, much research has been conducted on them. In order to realize the enhancement GaN hemt device, various manufacturing methods are used, wherein a common method is to use a Cascode structure composed of a low-voltage enhancement Si MOS fet and a high-voltage depletion GaN hemt device, as shown in fig. 1. By the structure, the GaN high electron mobility transistor device which is originally in a depletion mode can be more conveniently conducted to work when forward grid voltage is applied.
Currently, international rectifier corporation IR and Transform corporation are both working on developing enhancement GaN hemt devices based on this structure. However, until now, the fabrication of the GaN hemt device with the Cascode structure is still based on hybrid integration, that is, the GaN hemt device is implemented by packaging and bonding a silicon chip and a gallium nitride chip, as shown in fig. 2, the chip fabricated by the method has low integration level and large area, cannot meet the development requirements of miniaturization and high integration of the electronic system, and is not beneficial to the continuation of moore's law.
Disclosure of Invention
The invention aims to provide a monolithic heterogeneous integration-based GaN high electron mobility transistor with a Cascode structure and a manufacturing method thereof aiming at the defects of the prior art, so as to reduce the process difficulty of monolithic integration, enhance the reliability of devices, reduce the volume size of a microsystem, improve the integration level of a chip and realize the continuation of the Moore's law.
The technical key point for realizing the aim is as follows: the method comprises the following steps of transferring a monocrystalline silicon film on an AlGaN/GaN/substrate by adopting a transfer printing technology, and manufacturing a GaN high electron mobility transistor with a Cascode structure on the basis of the transfer printing technology, wherein the realization scheme is as follows:
1. a monolithic heterogeneous integration-based GaN high electron mobility transistor with a Cascode structure is formed by combining a GaN high electron mobility transistor and a Si metal oxide semiconductor field effect transistor, and comprises: substrate, GaN buffer layer, AlGaN barrier layer, Si active layer, its characterized in that:
an isolation groove is formed in the middle of the AlGaN barrier layer and used for electrically isolating the GaN high electron mobility transistor and the Si metal oxide semiconductor field effect transistor;
and the Si active layer is printed on the AlGaN barrier layer (3) on one side of the isolation groove to form a monolithic chip with silicon and gallium nitride heterointegrated.
Further, the transistor is characterized in that: the isolation groove in the middle of the AlGaN barrier layer is deep to the GaN buffer layer so as to cut off two-dimensional electron gas and prevent electric leakage between devices.
Further, the transistor is characterized in that:
the substrate, the GaN buffer layer and the AlGaN barrier layer are distributed from bottom to top, a source electrode and a drain electrode of a Si metal oxide semiconductor field effect transistor are arranged on two sides of the Si active layer, a gate dielectric layer is arranged between the source electrode and the drain electrode, and a gate electrode is arranged on the gate dielectric layer;
and the AlGaN barrier layer on the other side of the isolation groove is provided with a source electrode, a gate electrode and a drain electrode of the GaN high electron mobility transistor.
Further, the transistor is characterized in that:
a first metal interconnection strip for forming electrical connection is arranged between a drain electrode of the Si metal oxide semiconductor field effect transistor and a source electrode of the GaN high electron mobility transistor;
the source electrode of the Si metal oxide semiconductor field effect transistor and the gate electrode of the GaN high electron mobility transistor are provided with a second metal interconnection bar for forming electrical connection.
2. A manufacturing method of a monolithic heterogeneous integration-based GaN high electron mobility transistor with a Cascode structure is characterized by comprising the following steps:
1) forming a monocrystalline silicon thin film isolated island on the SOI substrate by adopting photoetching and reactive ion etching processes;
2) injecting phosphorus ions into the monocrystalline silicon film by adopting an ion injection process, and annealing for 20s at 900 ℃ in a nitrogen atmosphere to activate impurities to form an N-type heavily doped source drain region;
3) placing a source drain region sample with formed N-type heavy doping into 49% HF solution for 15min by adopting a wet etching process, and etching a part of exposed buried oxide layer;
4) manufacturing anchor points on the edge of the monocrystalline silicon film by adopting a photoetching process so as to prevent the displacement and falling off of the monocrystalline silicon film after the buried oxide layer is completely etched subsequently;
5) putting the sample with the anchor points into 49% HF solution for 2h by adopting a wet etching process, and completely etching the buried oxide layer to enable the monocrystalline silicon film to fall on the substrate;
6) transferring the monocrystalline silicon film with the thickness of 200nm obtained in the step 5) onto an AlGaN/GaN/sapphire substrate by adopting a transfer printing technology;
7) etching two-dimensional electron gas in the sample obtained in the step 6) by adopting photoetching and reactive ion etching processes to form an AlGaN/GaN island with the height of 100-150 nm;
8) depositing titanium metal with the thickness of 22nm, aluminum metal with the thickness of 140nm, nickel metal with the thickness of 55nm and gold metal with the thickness of 45nm on the AlGaN/GaN island in sequence by adopting an electron beam evaporation process to form a source drain electrode of the GaN HEMT device, and annealing for 30s in a nitrogen atmosphere at the temperature of 875 ℃ to enable the source drain electrode to form ohmic contact with the AlGaN;
9) depositing nickel metal with the thickness of 30-100nm on a monocrystalline silicon thin film island by adopting an electron beam evaporation process to form a source drain electrode of the Si metal oxide semiconductor field effect transistor device, and annealing for 1min in a nitrogen atmosphere at the temperature of 400 ℃ to form ohmic contact between the source drain electrode and a heavily doped source drain region;
10) depositing nickel metal with the thickness of 45nm and metal gold with the thickness of 100nm on the AlGaN/GaN isolated island in sequence by adopting an electron beam evaporation process to form a gate electrode of the GaN HEMT device;
11) depositing aluminum sesquioxide with the thickness of 10-20nm on the whole sample by adopting an atomic layer deposition process at the temperature of 300 ℃ and in a nitrogen atmosphere to serve as a gate dielectric layer of a Si metal oxide semiconductor field effect transistor device; sputtering tantalum nitride with the thickness of 100-200nm on the monocrystalline silicon thin film island by adopting a magnetron sputtering process to serve as a gate electrode of the Si metal oxide semiconductor field effect transistor device;
12) adopting a reactive ion etching process to completely etch the aluminum oxide coated on the gate source drain electrodes of the Si metal oxide semiconductor field effect transistor device and the GaN high electron mobility transistor device in the sample obtained in the step 11) so as to expose the gate source drain electrodes of the two devices outside;
13) and depositing 100-300nm thick aluminum metal on the aluminum oxide dielectric layer by adopting an electron beam evaporation process to form metal interconnection between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor, thereby completing the manufacture of the GaN high electron mobility transistor based on the monolithic heterogeneous integration.
Compared with the prior art, the invention not only greatly simplifies the monolithic heterogeneous integration process of Si and Ga N because the transfer printing technology is used as the monolithic heterogeneous integration means, but also greatly reduces the monolithic integration process difficulty, enhances the reliability of the device, reduces the volume size of a micro system, improves the chip integration level and continues the Moore's law by the Cascode structure enhanced GaN high electron mobility transistor device realized by the method.
Drawings
FIG. 1 is a schematic circuit diagram of a Cascode structure GaN HEMT device;
FIG. 2 is a schematic diagram of a prior art Cascode structure GaN HEMT device;
FIG. 3 is a schematic cross-sectional structure of the present invention;
FIG. 4 is a top view of FIG. 3;
fig. 5 is a schematic flow chart of the present invention for fabricating a Cascode structure GaN hemt device.
Detailed Description
Referring to fig. 3 and 4, the monolithic heterointegration-based GaN high electron mobility transistor of the present invention comprises, from bottom to top: 400-500 mu m thick substrate 1, 1-2 mu m thick GaN buffer layer 2, and 20-30nm thick AlGaN barrier layer 3. An isolation groove is formed in the middle of the AlGaN barrier layer 3 and extends to the GaN buffer layer 2 to cut off two-dimensional electron gas and prevent electric leakage between devices. The substrate material can be a sapphire substrate, a SiC substrate or a silicon substrate.
A Si active layer 4 with the thickness of 100-200nm is printed on the AlGaN barrier layer 3 on one side of the isolation groove, and a source electrode 8 and a drain electrode 11 with the thickness of 30-100nm are arranged on two sides of the Si active layer 4; aluminum oxide with the thickness of 10-20nm is arranged between the source electrode and the drain electrode to be used as a gate dielectric layer 9; a gate electrode 10 with the thickness of 100-200nm is arranged on the gate dielectric layer 9 to form the Si metal oxide semiconductor field effect transistor.
The AlGaN barrier layer 3 on the other side of the isolation groove is provided with a source electrode 5 and a drain electrode 7 with the thickness of 262nm, and a gate electrode 6 with the thickness of 145nm is arranged between the source electrode and the drain electrode to form the GaN high electron mobility transistor.
A first metal interconnection bar 12 with the thickness of 200-300nm is arranged between the drain electrode 11 of the Si metal oxide semiconductor field effect transistor and the source electrode 5 of the GaN high electron mobility transistor and is used for electrically connecting the two devices; a second metal interconnection strip 13 with the thickness of 200 and 300nm is arranged between the source electrode 8 of the Si metal oxide semiconductor field effect transistor and the gate electrode 6 of the GaN high electron mobility transistor and is used for electrically connecting the two devices, so that a silicon and gallium nitride hetero-integrated single chip is formed.
Referring to fig. 5, the method of fabricating a monolithic heterointegration-based GaN high electron mobility transistor of the present invention gives the following three examples.
Example 1: preparing a monolithic heterogeneous integrated Cascode structure gallium nitride high electron mobility transistor with the monocrystalline silicon thin film thickness of 200 nm.
Selecting an SOI substrate with the thickness of a monocrystalline silicon film of 200nm and the thickness of a buried oxide layer of 200nm, as shown in FIG. 5 (a);
and etching a monocrystalline silicon film isolated island on the upper part of the SOI substrate by adopting a photoetching process and a reactive ion etching process, as shown in figure 5 (b).
And 2, doping the monocrystalline silicon thin film to form a source drain region.
Adopting an ion implantation process to implant 5 multiplied by 10 dosage on the monocrystalline silicon film15cm-2Forming an N-type heavily doped source drain region by using phosphorus ions with the energy of 30 keV;
the impurities are activated by annealing for 20s at 900 c in a nitrogen atmosphere using a rapid thermal annealing process, as shown in fig. 5 (c).
And 3, partially etching the exposed buried oxide layer.
And (d) placing the SOI substrate subjected to ion implantation into 49% HF solution for 15min by adopting a wet etching process, and etching away part of the exposed buried oxide layer, as shown in FIG. 5 (d).
And 4, manufacturing a photoresist anchor point.
By using the photolithography process, anchor points are formed at the edge of the single crystal silicon thin film on the SOI substrate to prevent the single crystal silicon thin film from shifting and falling off after the buried oxide layer is completely etched, as shown in fig. 5 (e).
And 5, completely etching the whole buried oxide layer to release the monocrystalline silicon film.
The SOI substrate was placed in a 49% HF solution for 2h using a wet etch process to completely etch the buried oxide layer, as shown in fig. 5 (f).
The transfer printing technology is adopted to transfer the 200nm monocrystalline silicon film on the SOI substrate to the AlGaN/GaN/sapphire substrate with the thickness of the AlGaN barrier layer being 30nm, the thickness of the GaN buffer layer being 2 mu m and the thickness of the sapphire substrate being 500 mu m, and the specific implementation is as follows:
6a) sequentially placing the AlGaN/GaN/sapphire substrate in acetone, absolute ethyl alcohol and deionized water, respectively ultrasonically cleaning for 10min, and then blowing by using a nitrogen gun;
6b) coupling cured polydimethylsiloxane PDMS with the upper surface of a silicon SOI on an insulating substrate, and separating the two systems at a speed of 10cm/s, wherein the polydimethylsiloxane PDMS is an elastic viscous object, so that the surface adhesion is in direct proportion to the separation rate, and the PDMS has large adhesion due to rapid separation, so that a monocrystalline silicon film can be adhered to the polydimethylsiloxane PDMS;
6c) the polydimethylsiloxane PDMS adhered with the monocrystalline silicon film is coupled with the AlGaN/GaN/sapphire substrate, and then the two systems are separated at the speed of 1mm/s, because the polydimethylsiloxane PDMS is separated at a low speed, the adhesion force of the polydimethylsiloxane PDMS to the silicon film is smaller than that of the silicon film and the AlGaN/GaN/sapphire substrate, so that the silicon film can be obtained by the AlGaN/GaN/sapphire substrate, and the transfer printing of the silicon film is completed.
And 7, manufacturing isolated island isolation of the GaN high electron mobility transistor device.
And etching the AlGaN/GaN/sapphire substrate transferred with the monocrystalline silicon film by adopting photoetching and reactive ion etching processes to cut off two-dimensional electron gas to form an AlGaN/GaN isolated island, as shown in a figure 5 (h).
And 8, manufacturing a source electrode and a drain electrode of the GaN high electron mobility transistor device.
And (2) sequentially depositing 22nm of metal titanium, 140nm of metal aluminum, 55nm of metal nickel and 45nm of metal gold on the AlGaN/GaN island by adopting an electron beam evaporation process to form a source drain electrode of the GaN high electron mobility transistor device, and annealing for 30s in a nitrogen atmosphere at the temperature of 875 ℃ to enable the source drain electrode to form ohmic contact with the AlGaN. As in fig. 5 (i).
And 9, manufacturing a source electrode and a drain electrode of the Si metal oxide semiconductor field effect transistor device.
Depositing 100nm metallic nickel on the monocrystalline silicon thin film island by adopting an electron beam evaporation process to form a source drain electrode of the Si metal oxide semiconductor field effect transistor device, and annealing for 1min in a nitrogen atmosphere at the temperature of 400 ℃ to form ohmic contact between the source drain electrode and the heavily doped source drain region, as shown in figure 5 (j).
And step 10, manufacturing a gate electrode of the GaN high electron mobility transistor device.
And sequentially depositing 45nm metal nickel and 100nm metal gold on the AlGaN/GaN island by adopting an electron beam evaporation process to form a gate electrode of the GaN HEMT device, as shown in FIG. 5 (k).
And 11, manufacturing a gate dielectric of the Si metal oxide semiconductor field effect transistor device.
Depositing aluminum sesquioxide with the thickness of 20nm on the sample obtained in the step 10 by adopting an atomic layer deposition process at the temperature of 300 ℃ and in a nitrogen atmosphere to serve as a gate dielectric layer of the Si metal oxide semiconductor field effect transistor device, as shown in fig. 5 (l);
and sputtering tantalum nitride with the thickness of 150nm on the monocrystalline silicon thin film island by adopting a magnetron sputtering process to be used as a gate electrode of the Si metal oxide semiconductor field effect transistor device, as shown in figure 5 (m).
And step 12, opening holes in the electrodes.
And (3) completely etching the aluminum oxide coated on the source and drain electrodes of the Si metal oxide semiconductor field effect transistor and the GaN HEMT on the sample obtained in the step (11) by adopting a reactive ion etching process so as to expose the source and drain electrodes of the two devices, as shown in FIG. 5 (n).
And step 13, manufacturing a metal interconnection bar between the two devices.
And depositing aluminum metal with the thickness of 300nm on the aluminum oxide dielectric layer by adopting an electron beam evaporation process to form metal interconnection between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the gate electrode of the GaN high electron mobility transistor, and finishing the manufacture of the GaN high electron mobility transistor based on the monolithic heterogeneous integration structure, as shown in figure 5 (o).
Example 2: preparing a monolithic heterogeneous integrated Cascode structure gallium nitride high electron mobility transistor with a monocrystalline silicon thin film thickness of 100 nm.
Step one, forming monocrystalline silicon film isolated island on an SOI substrate.
Selecting an SOI substrate with a monocrystalline silicon film thickness of 100nm and a buried oxide layer thickness of 200nm, as shown in FIG. 5 (a);
and etching a monocrystalline silicon film isolated island on the upper part of the SOI substrate by adopting a photoetching process and a reactive ion etching process, as shown in figure 5 (b).
And step two, doping the monocrystalline silicon film to form a source drain region, such as 5 (c).
The specific implementation of this step is the same as step 2 of example 1.
Step three, partially etching the exposed buried oxide layer, as shown in fig. 5 (d). .
The specific implementation of this step is the same as in step 3 of example 1.
And step four, manufacturing the photoresist anchor point, as shown in fig. 5 (e).
The specific implementation of this step is the same as in step 4 of example 1.
And step five, completely etching the whole buried oxide layer to release the monocrystalline silicon thin film, as shown in figure 5 (f).
The specific implementation of this step is the same as step 5 of example 1.
Sixthly, the monocrystalline silicon thin film of 100nm on the SOI substrate is transferred to the AlGaN/GaN/SiC substrate of which the AlGaN barrier layer thickness is 20nm, the GaN buffer layer thickness is 1 μm and the SiC substrate thickness is 400 μm, as shown in FIG. 5 (g).
The specific implementation of this step is the same as step 6 of example 1.
And seventhly, manufacturing island isolation of the GaN high electron mobility transistor device, as shown in the figure 5 (h).
The specific implementation of this step is the same as in step 7 of example 1.
And step eight, manufacturing a source electrode and a drain electrode of the GaN HEMT device, as shown in FIG. 5 (i).
The specific implementation of this step is the same as step 8 of example 1.
And step nine, manufacturing a source electrode and a drain electrode of the Si metal oxide semiconductor field effect transistor device.
Depositing 30nm of metallic nickel on the monocrystalline silicon thin film island by adopting an electron beam evaporation process to form a source drain electrode of the Si metal oxide semiconductor field effect transistor device, and annealing for 1min in a nitrogen atmosphere at the temperature of 400 ℃ to form ohmic contact between the source drain electrode and the heavily doped source drain region, as shown in figure 5 (j).
Step ten, a gate electrode of the GaN hemt device is fabricated, as shown in fig. 5 (k).
The specific implementation of this step is the same as step 10 of example 1.
And eleventh, manufacturing a gate dielectric of the Si metal oxide semiconductor field effect transistor device.
Depositing aluminum sesquioxide with the thickness of 10nm on the sample obtained in the step ten by adopting an atomic layer deposition process at the temperature of 300 ℃ and in a nitrogen atmosphere to serve as a gate dielectric layer of the Si metal oxide semiconductor field effect transistor device, as shown in figure 5 (l); and sputtering tantalum nitride with the thickness of 100nm on the monocrystal silicon thin film island by adopting a magnetron sputtering process to be used as a gate electrode of the Si metal oxide semiconductor field effect transistor device, as shown in figure 5 (m).
Step twelve, opening the electrode, as shown in fig. 5 (n).
The specific implementation of this step is the same as step 12 of example 1.
And thirteen, manufacturing a metal interconnection bar between the two devices.
And depositing aluminum metal with the thickness of 200nm on the aluminum oxide dielectric layer by adopting an electron beam evaporation process so as to form metal interconnection between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor respectively, and finishing the manufacture of the GaN high electron mobility transistor based on the monolithic heterogeneous integration structure, as shown in figure 5 (o).
Example 3: preparing a monolithic heterogeneous integrated Cascode structure gallium nitride high electron mobility transistor with a monocrystalline silicon thin film thickness of 150 nm.
And step A, forming monocrystalline silicon thin film isolated island on the SOI substrate.
Selecting an SOI substrate with a monocrystalline silicon film thickness of 150nm and a buried oxide layer thickness of 200nm, as shown in FIG. 5 (a); and a photoetching process and a reactive ion etching process are adopted to etch a monocrystalline silicon film isolated island on the upper part of the SOI substrate, as shown in figure 5 (b).
And step B, doping the monocrystalline silicon thin film to form a source drain region, as shown in figure 5 (c).
The specific implementation of this step is the same as step 2 of example 1.
Step C, partially etching the exposed buried oxide layer, as shown in FIG. 5(d)
The specific implementation of this step is the same as in step 3 of example 1.
And D, manufacturing a photoresist anchor point as shown in the figure 5 (e).
The specific implementation of this step is the same as in step 4 of example 1.
Step E, the entire buried oxide layer is completely etched to release the single crystal silicon thin film, as shown in fig. 5 (f).
The specific implementation of this step is the same as step 5 of example 1.
Step F, transfer the single crystal silicon thin film to the AlGaN/GaN/silicon substrate base as shown in FIG. 5 (g).
Transferring the 150nm monocrystalline silicon film on the SOI substrate to an AlGaN/GaN/silicon substrate with the thickness of an AlGaN barrier layer being 25nm, the thickness of a GaN buffer layer being 1.5 mu m and the thickness of a silicon substrate being 450 mu m by adopting a transfer printing technology;
the specific implementation of this step is the same as step 6 of example 1.
Step G, forming an isolated island of the GaN hemt device, as shown in fig. 5 (h).
The specific implementation of this step is the same as in step 7 of example 1.
And step H, manufacturing a source electrode and a drain electrode of the GaN HEMT device, as shown in FIG. 5 (i).
The specific implementation of this step is the same as step 8 of example 1.
And step I, manufacturing a source electrode and a drain electrode of the Si metal oxide semiconductor field effect transistor device.
And depositing 60nm of metallic nickel on the monocrystalline silicon thin film island by adopting an electron beam evaporation process to form a source drain electrode of the Si metal oxide semiconductor field effect transistor device, and annealing for 1min in a nitrogen atmosphere at the temperature of 400 ℃ to form ohmic contact between the source drain electrode and the heavily doped source drain region, as shown in figure 5 (j).
Step J, a gate electrode of the GaN hemt device is fabricated, as shown in fig. 5 (k).
The specific implementation of this step is the same as step 10 of example 1.
And step K, manufacturing a gate dielectric of the Si metal oxide semiconductor field effect transistor device.
Depositing aluminum sesquioxide with the thickness of 15nm on the sample obtained in the step J by adopting an atomic layer deposition process at the temperature of 300 ℃ and in a nitrogen atmosphere to serve as a gate dielectric layer of the Si metal oxide semiconductor field effect transistor device, as shown in a figure 5 (l); and sputtering tantalum nitride with the thickness of 120nm on the monocrystalline silicon thin film island by adopting a magnetron sputtering process to be used as a gate electrode of the Si metal oxide semiconductor field effect transistor device, as shown in figure 5 (m).
Step L, opening the electrode, as shown in FIG. 5 (n).
The specific implementation of this step is the same as step 12 of example 1.
And step M, manufacturing a metal interconnection bar between the two devices.
And depositing aluminum metal with the thickness of 250nm on the aluminum oxide dielectric layer by adopting an electron beam evaporation process so as to form metal interconnection between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor respectively, and finishing the manufacture of the GaN high electron mobility transistor based on the monolithic heterogeneous integration structure, as shown in figure 5 (o).
The foregoing description is only three specific examples of the present invention and is not intended to limit the invention, so that it will be apparent to those skilled in the art that various changes and modifications in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (3)
1. A manufacturing method of a GaN high electron mobility transistor with a Cascode structure based on monolithic heterogeneous integration is disclosed, wherein the GaN high electron mobility transistor is formed by combining a GaN metal oxide semiconductor field effect transistor and a Si metal oxide semiconductor field effect transistor, and comprises a substrate (1), a GaN buffer layer (2), an AlGaN barrier layer (3) and a Si active layer (4); an isolation groove is formed in the middle of the AlGaN barrier layer (3) and used for electrically isolating the GaN high electron mobility transistor and the Si metal oxide semiconductor field effect transistor; the Si active layer (4) is printed on the AlGaN barrier layer (3) on one side of the isolation groove to form a monolithic chip with silicon and gallium nitride heterointegrated; the method is characterized by comprising the following steps:
1) forming a monocrystalline silicon thin film isolated island on the SOI substrate by adopting photoetching and reactive ion etching processes;
2) injecting phosphorus ions into the monocrystalline silicon film by adopting an ion injection process, and annealing for 20s at 900 ℃ in a nitrogen atmosphere to activate impurities to form an N-type heavily doped source drain region;
3) placing a source drain region sample with formed N-type heavy doping into 49% HF solution for 15min by adopting a wet etching process, and etching a part of exposed buried oxide layer;
4) manufacturing anchor points on the edge of the monocrystalline silicon film by adopting a photoetching process so as to prevent the displacement and falling off of the monocrystalline silicon film after the buried oxide layer is completely etched subsequently;
5) putting the sample with the anchor points into 49% HF solution for 2h by adopting a wet etching process, and completely etching the buried oxide layer to enable the monocrystalline silicon film to fall on the substrate;
6) transferring the 200nm monocrystalline silicon film obtained in the step 5) onto an AlGaN/GaN/substrate by adopting a transfer printing technology;
7) etching two-dimensional electron gas in the sample obtained in the step 6) by adopting photoetching and reactive ion etching processes to form an AlGaN/GaN island with the height of 100-150 nm;
8) depositing titanium metal with the thickness of 22nm, aluminum metal with the thickness of 140nm, nickel metal with the thickness of 55nm and gold metal with the thickness of 45nm on the AlGaN/GaN island in sequence by adopting an electron beam evaporation process to form a source drain electrode of the GaN HEMT device, and annealing for 30s in a nitrogen atmosphere at the temperature of 875 ℃ to enable the source drain electrode to form ohmic contact with the AlGaN;
9) depositing nickel metal with the thickness of 30-100nm on a monocrystalline silicon thin film island by adopting an electron beam evaporation process to form a source drain electrode of the Si metal oxide semiconductor field effect transistor device, and annealing for 1min in a nitrogen atmosphere at the temperature of 400 ℃ to form ohmic contact between the source drain electrode and a heavily doped source drain region;
10) depositing nickel metal with the thickness of 45nm and metal gold with the thickness of 100nm on the AlGaN/GaN isolated island in sequence by adopting an electron beam evaporation process to form a gate electrode of the GaN HEMT device;
11) depositing aluminum sesquioxide with the thickness of 10-20nm on the whole sample by adopting an atomic layer deposition process at the temperature of 300 ℃ and in a nitrogen atmosphere to serve as a gate dielectric layer of a Si metal oxide semiconductor field effect transistor device; sputtering tantalum nitride with the thickness of 100-200nm on the monocrystalline silicon thin film island by adopting a magnetron sputtering process to serve as a gate electrode of the Si metal oxide semiconductor field effect transistor device;
12) adopting a reactive ion etching process to completely etch the aluminum oxide coated on the gate source drain electrodes of the Si metal oxide semiconductor field effect transistor device and the GaN high electron mobility transistor device in the sample obtained in the step 11) so as to expose the gate source drain electrodes of the two devices outside;
13) and depositing 100-300nm thick aluminum metal on the aluminum oxide dielectric layer by adopting an electron beam evaporation process to form metal interconnection between the drain electrode of the Si metal oxide semiconductor field effect transistor and the source electrode of the GaN high electron mobility transistor and between the source electrode of the Si metal oxide semiconductor field effect transistor and the grid electrode of the GaN high electron mobility transistor, thereby completing the manufacture of the GaN high electron mobility transistor based on the monolithic heterogeneous integration.
2. The method of claim 1, wherein the implementation of 6) is as follows:
6a) sequentially placing the AlGaN/GaN/substrate in acetone, absolute ethyl alcohol and deionized water, respectively ultrasonically cleaning for 10min, and then blowing by using a nitrogen gun;
6b) coupling the cured polydimethylsiloxane PDMS with the upper surface of the silicon SOI on the insulating substrate, and separating the two systems at the speed of 10cm/s to adhere the monocrystalline silicon film on the polydimethylsiloxane PDMS;
6c) and coupling the polydimethylsiloxane PDMS adhered with the monocrystalline silicon film with the AlGaN/GaN/substrate, and separating the two systems at the speed of 1mm/s so as to adhere the silicon film to the AlGaN/GaN/sapphire substrate to finish the transfer printing of the silicon film.
3. The method of claim 1, wherein the ion implantation dose in 2) is 5 x 1015cm-2The implantation energy was 30 keV.
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