CN111863615A - Semiconductor packaging later-period curing method - Google Patents
Semiconductor packaging later-period curing method Download PDFInfo
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- CN111863615A CN111863615A CN202010735406.XA CN202010735406A CN111863615A CN 111863615 A CN111863615 A CN 111863615A CN 202010735406 A CN202010735406 A CN 202010735406A CN 111863615 A CN111863615 A CN 111863615A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Abstract
The invention provides a later-stage curing method for semiconductor packaging, which comprises the following steps of S1, charging into a furnace at a low temperature, heating the temperature in the furnace to 50 ℃, putting a product into the furnace, and heating the temperature in the furnace to 175 ℃; s2, curing at high temperature, and controlling the temperature in the furnace at 120-175 ℃; s3, cooling the furnace, and reducing the temperature in the furnace to 50 ℃ within 40 min; s4, discharging, taking out the product, and cooling at room temperature; the invention has the beneficial effects that: the temperature of the product entering the furnace and the temperature of the product exiting the furnace are reduced, so that the temperature of the product is slowly raised and lowered, the internal stress of the product is eliminated, and the poor layering ratio is reduced from 2.49% to 0.6%; curing at high temperature, keeping the temperature at 175 ℃ for 120min, cooling for 30min, and keeping the temperature at 120 ℃ for 120 min; in the curing process, the internal stress is gradually released, the poor material layering ratio is reduced to 0, the high-temperature duration is reduced, and energy is saved; the temperature of the product discharged from the furnace is reduced, the room temperature cooling time is shortened, the total curing time of the product in the later period of the PMC is close, and the production efficiency cannot be reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a later-period curing method for semiconductor packaging.
Background
The whole process of semiconductor device production is generally divided into a wafer manufacturing process and a sealing and testing process, wherein the sealing and testing process generally comprises the working procedures of wafer thinning, back evaporation, wafer scribing, wafer mounting, bonding, packaging, later-stage curing, high-temperature storage, deburring, tin dipping, rib cutting, testing and sorting, printing, packaging and the like.
The conventional process comprises three steps of charging, constant temperature and discharging, wherein as shown in figure 1, the charging temperature is 150 ℃, the product is charged, the temperature is raised to 175 ℃ after the product is charged, the constant temperature of 175 ℃ is kept for 400min, and finally the product is discharged at 175 ℃ and cooled for 60min at room temperature; under the process, the poor rate of delamination of the product is about 2.49%, and how to reduce the poor rate of delamination of the product is a problem to be solved at present.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a later curing method for semiconductor packaging.
The invention solves the technical problems through the following technical means:
the post-curing method for semiconductor package comprises the following steps,
s1 low-temperature furnace entering
Heating the temperature in the furnace to 50 ℃, putting the product into the furnace, and heating the temperature in the furnace to 175 ℃;
s2 high temperature curing
Controlling the temperature in the furnace at 120-175 ℃;
s3 reducing temperature in furnace
Reducing the temperature in the furnace to 50 ℃ within 40 min;
s4 discharging
The product was taken out and left to cool at room temperature.
As a further improvement of the technology, the product is placed in the S1 and heated to 175 ℃ for 27 min.
As a further improvement of the above technique, the duration of S2 is 510 min.
As a further improvement of the technology, the high-temperature curing of S2 comprises two stages, wherein the first stage is constant temperature of 175 ℃, and the second stage is constant temperature of 120 ℃.
As a further improvement of the technology, the duration of the first stage is 120min, the duration of the second stage is 120min, and the temperature of the first stage in the furnace is reduced to the temperature of the second stage after 30 min.
As a further improvement of the above technology, in S3, the cooling duration is 40 min.
The invention has the beneficial effects that: by reducing the temperature of the product entering the furnace and the temperature of the product exiting the furnace, the temperature is slowly increased and decreased compared with the common process, the internal stress of the product material is eliminated, and the poor material layering ratio is reduced from 2.49% to 0.6%.
Setting two stages of high-temperature curing, namely a second stage of cooling the high-temperature curing from a first stage of keeping the temperature at 175 ℃ for 120min to a second stage of keeping the temperature at 120 ℃ for 120 min; in the curing process, the internal stress of the material is gradually released, the poor layering ratio of the material is reduced to 0, and meanwhile, the high-temperature duration is reduced, so that the energy-saving effect is achieved; when the high-temperature curing time is prolonged, the temperature of the product discharged from the furnace is reduced, the room-temperature cooling time after the product is discharged from the furnace is reduced, the total time of the product in the later curing period of the PMC is close, and the production efficiency cannot be reduced.
Drawings
FIG. 1 is a graph showing a temperature change in a conventional process;
FIG. 2 is a graph illustrating temperature variation in the post-curing method for semiconductor packaging according to the present embodiment;
FIG. 3 is a photograph of a C-SAM layered scan of a layered product obtained in a conventional process;
FIG. 4 is a photograph of a C-SAM layered scan of a layered product obtained in example 1;
FIG. 5 is a photograph of a C-SAM layered scan of a product obtained in example 1, in which no layering has occurred;
FIG. 6 is a photograph of a C-SAM layered scan of a product obtained in example 2, in which no delamination occurred.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Example 1
The post-curing method for semiconductor package comprises the following steps,
s1 low-temperature furnace entering
Heating the temperature in the furnace to 50 ℃, putting the product in the furnace, and heating the temperature in the furnace to 175 ℃ for 27 min;
s2 high temperature curing
Controlling the temperature in the furnace at 175 ℃ and keeping for 480 min; .
S3 reducing temperature in furnace
Reducing the temperature in the furnace to 50 ℃ within 40 min;
s4 discharging
The product was taken out and left to cool at room temperature.
As shown in fig. 4, a C-SAM layered scan picture of a product for the appearance of a layer for the product; as shown in fig. 5, a C-SAM layered scanning picture of the product without layering; scanning pictures of products produced in one week are taken for comparison, and the delamination rate and the delamination failure rate are 0.6%.
Example 2
The post-curing method for semiconductor package comprises the following steps,
s1 low-temperature furnace entering
Heating the temperature in the furnace to 50 ℃, putting the product in the furnace, and heating the temperature in the furnace to 175 ℃ for 27 min;
s2 high temperature curing
Controlling the temperature in the furnace at 175 ℃ below zero and 120-; .
S3 reducing temperature in furnace
Reducing the temperature in the furnace to 50 ℃ within 40 min;
s4 discharging
The product was taken out and left to cool at room temperature.
As shown in fig. 6, a C-SAM layered scanning picture of the product without layering; scanning pictures of products produced in one week are taken for comparison, and the delamination rate and the delamination failure rate are 0%.
By reducing the temperature of the product entering the furnace and the temperature of the product exiting the furnace, the temperature is slowly increased and decreased compared with the common process, the internal stress of the product material is eliminated, and the poor material layering ratio is reduced from 2.49% to 0.6%.
Setting two stages of high-temperature curing, namely a second stage of cooling the high-temperature curing from a first stage of keeping the temperature at 175 ℃ for 120min to a second stage of keeping the temperature at 120 ℃ for 120 min; in the curing process, the internal stress of the material is gradually released, the poor layering ratio of the material is reduced to 0, and meanwhile, the high-temperature duration is reduced, so that the energy-saving effect is achieved; when the high-temperature curing time is prolonged, the temperature of the product discharged from the furnace is reduced, the room-temperature cooling time after the product is discharged from the furnace is reduced, the total time of the product in the later curing period of the PMC is close, and the production efficiency cannot be reduced.
It is noted that, in this document, relational terms such as first and second, and the like, if any, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. The post-curing method for the semiconductor packaging is characterized by comprising the following steps: comprises the following steps of (a) carrying out,
s1 low-temperature furnace entering
Heating the temperature in the furnace to 50 ℃, putting the product into the furnace, and heating the temperature in the furnace to 175 ℃;
s2 high temperature curing
Controlling the temperature in the furnace at 120-175 ℃;
s3 reducing temperature in furnace
Reducing the temperature in the furnace to 50 ℃ within 40 min;
s4 discharging
The product was taken out and left to cool at room temperature.
2. The semiconductor package post-cure method of claim 1, wherein: after the product was placed in S1, it was heated to 175 ℃ over 27 min.
3. The semiconductor package post-cure method of claim 1, wherein: the duration of the S2 is 510 min.
4. The semiconductor package post-curing method of claim 3, wherein: the high-temperature curing of the S2 comprises two stages, wherein the first stage is constant temperature of 175 ℃, and the second stage is constant temperature of 120 ℃.
5. The semiconductor package post-curing method of claim 4, wherein: the duration time of the first stage is 120min, the duration time of the second stage is 120min, and the temperature of the first stage in the furnace is reduced to the temperature of the second stage after 30 min.
6. The semiconductor package post-cure method of claim 1, wherein: and in the step S3, the cooling duration is 40 min.
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| CN202010735406.XA CN111863615A (en) | 2020-07-28 | 2020-07-28 | Semiconductor packaging later-period curing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113206011A (en) * | 2021-03-18 | 2021-08-03 | 中国科学院微电子研究所 | Processing method and device for reducing optical waveguide loss |
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| US6200913B1 (en) * | 1998-11-12 | 2001-03-13 | Advanced Micro Devices, Inc. | Cure process for manufacture of low dielectric constant interlevel dielectric layers |
| CN101714598A (en) * | 2009-09-25 | 2010-05-26 | 深圳莱特光电有限公司 | Method for layering and precipitating fluorescent powder in packaging process of white LED |
| CN105047727A (en) * | 2015-06-03 | 2015-11-11 | 重庆鹰谷光电有限公司 | Silica gel embedding technology for photoelectric detector with ceramic tube casing |
| CN105556645A (en) * | 2013-09-17 | 2016-05-04 | 德卡技术股份有限公司 | Two step method of rapid curing a semiconductor polymer layer |
| CN106098914A (en) * | 2016-08-09 | 2016-11-09 | 杭州天之圣光电子有限公司 | A kind of LED glue package curing process |
| CN111128757A (en) * | 2019-12-31 | 2020-05-08 | 中国电子科技集团公司第四十七研究所 | Method for controlling water vapor and hydrogen content in integrated circuit sealed cavity |
-
2020
- 2020-07-28 CN CN202010735406.XA patent/CN111863615A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6200913B1 (en) * | 1998-11-12 | 2001-03-13 | Advanced Micro Devices, Inc. | Cure process for manufacture of low dielectric constant interlevel dielectric layers |
| CN101714598A (en) * | 2009-09-25 | 2010-05-26 | 深圳莱特光电有限公司 | Method for layering and precipitating fluorescent powder in packaging process of white LED |
| CN105556645A (en) * | 2013-09-17 | 2016-05-04 | 德卡技术股份有限公司 | Two step method of rapid curing a semiconductor polymer layer |
| CN105047727A (en) * | 2015-06-03 | 2015-11-11 | 重庆鹰谷光电有限公司 | Silica gel embedding technology for photoelectric detector with ceramic tube casing |
| CN106098914A (en) * | 2016-08-09 | 2016-11-09 | 杭州天之圣光电子有限公司 | A kind of LED glue package curing process |
| CN111128757A (en) * | 2019-12-31 | 2020-05-08 | 中国电子科技集团公司第四十七研究所 | Method for controlling water vapor and hydrogen content in integrated circuit sealed cavity |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113206011A (en) * | 2021-03-18 | 2021-08-03 | 中国科学院微电子研究所 | Processing method and device for reducing optical waveguide loss |
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