CN111863114A - Chip sampling quasi-position determining method and device - Google Patents
Chip sampling quasi-position determining method and device Download PDFInfo
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- CN111863114A CN111863114A CN201910353218.8A CN201910353218A CN111863114A CN 111863114 A CN111863114 A CN 111863114A CN 201910353218 A CN201910353218 A CN 201910353218A CN 111863114 A CN111863114 A CN 111863114A
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Abstract
The embodiment of the disclosure provides a chip sampling level determination method, a chip sampling level determination device, a computer readable medium and an electronic device. The chip sampling level determining method comprises the following steps: acquiring a data signal on a specified channel of a chip to be tested; setting a plurality of first test sampling points for the data signal according to a first interval; determining a first signal or a second signal corresponding to each first test sampling point according to the quasi-level voltage; sequencing the corresponding first signals or second signals according to the sequence of the sampling positions corresponding to the first test sampling points; and determining the sampling level of the chip to be tested according to the sorted first signal and second signal. The technical scheme of the embodiment of the disclosure can realize automatic and accurate positioning of the sampling quasi-position of the chip to be detected.
Description
Technical Field
The present disclosure relates to the field of chip testing technologies, and in particular, to a method and an apparatus for determining a chip sampling level, a computer readable medium, and an electronic device.
Background
When a memory chip is tested for reading data through a tester, a signal sampling point of the tester needs to be determined first. Because the time starting points of the data signals output by each memory chip are different, if the data signals output by the memory chips are sampled by inaccurate signal sampling points, a tester may sample wrong signals, which causes inaccurate read data, thereby affecting test results.
Therefore, how to accurately position the sampling level of the memory chip is a technical problem to be solved.
Disclosure of Invention
An object of the embodiments of the present disclosure is to provide a method and an apparatus for determining a chip sampling level, a computer readable medium, and an electronic device, so as to achieve accurate positioning of the sampling level of a memory chip at least to a certain extent.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
According to an aspect of the embodiments of the present disclosure, there is provided a chip sampling level determining method, including: acquiring a data signal on a specified channel of a chip to be tested; setting a plurality of first test sampling points for the data signal according to a first interval; determining a first signal or a second signal corresponding to each first test sampling point according to the quasi-level voltage; sequencing the corresponding first signals or second signals according to the sequence of the sampling positions corresponding to the first test sampling points; and determining the sampling level of the chip to be tested according to the sorted first signal and second signal.
According to an aspect of the disclosed embodiments, there is provided a chip sampling level determining apparatus, including: the data signal acquisition module is configured to acquire a data signal on a specified channel of the chip to be tested; the first sampling setting module is configured to set a plurality of first test sampling points for the data signal according to a first interval; the digital signal conversion module is configured to determine a first signal or a second signal corresponding to each first test sampling point according to the level voltage; the digital signal sequencing module is configured to sequence the corresponding first signal or second signal according to the sequence of the sampling positions corresponding to the first test sampling points; and the sampling level determining module is configured to determine the sampling level of the chip to be tested according to the sorted first signal and second signal.
According to an aspect of the embodiments of the present disclosure, there is provided a computer readable medium, on which a computer program is stored, the computer program, when being executed by a processor, implementing the chip sampling level determination method as described in the above embodiments.
According to an aspect of an embodiment of the present disclosure, there is provided an electronic device including: one or more processors; a storage device for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement the chip sample level determination method as described in the above embodiments.
In the technical solutions provided in some embodiments of the present disclosure, a data signal of an assigned channel of a chip to be tested is read by using a programmable function of a testing machine and a language rule of the chip to be tested, then a plurality of first test sampling points are respectively set for the data signal according to a first interval, and a sampling signal of each first test sampling point is converted into a first signal or a second signal by comparing with a level voltage, so that a sampling level of the chip to be tested can be determined according to the first signal and the second signal, on one hand, the sampling level of the testing machine to different chips to be tested can be calibrated by this way, testing time is reduced, and testing is more automated; on the other hand, the accuracy of the sampling quasi-position of the chip to be tested can be improved, so that the accuracy of a subsequent test result can be ensured, and even in high-speed test, a tester can be ensured to sample an accurate signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:
fig. 1 schematically illustrates a read timing definition schematic of a DRAM chip according to one embodiment of the present disclosure;
FIG. 2 schematically illustrates a schematic diagram of an inaccurate signal sampling point;
FIG. 3 schematically illustrates a diagram of accurate signal sampling points;
FIG. 4 schematically illustrates a flow chart of a method of chip sample level determination according to one embodiment of the present disclosure;
FIG. 5 schematically illustrates a flowchart of step S3 of FIG. 4 in one embodiment;
FIG. 6 schematically illustrates a schematic diagram of a first test sampling point of a data signal, according to one embodiment of the present disclosure;
FIG. 7 schematically illustrates a schematic diagram of converting first test sample points to digital signals of 1's and 0's, according to one embodiment of the present disclosure;
FIG. 8 schematically illustrates a flowchart of step S5 of FIG. 4 in one embodiment;
FIG. 9 schematically illustrates a flowchart of step S51 of FIG. 8 in one embodiment;
FIG. 10 schematically illustrates a flow diagram of step S513 of FIG. 9 in one embodiment;
FIG. 11 schematically illustrates a coarse sampling followed by a fine sampling according to one embodiment of the present disclosure;
FIG. 12 schematically illustrates a system architecture diagram of a chip sampling level determination method according to one embodiment of the present disclosure;
FIG. 13 schematically illustrates a block diagram of an on-chip sampling level determining apparatus according to one embodiment of the present disclosure;
FIG. 14 illustrates a schematic structural diagram of a computer system suitable for use in implementing the electronic device of an embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the disclosure.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.
The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
Fig. 1 schematically shows a read timing definition diagram of a DRAM (Dynamic Random access memory) chip according to one embodiment of the present disclosure.
As shown in FIG. 1, tDQSCKThe phase difference between a data strobe signal DQS and a clock signal CK of the DRAM chip is referred to; t is tDQSQWhich refers to a phase difference between the data strobe signal DQS and the output data signal DQ.
As can be seen from fig. 1, when testing the accuracy of the data read by the DRAM, the tester needs to first determine the signal sampling points of the tester. The timing starting point of the DRAM outputting the data signal DQ is related to the phase difference between the data signal DQ and the clock signal CK. I.e. t in fig. 1DQSCKAnd tDQSQIt is related. The time starting point of the output data signal DQ of the memory chip is equal to tDQSCKPlus tDQSQ. But t of each memory chipDQSCKAnd tDQSQThey are not all the same, so the time starting points of the data signals DQ output by each memory chip are different. Since only the starting point in time, t, of the clock signal CK is knownDQSCKAnd tDQSQIs unknown, so that a time starting point of an actual output data signal DQ is unknown. Therefore, especially in the high-speed testing of DRAM, it is necessary to first calibrate the sampling levels of the tester for different memory chips to be tested, so as to ensure the accuracy of the testing result.
Fig. 2 schematically shows a schematic diagram of an inaccurate signal sampling point. As shown in fig. 2, it can be seen that if the signal sampling level is not calibrated, the test may sample the wrong signal, thereby affecting the test result. Figure 3 schematically shows a schematic diagram of an accurate signal sampling point.
Fig. 4 schematically illustrates a flow chart of a chip sampling level determination method according to one embodiment of the present disclosure. The method provided by the embodiment of the present disclosure may be executed by any electronic device with computing processing capability, for example, the method may be executed by using the programmable capability of a tester, or the tester may be used to collect a data signal of a chip to be tested, sample an analog data signal waveform, and then input the sampled digital signal to another independent processing device, for example, a user terminal and/or a server terminal, for processing.
As shown in fig. 4, the method for determining a sampling level of a chip according to an embodiment of the present disclosure may include the following steps.
In step S1, a data signal on a designated channel of the chip under test is acquired.
In the embodiment of the present disclosure, the chip to be tested refers to a memory chip to be tested. For example, the chip to be tested is a DRAM chip, for example, a DDR4 memory chip, but the disclosure is not limited thereto. The scheme provided by the embodiment of the disclosure can be used for testing the DDR4 memory chip, and particularly aims at capturing the output signal of the DRAM chip in high-speed testing.
In an exemplary embodiment, acquiring the data signal on the designated channel of the chip under test may include: sending a write control signal to the chip to be tested so as to write analog data into the chip to be tested; sending a reading control signal to the chip to be tested so as to read the analog data from the chip to be tested; and receiving a data signal which is output by the appointed channel of the chip to be tested and corresponds to the analog data.
For example, according to the JEDEC standard, "1" and "0" such as "10101010" or "01010101" can be written into a DRAM chip to be tested by using a tester, and the machine word length of the analog data is not limited thereto, and the example of the analog data written in "10101010" will be described below. Then, a tester is used to send a read control signal to the DRAM chip to be tested to enable the DRAM chip to read data, and a specified channel DQ (here, it is assumed that the DRAM chip has eight parallel channels, i.e., DQ0-DQ7, but the present disclosure does not limit the number of pins of the DRAM chip to be tested, and it is assumed that the specified channel is DQ0, but in practice, it is not limited thereto, and any channel may be used) is ensured to output a segment of analog data signal of "10101010". Digital data is read in the test, but actually, the data signal with the waveform is output by the chip to be tested. After the waveform data signal is sampled to determine the high or low voltage condition of the data signal at each sampling point, the digital data of "1" or "0" can be obtained, so the sampling level of the chip to be tested needs to be determined first to obtain the high or low voltage at the accurate position in the waveform data signal.
In step S2, a plurality of first test sample points are set to the data signal at first intervals.
In an exemplary embodiment, the first interval is less than a quarter cycle of the data signal. For example, assuming that the period of the data signal is T, the first interval between the first test sample points set for a given channel is less than T/4.
In step S3, a first signal (e.g., "1") or a second signal (e.g., "0") corresponding to each first sample point is determined according to the level voltage.
In step S4, the corresponding first signals or second signals are sorted in the order of the sampling positions corresponding to the first test sampling points.
In step S5, a sampling level of the chip to be tested is determined according to the sorted first and second signals.
The chip sampling level determining method provided by the embodiment of the disclosure reads a data signal of a specified channel of a chip to be tested by using a programmable function of a testing machine and a language rule of the chip to be tested, then sets a plurality of first testing sampling points for the data signal according to a first interval, and converts the sampling signal of each first testing sampling point into a first signal or a second signal by comparing with a level voltage, so that the sampling level of the chip to be tested can be determined according to the first signal and the second signal, on one hand, the sampling level of the testing machine to different chips to be tested can be calibrated by the method, the testing time is reduced, and the testing is more automatic; on the other hand, the accuracy of the sampling quasi-position of the chip to be tested can be improved, so that the accuracy of a subsequent test result can be ensured, and even in high-speed test, a tester can be ensured to sample an accurate signal.
FIG. 5 schematically illustrates a flowchart of step S3 of FIG. 4 in one embodiment. As shown in fig. 5, in the embodiment of the present disclosure, the step S3 may further include the following steps.
In step S31, the sampling signal of each first test sampling point is compared with the level voltage respectively to obtain a first comparison result.
By adopting the technical scheme provided by the embodiment of the disclosure, the sampling signal of the first test sampling point and the quasi-potential voltage can be used as two inputs of the voltage comparator, and the voltage comparator can output the comparison result of the sampling signal of the corresponding first test sampling point and the two voltages of the quasi-potential voltage, namely, the first comparison result, namely, the specific sampling voltage of each first test sampling point is not required to be acquired.
In step S32, if the first comparison result is that the sampling signal of the first test sampling point is greater than the level voltage, the corresponding first test sampling point is marked as the first signal (e.g., "1").
In step S33, if the first comparison result is that the sampling signal of the first test sampling point is smaller than the level voltage, the corresponding first test sampling point is marked as the second signal (e.g., "0").
In an exemplary embodiment, determining the sampling level of the chip under test according to the sorted first signal and second signal may include: and if the middle position of a section of continuous first signal or a section of continuous second signal in the sorted first signal and second signal corresponds to a first test sampling point, taking the first test sampling point corresponding to the middle position as the sampling quasi-position of the chip to be tested.
For example, the sampling level of the chip under test can be determined by finding the middle position of a series of consecutive "1" (high voltage portion) in the waveform diagram, or the middle position of a series of consecutive "0" (low voltage portion).
In an exemplary embodiment, determining the sampling level of the chip under test according to the sorted first signal and second signal may include: if the middle position of a section of continuous first signal or a section of continuous second signal in the sequenced first signal and second signal corresponds to two first test sampling points, randomly selecting any one of the two first test sampling points as the sampling quasi-position of the chip to be tested; or taking the intermediate value of the two first test sampling points as the sampling quasi-position of the chip to be tested.
For example, if two "1" exist at the middle position of a continuous segment of "1", the first test sampling point corresponding to any one of the "1" at the two middle positions may be used as the sampling level of the chip to be tested, or the middle value of the "1" at the two middle positions may be used as the sampling level of the chip to be tested. Generally, the smaller the first interval, the higher the precision of the sampling point, and the better the sampling level can be found.
After the sampling level of the chip to be tested is determined, sampling points at intervals of 0.5 period (T/2) from the sampling level are accurate signal sampling points.
Fig. 6 schematically shows a schematic diagram of a first test sampling point of a data signal according to one embodiment of the present disclosure. As shown in fig. 6, it is assumed that a total of 13 first-interval samples, sample 1 to sample 13, are set from DQ 0.
Fig. 7 schematically shows a schematic diagram of converting the first test sample points into digital signals of 1 and 0 according to one embodiment of the present disclosure. As shown in fig. 7, assuming that a total of 21 sampling points from sampling point 1 to sampling point 21 of the first interval are provided, the signal sampled by each sampling point is compared with the reference voltage, if the sampled signal is higher than the reference voltage, the sampling point is set to Pass (as shown by the hatched square in fig. 7), if the sampled signal is lower than the reference voltage, the sampling point is set to Fail (as shown by the blank square in fig. 7), and the resulting states are converted into digital signals, and if Pass is "1" and Fail is "0", 000000111111111100000 can be obtained. And setting the first test sampling point at the middle position of a continuous section of 1 as the optimal test sampling point, namely the sampling level of the chip to be tested, through data processing.
FIG. 8 schematically illustrates a flowchart of step S5 of FIG. 4 in one embodiment.
As shown in fig. 8, in the embodiment of the present disclosure, the step S5 may further include the following steps.
In step S51, two adjacent signal switching positions where the first signal and the second signal are switched are determined.
In an exemplary embodiment, determining two adjacent signal switching positions where the first signal and the second signal are switched may include: taking any one of two first test sampling points corresponding to the first signal and the second signal to be switched in the sequenced first signal and second signal as a signal switching position; or taking the middle value of two first test sampling points corresponding to the first signal and the second signal to be switched in the sequenced first signal and second signal as a signal switching position; and taking the signal switching positions corresponding to the adjacent first signal and second signal to be switched as two adjacent signal switching positions.
Taking fig. 7 as an example, the obtained sequenced first signal and second signal are assumed to be 000000111111111100000, and two first test sampling points corresponding to the first signal and second signal to be switched are sampling point 6 and sampling point 7, and sampling point 16 and sampling point 17, respectively, so that sampling point 6 or sampling point 7 may be used as the first signal switching position, and sampling point 16 or sampling point 17 may also be used as the second signal switching position; alternatively, the intermediate value between sample point 6 and sample point 7 may be set as the first signal switching position, and the intermediate value between sample point 16 and sample point 17 may be set as the second signal switching position.
In step S52, the middle value of the two adjacent signal switching positions is used as the sampling level of the chip under test.
For example, if sampling point 6 is the first signal switching position and sampling point 16 is the second signal switching position, sampling point 6 and sampling point 16 are two adjacent signal switching positions. At this time, the middle value between sampling point 6 and sampling point 16 can be used as the sampling level of the chip under test.
FIG. 9 schematically illustrates a flowchart of step S51 of FIG. 8 in one embodiment. As shown in fig. 9, in the embodiment of the present disclosure, the step S51 may further include the following steps.
In step S511, two adjacent signal switching intervals in each data signal are determined according to two first test sampling points corresponding to two adjacent first signals and second signals to be switched, respectively, in the sorted first signals and second signals.
Also taking fig. 7 as an example, the obtained first signal and second signal are assumed to be 000000111111111100000, and two first test sampling points corresponding to the first signal and second signal to be switched are sampling point 6 and sampling point 7, and sampling point 16 and sampling point 17, respectively, so that the first signal switching interval in each data signal is between sampling point 6 and sampling point 7, and the second signal switching interval is between sampling point 16 and sampling point 17.
In step S512, a second test sampling point is set in two adjacent signal switching intervals of the data signal for each channel according to the second interval.
In an exemplary embodiment, the first interval is less than one-quarter of a period of the data signal, and the second interval is less than one-half of the first interval.
For example, second test sample points spaced at second intervals are provided between the above-described sample point 6 and sample point 7, and second test sample points spaced at second intervals are provided between the above-described sample point 16 and sample point 17.
In step S513, two adjacent signal switching positions are determined according to the sampling signal of the second test sampling point.
Fig. 10 schematically illustrates a flow chart of step S513 of fig. 9 in one embodiment. As shown in fig. 10, in the embodiment of the present disclosure, the step S513 may further include the following steps.
In step S5131, the sampling signal of each second sampling point under test is compared with the level voltage to obtain a second comparison result.
Similarly, by adopting the technical scheme provided by the embodiment of the disclosure, the sampling signal of the second test sampling point and the level voltage can be used as two inputs of the voltage comparator, and the voltage comparator can output the comparison result of the sampling signal of the corresponding second test sampling point and the two voltages of the level voltage, namely, the second comparison result, namely, the specific sampling voltage of each second test sampling point does not need to be acquired.
In step S5132, if the second comparison result indicates that the sampling signal of the second test sampling point is greater than the level voltage, the corresponding second test sampling point is marked as the first signal.
In step S5133, if the second comparison result indicates that the sampling signal of the second test sampling point is smaller than the level voltage, the corresponding second test sampling point is marked as the second signal.
In step S5134, the corresponding first signals or second signals are reordered according to the sequence of the sampling positions corresponding to the second test sampling points.
In step S5135, a signal switching position where two adjacent first signals and second signals are switched is determined in the reordered first signals and second signals.
This is illustrated below with reference to fig. 11. Fig. 11 schematically illustrates a coarse-sampling followed by a fine-sampling schematic according to one embodiment of the present disclosure.
As shown in fig. 11, the first time is coarse sampling, a first test sampling point is set on a data signal of DQ0, assuming that five first test sampling points from sample 1 to sample 5 are provided, and a first interval is provided between adjacent first test sampling points, the sampling signals from sample 1 to sample 5 are respectively compared with a reference voltage to obtain a first signal and a second signal of 00110, where a signal switching position of 0 and 1 is included between sample 2 and sample 3, and a signal switching position of 1 and 0 is included between sample 4 and sample 5, and then an interval from sample 2 to sample 3 and an interval from sample 4 to sample 5 are signal switching intervals. The first interval of the first coarse sampling D1< T/4.
The second time is a fine sample, sample points 6 and 7 are added between sample point 2 and sample point 3, sample points 8 and 9 are added between sample points 4 and 5, sample points 6 and 7 and sample points 8 and 9 are four second test sample points, and there is a second interval between sample point 2 and sample point 6, between sample point 6 and sample point 7, between sample point 7 and sample point 3, and there is a second interval between sample point 4 and sample point 8, between sample point 8 and sample point 9, between sample point 9 and sample point 5. Comparing the sampling signals of the sampling point 2, the sampling point 6, the sampling point 7 and the sampling point 3 with the reference voltage respectively to obtain a first signal and a second signal of 0111, comparing the sampling signals of the sampling point 4, the sampling point 8, the sampling point 9 and the sampling point 5 with the reference voltage respectively to obtain a first signal and a second signal of 1000, wherein a signal switching position of 0 and 1 is contained between the sampling point 2 and the sampling point 6, and a signal switching position of 1 and 0 is contained between the sampling point 4 and the sampling point 8. The second interval of the second sub-fine sampling D2< D1/2. That is, the switching position of 1/0 or 0/1 in the waveform diagram is found, and then the middle value of two adjacent switching positions of 1/0 or 0/1 is used as the sampling level of the chip to be tested.
In this way, if the sampling is a plurality of times of fine sampling, the nth interval of the nth sampling is less than half of the nth-1 interval of the previous sampling, i.e., the nth-1 sampling, and N is a positive integer greater than or equal to 1. For example, if further fine sampling is performed, the interval between sample point 2 and sample point 6 and the interval between sample point 4 and sample point 8 are signal switching intervals, and the fine sampling may be performed at the third interval D3< D2/2 between the two signal switching intervals. If the set preset sampling frequency or preset interval precision is reached, the found sampling quasi-position can reach the required precision, and more detailed sampling can not be carried out.
In order to meet the requirement of sufficient sampling level accuracy, the best test sampling point can be accurately found only by the need of sufficient test sampling points, but the more the test sampling points are, the more the operation times are, and the time consumption is long, in the embodiment of the disclosure, the range of the interval where the signal switching position is located is continuously reduced by a mode of firstly roughly sampling, finding 1/0 or 0/1 switching positions, and then finely sampling between two adjacent signal switching positions, on one hand, the operation times can be reduced, on the other hand, by continuously refining the interval, the accurate signal switching position can be approached, the condition of missing the sampling level can be avoided, the accuracy of the determined switching position is improved, and therefore, the accuracy of the sampling level of the chip to be tested can be finally improved.
Fig. 12 schematically shows a system configuration diagram of a chip sampling level determination method according to an embodiment of the present disclosure. As shown in fig. 12, the DRAM chip outputs a data signal DQ0 to an ATE (Automatic Test Equipment, such as a tester for memory testing, but the disclosure is not limited thereto), the ATE samples DQ0 with different sampling points, compares the sampling signal of each sampling point with a level voltage, converts the sampling signal into a digital signal of 1 and 0, selects an optimal sampling level, and automatically replaces parameters in a Timing file (Timing file) for a later Test.
As shown in fig. 13, the apparatus 1300 for determining a sampling level of a chip according to an embodiment of the present disclosure may include a data signal obtaining module 1310, a first sampling setting module 1320, a digital signal converting module 1330, a digital signal sorting module 1340, and a sampling level determining module 1350.
The data signal acquiring module 1310 may be configured to acquire a data signal on a designated channel of the chip under test. The first sample setting module 1320 may be configured to set a plurality of first test sample points to the data signal at first intervals. The digital signal conversion module 1330 can be configured to determine the first signal or the second signal corresponding to each first test sampling point according to the level voltage. The digital signal ordering module 1340 may be configured to order the respective first signals or second signals in an order of the sampling positions corresponding to the first test sampling points. The sampling level determining module 1350 may be configured to determine the sampling level of the chip to be tested according to the sorted first signal and second signal.
In an exemplary embodiment, the data signal acquisition module 1310 may be configured to: sending a write control signal to the chip to be tested so as to write analog data into the chip to be tested; sending a reading control signal to the chip to be tested so as to read the analog data from the chip to be tested; and receiving a data signal which is output by the appointed channel of the chip to be tested and corresponds to the analog data.
In an exemplary embodiment, the first interval is less than a quarter cycle of the first data signal.
In an exemplary embodiment, the digital signal conversion module 1330 may be configured to: comparing the sampling signal of each first test sampling point with the quasi-level voltage respectively to obtain a first comparison result; if the first comparison result indicates that the sampling signal of the first test sampling point is greater than the quasi-level voltage, marking the corresponding first test sampling point as a first signal; and if the first comparison result shows that the sampling signal of the first test sampling point is smaller than the quasi-level voltage, marking the corresponding first test sampling point as a second signal.
In an exemplary embodiment, the sampling level determination module 1350 may be configured to: and if the middle position of a section of continuous first signal or a section of continuous second signal in the sorted first signal and second signal corresponds to a first test sampling point, taking the first test sampling point corresponding to the middle position as the sampling quasi-position of the chip to be tested.
In an exemplary embodiment, the sampling level determination module 1350 may be configured to: if the middle position of a section of continuous first signal or a section of continuous second signal in the sequenced first signal and second signal corresponds to two first test sampling points, randomly selecting any one of the two first test sampling points as the sampling quasi-position of the chip to be tested; or taking the intermediate value of the two first test sampling points as the sampling quasi-position of the chip to be tested.
In an exemplary embodiment, the sampling level determining module 1350 may include: an adjacent signal switching position determination unit that may be configured to determine two adjacent signal switching positions at which the first signal and the second signal are switched; the sampling level determining unit may be configured to use a middle value of the two adjacent signal switching positions as the sampling level of the chip to be tested.
In an exemplary embodiment, the adjacent signal switching position determining unit may be configured to: taking any one of two first test sampling points corresponding to the first signal and the second signal to be switched in the sequenced first signal and second signal as a signal switching position; or taking the middle value of two first test sampling points corresponding to the first signal and the second signal to be switched in the sequenced first signal and second signal as a signal switching position; and taking the signal switching positions corresponding to the adjacent first signal and second signal to be switched as two adjacent signal switching positions.
In an exemplary embodiment, the adjacent signal switching position determining unit may include: the adjacent signal switching interval determining subunit may be configured to determine two adjacent signal switching intervals in each data signal according to two first test sampling points respectively corresponding to two adjacent first signals and second signals to be switched in the sorted first signals and second signals; the second test sampling point setting subunit may be configured to set a second test sampling point in two adjacent signal switching intervals of the data signal of each channel according to a second interval; and the adjacent signal switching position determining subunit can be configured to determine two adjacent signal switching positions according to the sampling signal of the second test sampling point.
In an exemplary embodiment, the adjacent signal switching position determining subunit may be configured to: comparing the sampling signal of each second test sampling point with the quasi-level voltage respectively to obtain a second comparison result; if the second comparison result indicates that the sampling signal of the second test sampling point is greater than the quasi-level voltage, marking the corresponding second test sampling point as a first signal; if the second comparison result indicates that the sampling signal of the second test sampling point is smaller than the quasi-level voltage, marking the corresponding second test sampling point as a second signal; according to the sequence of the sampling positions corresponding to the second testing sampling points, corresponding first signals or second signals are sequenced again; and determining a signal switching position for switching two adjacent first signals and second signals in the reordered first signals and second signals.
In an exemplary embodiment, the first interval is less than one-quarter of a period of the data signal, and the second interval is less than one-half of the first interval.
In an exemplary embodiment, the chip under test may be a DRAM chip.
Since each functional module of the chip sampling level determining apparatus 1000 according to the exemplary embodiment of the present disclosure corresponds to the steps of the exemplary embodiment of the chip sampling level determining method, it is not described herein again.
Other contents in the embodiments of the present disclosure may refer to the contents in the embodiments of fig. 1 to 12, and are not described herein again.
In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided. Referring now to FIG. 14, shown is a block diagram of a computer system suitable for use in implementing the electronic device of an embodiment of the present disclosure. The computer system of the electronic device shown in fig. 14 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
As shown in fig. 14, the computer system includes a Central Processing Unit (CPU)1401, which can perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)1402 or a program loaded from a storage portion 1408 into a Random Access Memory (RAM) 1403. In the RAM 1403, various programs and data necessary for system operation are also stored. The CPU 1401, ROM 1402, and RAM 1403 are connected to each other via a bus 1404. An input/output (I/O) interface 1405 is also connected to bus 1404.
The following components are connected to the I/O interface 1405: an input portion 1406 including a keyboard, a mouse, and the like; an output portion 1407 including a display such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker and the like; a storage portion 1408 including a hard disk and the like; and a communication portion 1409 including a network interface card such as a LAN card, a modem, or the like. The communication section 1409 performs communication processing via a network such as the internet. The driver 1410 is also connected to the I/O interface 1405 as necessary. A removable medium 1411 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 1410 as necessary, so that a computer program read out therefrom is installed into the storage section 1408 as necessary.
In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication portion 1409 and/or installed from the removable medium 1411. The above-described functions defined in the system of the present application are executed when the computer program is executed by a Central Processing Unit (CPU) 1401.
It should be noted that the computer readable media shown in the present disclosure may be computer readable signal media or computer readable storage media or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer-readable signal medium may include a propagated data signal with computer-readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The modules or units or sub-units described in the embodiments of the present disclosure may be implemented by software, or may be implemented by hardware, and the described modules or units or sub-units may also be disposed in a processor. The names of these modules or units or sub-units do not in some cases form a limitation to the modules or units or sub-units themselves.
As another aspect, the present application also provides a computer-readable medium, which may be contained in the electronic device described in the above embodiments; or may exist separately without being assembled into the electronic device. The computer readable medium carries one or more programs which, when executed by an electronic device, cause the electronic device to implement the method for determining a chip sampling level as described in the above embodiments.
For example, the electronic device may implement the following as shown in fig. 4: step S1, acquiring a data signal on a specified channel of a chip to be tested; step S2, setting a plurality of first test sampling points for the data signal according to a first interval; step S3, determining a first signal or a second signal corresponding to each first test sampling point according to the level voltage; step S4, sorting the corresponding first signals or second signals according to the sequence of the sampling positions corresponding to the first testing sampling points; step S5, determining a sampling level of the chip to be tested according to the sorted first signal and second signal.
It should be noted that although in the above detailed description several modules or units of a device or apparatus for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (15)
1. A method for determining a chip sampling level, comprising:
acquiring a data signal on a specified channel of a chip to be tested;
setting a plurality of first test sampling points for the data signal according to a first interval;
determining a first signal or a second signal corresponding to each first test sampling point according to the quasi-level voltage;
sequencing the corresponding first signals or second signals according to the sequence of the sampling positions corresponding to the first test sampling points;
and determining the sampling level of the chip to be tested according to the sorted first signal and second signal.
2. The method of claim 1, wherein obtaining data signals on a designated channel of a chip under test comprises:
sending a write control signal to the chip to be tested so as to write analog data into the chip to be tested;
sending a reading control signal to the chip to be tested so as to read the analog data from the chip to be tested;
And receiving a data signal which is output by the appointed channel of the chip to be tested and corresponds to the analog data.
3. The method of claim 1, wherein the first interval is less than one quarter of a period of the first data signal.
4. The method of claim 1, wherein determining the first signal or the second signal corresponding to each of the first test sample points according to the level voltage comprises:
comparing the sampling signal of each first test sampling point with the quasi-level voltage respectively to obtain a first comparison result;
if the first comparison result indicates that the sampling signal of the first test sampling point is greater than the quasi-level voltage, marking the corresponding first test sampling point as a first signal;
and if the first comparison result shows that the sampling signal of the first test sampling point is smaller than the quasi-level voltage, marking the corresponding first test sampling point as a second signal.
5. The method of claim 1, wherein determining the sampling level of the chip to be tested according to the sorted first and second signals comprises:
and if the middle position of a section of continuous first signal or a section of continuous second signal in the sorted first signal and second signal corresponds to a first test sampling point, taking the first test sampling point corresponding to the middle position as the sampling quasi-position of the chip to be tested.
6. The method of claim 1, wherein determining the sampling level of the chip to be tested according to the sorted first and second signals comprises:
if the middle position of a section of continuous first signal or a section of continuous second signal in the sequenced first signal and second signal corresponds to two first test sampling points, randomly selecting any one of the two first test sampling points as the sampling quasi-position of the chip to be tested; or
And taking the intermediate value of the two first test sampling points as the sampling quasi-position of the chip to be tested.
7. The method of claim 1, wherein determining the sampling level of the chip to be tested according to the sorted first and second signals comprises:
determining two adjacent signal switching positions at which the first signal and the second signal are switched;
and taking the intermediate value of the two adjacent signal switching positions as the sampling quasi-position of the chip to be tested.
8. The method of claim 7, wherein determining two adjacent signal switching positions at which the first signal and the second signal are switched comprises:
Taking any one of two first test sampling points corresponding to the first signal and the second signal to be switched in the sequenced first signal and second signal as a signal switching position; or
Taking the middle value of two first test sampling points corresponding to the first signal and the second signal to be switched in the sequenced first signal and second signal as a signal switching position;
and taking the signal switching positions corresponding to the adjacent first signal and second signal to be switched as two adjacent signal switching positions.
9. The method of claim 7, wherein determining two adjacent signal switching positions at which the first signal and the second signal are switched comprises:
determining two adjacent signal switching intervals in each data signal according to two first test sampling points respectively corresponding to two adjacent first signals and second signals for switching in the sorted first signals and second signals;
setting a second test sampling point in two adjacent signal switching intervals of the data signals of each channel according to a second interval;
and determining the switching positions of two adjacent signals according to the sampling signals of the second test sampling point.
10. The method of claim 9, wherein determining two adjacent signal switching positions according to the sampling signal of the second test sample point comprises:
comparing the sampling signal of each second test sampling point with the quasi-level voltage respectively to obtain a second comparison result;
if the second comparison result indicates that the sampling signal of the second test sampling point is greater than the quasi-level voltage, marking the corresponding second test sampling point as a first signal;
if the second comparison result indicates that the sampling signal of the second test sampling point is smaller than the quasi-level voltage, marking the corresponding second test sampling point as a second signal;
according to the sequence of the sampling positions corresponding to the second testing sampling points, corresponding first signals or second signals are sequenced again;
and determining a signal switching position for switching two adjacent first signals and second signals in the reordered first signals and second signals.
11. The method of claim 9, wherein the first interval is less than one quarter of a period of the data signal, and the second interval is less than one half of the first interval.
12. The method as claimed in claim 1, wherein the chip under test is a DRAM chip.
13. A chip sampling level determining apparatus, comprising:
the data signal acquisition module is configured to acquire a data signal on a specified channel of the chip to be tested;
the first sampling setting module is configured to set a plurality of first test sampling points for the data signal according to a first interval;
the digital signal conversion module is configured to determine a first signal or a second signal corresponding to each first test sampling point according to the level voltage;
the digital signal sequencing module is configured to sequence the corresponding first signal or second signal according to the sequence of the sampling positions corresponding to the first test sampling points;
and the sampling level determining module is configured to determine the sampling level of the chip to be tested according to the sorted first signal and second signal.
14. A computer-readable medium, on which a computer program is stored, which, when being executed by a processor, implements the method for determining the sampling level of a chip according to any one of claims 1 to 12.
15. An electronic device, comprising:
One or more processors;
storage means for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to implement the chip sampling level determination method as claimed in any one of claims 1 to 12.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116501235A (en) * | 2023-06-29 | 2023-07-28 | 珠海妙存科技有限公司 | Sampling point determining method, system, device and storage medium |
| CN117250484A (en) * | 2023-11-20 | 2023-12-19 | 北京小米移动软件有限公司 | Chip testing method and device, test chip and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104240748A (en) * | 2013-06-19 | 2014-12-24 | 瑞昱半导体股份有限公司 | Oversampling method for data signal and oversampling device for data signal |
| CN104333443A (en) * | 2014-10-27 | 2015-02-04 | 大唐移动通信设备有限公司 | Method and device for acquiring signal channel |
| US20170109040A1 (en) * | 2015-10-20 | 2017-04-20 | Sandisk Technologies Inc. | Systems and Methods for Sampling Data at a Non-Volatile Memory System |
| CN107359934A (en) * | 2017-08-30 | 2017-11-17 | 重庆理工大学 | Single channel dual signal live transmission method and system |
| CN108282163A (en) * | 2018-02-12 | 2018-07-13 | 上海贝岭股份有限公司 | Sampling instant mismatch calibration device, method and time-interleaved analog-digital converter |
-
2019
- 2019-04-29 CN CN201910353218.8A patent/CN111863114B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104240748A (en) * | 2013-06-19 | 2014-12-24 | 瑞昱半导体股份有限公司 | Oversampling method for data signal and oversampling device for data signal |
| US20140375365A1 (en) * | 2013-06-19 | 2014-12-25 | Realtek Semiconductor Corp. | Oversampling method for data signal and oversampling apparatus thereof |
| CN104333443A (en) * | 2014-10-27 | 2015-02-04 | 大唐移动通信设备有限公司 | Method and device for acquiring signal channel |
| US20170109040A1 (en) * | 2015-10-20 | 2017-04-20 | Sandisk Technologies Inc. | Systems and Methods for Sampling Data at a Non-Volatile Memory System |
| CN107359934A (en) * | 2017-08-30 | 2017-11-17 | 重庆理工大学 | Single channel dual signal live transmission method and system |
| CN108282163A (en) * | 2018-02-12 | 2018-07-13 | 上海贝岭股份有限公司 | Sampling instant mismatch calibration device, method and time-interleaved analog-digital converter |
Non-Patent Citations (1)
| Title |
|---|
| 蔡花梅等: "随机等效采样系统设计及其关键技术点分析", 《电子质量》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116501235A (en) * | 2023-06-29 | 2023-07-28 | 珠海妙存科技有限公司 | Sampling point determining method, system, device and storage medium |
| CN116501235B (en) * | 2023-06-29 | 2024-02-23 | 珠海妙存科技有限公司 | Sampling point determining method, system, device and storage medium |
| CN117250484A (en) * | 2023-11-20 | 2023-12-19 | 北京小米移动软件有限公司 | Chip testing method and device, test chip and storage medium |
| CN117250484B (en) * | 2023-11-20 | 2024-03-12 | 北京小米移动软件有限公司 | Chip testing method and device, test chip and storage medium |
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|---|---|
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