CN111857074A

CN111857074A - High-speed high-precision path comparison control method and path comparison controller

Info

Publication number: CN111857074A
Application number: CN202010708516.7A
Authority: CN
Inventors: 张靖雯; 邓伦; 梁朝秋
Original assignee: Guangdong Anda Intelligent Equipment Co Ltd
Current assignee: Guangdong Anda Intelligent Equipment Co Ltd
Priority date: 2020-07-22
Filing date: 2020-07-22
Publication date: 2020-10-30

Abstract

The invention relates to the technical field of industrial control, in particular to a high-speed high-precision path comparison control method and a path comparison controller. In order to solve the problems that the actual coordinate point of industrial equipment in the prior art cannot be checked in real time and the transmission efficiency is low due to too long feedback delay, the invention provides a high-speed high-precision path comparison control method and a path comparison controller, wherein the method comprises the following steps: receiving an industrial computer instruction, and acquiring a target point position coordinate signal of industrial equipment from the industrial computer instruction; receiving a pulse signal of a feedback device, and acquiring an actual position signal of the industrial equipment from the pulse signal; converting the actual position signal into an actual point position coordinate signal; comparing the target point location coordinate signal with the actual point location coordinate signal; judging whether the comparison result meets the threshold requirement or not; if the error is less than or equal to the threshold value, outputting a comparison result; if the error is greater than the threshold, execution is immediately terminated.

Description

High-speed high-precision path comparison control method and path comparison controller

Technical Field

The invention relates to the technical field of industrial control, in particular to a high-speed high-precision path comparison control method and a path comparison controller.

Background

With the rapid development of the industrial field, automation equipment is continuously updated, and important indexes of actual production application to industrial equipment are as follows: the requirements of safety, speed and precision are more and more strict, and the same is true for the automation equipment with the path comparison function.

The path comparison is the application of bottom hardware in the automation industry, related processing steps and algorithms are completed by the bottom hardware, and errors are mostly determined by machining precision, the bottom algorithm and communication response speed among various hardware. Therefore, a mature path comparison control system has the functions of improving the response speed and precision of equipment and the like, and has wide application prospect.

However, the existing path comparison controllers are generally integrated in a PCI (Peripheral component interconnect) type motion control card, and a pulse signal source and real-time motion are semi-closed loop control, so that the path comparison control cannot be used independently, and the delay of path comparison signal transmission is increased in the EtherCAT bus type motion control card; the encoder signal is output to the driver and then read from the motion control card to the driver end, which causes the error and delay increase of signal transmission, thus bringing great influence to debugging and production in practical application.

The prior design is shown in the specification and attached to fig. 1, and the implementation steps are as follows:

(step 1) as shown in figure 1 (I), an industrial computer drives an industrial camera to obtain a target image, a target coordinate is automatically calculated according to related process requirements, and then the target point position is dynamically or statically transmitted to a motion control card/path plan through figure (PCI).

(step 2) as shown in figure 1, the industrial computer drives the motion control card, and the motor is controlled to move according to a specified path and speed by sending and receiving commands to the driver.

(step 3) as shown in fig. 1 (c), the encoder signal is connected to the driver, the driver performs internal operation to cause the signal to be output to the motion control card/path planning after a certain time delay, the motion control card/path planning compares the signal with a target point, and finally the result is transmitted to an executable device (such as a dispensing valve and a laser) in a high-low level mode through a designated output port.

(step 4) as shown in fig. 1, the industrial computer obtains the comparison result of the motion control card/path plan, and determines whether the motor operates according to the plan instruction according to the result.

The existing common design is not suitable for most occasions with strict requirements on speed and precision, but has obvious limitations when meeting the requirements on high quality, high speed and high precision:

1. When the design is applied to high-speed equipment, the result of the coordinate point position comparison is too late, so that corresponding hardware cannot respond in time during high-speed operation, and the production efficiency is low.

2. The product replacement cost is high, and when the motion control function has problems, the path planning controller also needs to be replaced; similarly, when the path planning controller fails, the motion controller needs to be replaced, which is worse.

The above factors greatly limit the improvement of the speed and the precision of the equipment, along with the increasing of the running speed of the automation equipment, the control precision is higher and higher, the technical limitation enables the development of the equipment to be limited to a great extent, and therefore, the development of a path comparison planning controller with low replacement cost, good universality and high speed and high precision is very necessary.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a high-speed and high-precision path comparison control method and a path comparison controller, aiming at the above-mentioned defects of the prior art for performing semi-closed loop motion control.

According to an aspect of the present invention, there is provided a high-speed high-precision path comparison control method, including:

Step S10, receiving an industrial computer instruction, and acquiring an industrial equipment target point position coordinate signal from the industrial computer instruction;

step S20, receiving a feedback device pulse signal;

step S21, filtering the pulse signal;

step S22, converting the pulse signal into an actual point position coordinate signal;

step S30, comparing the coordinate signal of the target point with the coordinate signal of the actual point;

step S31, judging whether the error of the comparison result is less than or equal to the threshold value;

and step S32, if the error is less than or equal to the threshold value, outputting the comparison result to a designated output port.

As a further improvement of the present invention, the pulse signal includes information about the actual position of the industrial equipment, and if the error is larger than the threshold, step S33 is executed to immediately terminate the execution.

According to another aspect of the present invention, there is provided a high-speed high-precision path comparison controller, including: the EtherCAT communication module is used for communicating with other equipment on the EtherCAT bus communication, acquiring an industrial computer instruction and acquiring a target point position coordinate signal of the industrial equipment to reach a preset position from the industrial computer instruction; the pulse signal acquisition module is used for receiving a pulse signal of the motor encoder; the pulse signal filtering module is used for filtering the pulse signal; the path comparison module is used for comparing the target point coordinate signal with the actual point coordinate signal and judging whether the error of the comparison result is less than or equal to a threshold value; the storage module is used for storing the target point bit coordinate signal and the threshold parameter; the ultra-high speed output module is used for sending the result of the operation comparison to an output port; the path comparison module is respectively connected with the pulse signal filtering module, the storage module and the ultra-high speed output module, the storage module is connected with the EtherCAT communication module, and the pulse signal filtering module is connected with the pulse signal acquisition module.

As a further improvement of the invention, the memory module is a high-speed hardware FIFO memory module.

As a further improvement of the invention, the storage module, the path comparison module, the ultra-high speed output module, the pulse signal acquisition module and the pulse signal filtering module are arranged in the FPGA system.

As a further improvement of the invention, the system also comprises a high-speed output module which is used for outputting a coordinate comparison result, the high-speed output module is arranged outside the FPGA system, and the high-speed output module is connected with the path comparison module.

As a further improvement of the invention, the pulse signal filtering module is an infinite impulse response filtering module.

As a further improvement of the invention, the EtherCAT communication module is a two-way EtherCAT ad hoc network communication module.

As a further improvement of the invention, the multi-channel independent high-speed output coordinate comparison result control module is also included.

As a further improvement of the invention, the FPGA-based power supply system further comprises a filtering module, and the filtering module is arranged outside the FPGA system.

The high-speed high-precision path comparison control system has the following beneficial effects: the control system is independently designed and optimizes the existing path comparison function, realizes the real-time output of the full closed-loop signal, reduces the calculation error range and effectively improves the response speed; the actual position signal of the industrial equipment is acquired through the pulse signal acquisition module, the target working position signal of the industrial equipment is acquired through the communication module, the actual position signal and the target working position signal are directly compared, the data transmission comparison time is greatly saved, high-speed operation is performed in the FPGA, the speed and the effect of path comparison are obviously improved, the problems of delay and inaccuracy of output control signals of the path comparison controller are solved, and the high-speed and high-precision control effect is achieved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention.

FIG. 1 is a schematic diagram of a path comparison control system of prior art design;

FIG. 2 is a schematic diagram of the improved path comparison control system of the present invention;

FIG. 3 is a flow chart of a path comparison control method according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a path comparison control system according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a path comparison control system according to another embodiment of the present invention;

FIG. 6 is a schematic diagram of a filtering simulation of the pulse signal filtering module according to the present invention;

FIG. 7 is a diagram of the filtering process of the pulse signal filtering module of the present invention;

FIG. 8 is a graph of comparative trigger results for X, Y axis interpolation motion;

FIG. 9 is a schematic diagram of the comparative triggering results of the interpolation motion of the X, Y axes;

in the figure: an industrial computer 10; a motion control card 11; a driver 12; a motor encoder 13; an industrial camera 14; an FPGA system 20; a path comparison controller 30; a storage module 21; a path comparison module 22; an ultra-high speed output module 23; a pulse signal acquisition module 24; a pulse signal filtering module 25; an EtherCAT communication module 31; a filtering module 32; a high-speed output module 33; a first data transmission unit 34; a first network interface 341; a first network transformer 342; a first transceiver 343; a second data transmission unit 35; a second network interface 351; a second network transformer 352; a second transceiver 353.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Referring to fig. 3-4, fig. 3 is a flowchart illustrating a path comparison control method according to an embodiment of the invention.

In the embodiment of the present invention, optionally, the two control links of step S10 and step S20 run in parallel, which has the beneficial effect of improving efficiency.

And step S10, receiving the instruction of the upper computer, and acquiring a target point coordinate signal of the industrial equipment to reach a preset position.

In the embodiment of the invention, the upper computer is an industrial computer 10, and the industrial computer 10 sends out a target point position coordinate signal to enable the industrial equipment to move to a specified position.

Step S20, receiving the pulse signal of the feedback device and acquiring the actual position signal of the industrial equipment;

in the embodiment of the invention, the feedback device is a motor encoder 13, the motor encoder 13 is installed on the motor to collect the running state of the motor, and the motor encoder 13 can output information as a pulse signal.

Step S21, filtering the impulse signal of the feedback device;

in the embodiment of the present invention, the FPGA system 20 is provided with a pulse signal filtering module 25, which is used for performing filtering processing on the pulse signal from the motor encoder 13 to filter out an interference signal.

Step S22, converting the pulse signal of the actual position into an actual point position coordinate signal;

Step S30, comparing the target point position coordinate signal with the actual point position coordinate signal;

the path comparison module 22 compares the target point location coordinate signal and the actual point location coordinate signal.

Step S31, determining whether the error of the comparison result is less than or equal to a threshold:

if the error is less than or equal to the threshold, step S32 outputs the comparison result.

If the error is greater than the threshold, step S33 is executed to terminate execution immediately.

Referring to fig. 2, a schematic diagram of the improved path comparison control system of the present invention is shown.

Comparing with fig. 1, compared with the prior art, the path planning in the prior art is independent and optimized, and the filtering unit is added to filter the signal of the encoder. The dotted line box N in the figure uses the same FPGA hardware module and parallel processing principles.

The industrial computer drives the industrial camera to quickly calculate the coordinates of all target points according to the returned images and a related algorithm.

The industrial computer transmits the corresponding control instruction and the calculated target point coordinates to the FPGA through a in the figure, and the FPGA establishes a high-speed hardware FIFO inside to store the target point coordinates.

The FPGA builds a filtering hardware unit that detects the encoder signal and performs filtering and arithmetic on it, as shown in b in the figure.

The processing results of the encoders are passed inside the FPGA to a path planning unit which compares the actual position coordinates with the coordinates of the target point bits stored in the module on a relevant error handling algorithm.

In fig. 2, the M and N dashed boxes adopt the parallel processing principle, the N dashed boxes adopt the FPGA hardware processing and the parallel processing capability to achieve the effects of high speed and high precision, the existing path comparison function is optimized, the replacement steps are simplified, the replacement cost is saved, the test error range is greatly reduced (at least 2-3 times or more can be reduced), the actual comparison speed is effectively increased (more than 2000mm/s can be increased), the speed and precision of the device are improved, and the universality is better.

Referring to fig. 4, the path comparison controller 30 includes an FPGA system 20, an EtherCAT communication module 31, and a high-speed output module 33; a first data transmission unit 34; a second data transmission unit 35.

The EtherCAT communication module 31 is connected to the FPGA system 20, the first data transmission unit 34, and the second data transmission unit 35, respectively.

The first data transmission unit 34 includes a first network interface 341, a first network transformer 342, and a first transceiver 343, the first transceiver 343 is connected to the EtherCAT communication module 31, and the first network transformer 342 is connected to the first network interface 341 and the first transceiver 343, respectively;

The second data transmission unit 35 includes a second network interface 351, a second network transformer 352, and a second transceiver 353, the second transceiver 353 is connected to the EtherCAT communication module 31, and the second network transformer 352 is connected to the second network interface 351 and the second transceiver 353, respectively.

The first network interface 341 and the second network interface 351 are RJ45 sockets for connecting network cables; the first network transformer 342 and the second network transformer 352 respectively couple and filter the differential signals sent by the first transceiver 343 and the second transceiver 353 by using a differential mode coupling coil to increase the signals, so that the chip end is isolated from the outside, the anti-interference capability is greatly enhanced, and the chip is greatly protected; the first transceiver 343 and the second transceiver 353 are used for transmitting and receiving data frames of ethernet.

The EtherCAT communication module 31 is a chip based on a field bus of an industrial ethernet, and has the characteristics of high speed and high data efficiency, and the EtherCAT communication module in this embodiment is a two-way EtherCAT ad hoc network communication module.

And a high-speed output module 33, configured to output the comparison result, and may respond in microseconds, where a trigger time difference between each channel and each module is in microseconds.

The FPGA system 20 includes a storage module 21, a path comparison module 22, an ultra-high speed output module 23, a pulse signal acquisition module 24, and a pulse signal filtering module 25.

The storage module 21, the path comparison module 22 and the ultra-high speed output module 23 belong to a path planning unit, and the pulse signal acquisition module 24 and the pulse signal filtering module 25 belong to a filtering unit.

The path comparison module 22 is respectively connected with the storage module 21, the ultra-high speed output module 23 and the pulse signal filtering module 25, and the pulse signal acquisition module 24 is connected with the pulse signal filtering module 25.

And the ultra-high-speed output module 23 is used for outputting the comparison result, and can respond in a nanosecond level, and the triggering time difference between each channel and each module is in a nanosecond unit.

The FPGA is a chip, can be programmed by hardware, and is internally provided with modules with different functions. The FPGA is installed on a printed circuit board through a surface mount technology, the printed circuit board is a support body of an electronic component and is a carrier for electrical connection of the electronic component, the peripheral of the FPGA system 20, such as an EtherCAT communication module 31, is also installed on the printed circuit board, a first data transmission unit 34 and a second data transmission unit 35 are used for achieving EtherCAT network communication with other equipment, and a high-speed output module 33 is connected with a path comparison module 22.

The design is based on an FPGA (Field Programmable Gate Array), data can be processed in parallel, programs inside the FPGA run in parallel, the capacity of processing more complex functions is achieved, different logics of the FPGA can be executed in parallel, different tasks can be processed simultaneously, the working efficiency of the FPGA is higher, and the roundabout processing mode of signals of the path comparison control system in the existing design is changed.

As the core of the control system, the master control chip selects a Cyclone chip EP1C3T1448 of Altera corporation, and has the advantages of high capacity, low price and good characteristics, and the system software design is completed through Quratus II 13.0.

The industrial computer 10 drives the industrial camera 14 to take a picture, and the result of taking a picture is retrieved to the industrial computer 10 for processing, so as to calculate the instantaneous position of the object to be taken, and quickly calculate the position coordinates of all the target points according to the related algorithm.

The industrial computer 10 is connected to the EtherCAT communication module 31 through the first data transmission unit 34 or the second data transmission unit 35 for data interaction, and in this embodiment, the FPGA system 20 receives the target point bit coordinate signal through the EtherCAT communication module 31.

In a specific application embodiment, the EtherCAT communication module 31 is an EtherCAT communication module of a two-way ad hoc network.

The industrial computer 10 communicates with the path comparison controller 30 via an EtherCAT bus, which is an open architecture ethernet-based field bus system. The EtherCAT has the prominent characteristics of real-time performance and synchronization, the EtherCAT realizes synchronization by adopting a distributed clock concept, and through a calibration mechanism of a master clock and a slave clock in a system, the jitter of the clocks is far less than 1 mu s, and the synchronization is also in the mu s level. And because the synchronism is realized by hardware, the reliability of the EtherCAT is ensured to a great extent. The characteristic has obvious advantages in the high-end application field, such as a numerical control system, a motion control system and the like, so that the method has the beneficial effect of effectively ensuring the real-time property and the synchronism of communication.

The path planning unit stores the target point bit coordinate signal sent by the industrial computer 10 into the storage module 21 after receiving the target point bit coordinate signal, the storage module 21 in this embodiment is preferably a high-speed hardware FIFO storage module, the number of position points in the path planning is more than 1000, and dynamic storage of the position points is supported, so that position storage of infinite points can be realized by this method, and a FIFO first-in first-out mechanism is utilized.

The FIFO is an abbreviation of english First In First Out, and is a First In First Out data buffer for buffering data, i.e. the data written First, is read First. The parameters of the FIFO include data depth and data width, the data width refers to the width of stored data, and the depth refers to how many data the memory can store. The FIFO control logic is programmed by using a state machine and is divided into an idle state, a ready-to-read state, a read complete state, a ready-to-write state, a write state and a write complete state. Two read-write address registers are arranged in the logic, and the empty state and the full state of the memory are set through address judgment. If the memory is empty, it cannot be read and the memory is full and cannot be written.

In this embodiment, the industrial computer 10 is connected to a motion control card 11, the motion control card 11 is connected to a driver 12, the driver 12 is connected to a motor encoder 13, and the motor encoder 13 is connected to a pulse signal acquisition module 24.

The motion control card 11 is used for receiving a target point coordinate signal sent by the industrial computer 10, and the motion control card 11 controls the driver 12 by sending a pulse or an analog quantity.

The driver 12 controls the servo motor and provides corresponding instructions to operate the servo motor, and the motor encoder 13 feeds the pulse signals back to the driver 12 and the pulse signal acquisition module 24.

The pulse signal acquisition module 24 is used for receiving the fed back pulse signal to acquire an actual point location coordinate signal of the industrial equipment.

The encoder is one of sensors, and the encoder is installed on the motor, mainly used to detect the speed, position, angle, distance or count of the mechanical movement, and can output the information as a pulse signal.

The pulse signal filtering module 25 is arranged in the FPGA system 20:

further, the pulse signal filtering module 25 may filter the pulse signal in order to make the data accuracy higher.

Further, in this embodiment, the impulse signal filtering module 25 is an infinite impulse response filtering module.

An infinite impulse response filter, also called a recursive filter, is structurally provided with a feedback loop. The number of multipliers required by the infinite impulse response filter to output each signal is greatly reduced. From the hardware perspective, the infinite impulse response filter is fast in speed and high in efficiency, and the sampling rate of the real-time infinite impulse response filter is far higher than that of the finite impulse response. The impulse response length of the infinite impulse response filter is not limited by the number of taps, so the filter performance of the infinite impulse response filter is much better than that of the finite impulse response filter for finite continuous non-zero input values, and the infinite impulse response filter outputs infinite continuous non-zero samples under the same number of multipliers. The infinite impulse response filtering module designed on the FPGA system has the advantages of high speed, more accurate data and higher efficiency.

Referring to fig. 6-7, fig. 6 is a simplified illustration of fig. 7 for a more visual and brief explanation, Clk represents a system clock, Rst _ n represents a system Reset signal, Ena represents an encoder enable signal, Reset represents an encoder Reset signal, X _ a represents a signal of a grating scale a phase signal processed by hardware circuitry, X _ B represents a signal of a grating scale B phase signal processed by hardware circuitry, XCoordinate (X coordinate) represents a reading of the encoder after filtering, a place circled out from a in fig. 7 represents an interference signal introduced on X _ a, and in a low level region, two narrow pulses are generated, which have a higher frequency than a normal square wave signal and can be filtered out by the bandpass filtering characteristic of an infinite impulse response filter, and the XCoordinate (X coordinate) is referred to the circled data in fig. 7, and experiments prove that the XCoordinate (X coordinate) is consistent after the two interference pulses, the filtering design is efficient.

The EtherCAT communication module 31 is connected with the storage module 21, the received target point bit coordinate and the threshold parameter are stored in the storage module 21, the path comparison module 22 is connected with the storage module 21, the path comparison module 22 reads the target point bit coordinate and the threshold parameter from the storage module 21, the path comparison module 22 is connected with the pulse signal acquisition module 24 to receive the actual point bit coordinate, the path comparison module 22 compares the actual point bit coordinate with the target point bit coordinate, when the actual point bit coordinate signal and the target point bit coordinate signal meet an error requirement, the error corresponds to a threshold, the threshold is specifically set by a user, the minimum value is 1 pulse, and excessive limitation is not performed here. When the comparison result is less than or equal to the threshold value, the comparison result is output through the ultra-high speed output module 23, the output result is a low level signal, and other communication equipment interfaces receive the level signal to drive corresponding equipment and provide the result for the industrial computer to inquire; when the comparison result is greater than the threshold value, the execution is immediately terminated.

Referring to fig. 5, in an embodiment of the present invention, the present invention further includes a filtering module 32, and the filtering module 32 is disposed outside the FPGA system 20 on the printed circuit board.

In the actual industrial field environment, on one hand, various electrical interferences, surges, static electricity, electromagnetic radiation, conduction and the like exist, on the other hand, the system load, the motor and other factors influence, and the output signals of the encoder or the grating ruler contain more jittering error code pulses, which can cause miscounting and cause errors in measuring the speed and the position of the rotating mechanism.

In order to eliminate static electricity which has a large influence, an ESD (Electro-static discharge) device is arranged on the printed circuit board, and when the static electricity reaches a signal input end of the PCB, high-voltage static electricity is released, so that the safety of the device is protected.

In order to eliminate the influence of the surge, a TVS (TVS is an abbreviation of Transient voltage suppressor, and the chinese means Transient voltage suppressor) device is arranged on the printed circuit board, and when the surge reaches the power input end of the PCB, the surge is released, so as to protect the safety of the device.

The unit or the module in the embodiment is only used for explanation, does not represent to limit the number of the units, the module and the unit can be expanded, and the controller is also provided with a control module for controlling the comparison result of the independent high-speed output coordinates of multiple paths, can realize the characteristics of simultaneously processing the actual position comparison output of 2 to 4 axes and the high-speed parallel operation of the FPGA, and supports 20 paths of input signals of 1 microsecond and 20 paths of output signals of 670 nanoseconds.

In summary, the working principle and the operation steps of the present invention are summarized as follows:

(1) in the environment of an EtherCAT bus, sending a zero-returning finishing instruction to the path comparison controller 30 through upper computer software of the industrial computer 10, and clearing the encoder reading of the internal hardware module by the path comparison controller 30 according to the instruction;

(2) in the environment of the EtherCAT bus, an encoder enabling command is sent to the path comparison controller 30 through the industrial computer 10, so that the path comparison controller 30 enables the encoder;

(3) sending a comparison enabling command to the path comparison controller 30 through the industrial computer 10, and starting a path comparison function of the path comparison controller 30; parameters required by the comparison functions, such as trigger hold time, trigger allowable error value, etc., are transmitted to the path comparison controller 30; the processed coordinate values are transmitted to a path comparison controller, and the movement of the working shaft is controlled according to the planned path at different speeds, so that the comparison result of each allowable error at different speeds can be counted; and according to the statistical result, the external equipment can be directly triggered.

And (3) correctly accessing the path comparison controller 30 to the automatic motion equipment, switching on a power supply after checking that no error exists, and counting the comparison speed and the error of the path comparison controller 30 by using upper computer test software.

X, Y comparison of axis interpolation motion triggers:

referring to fig. 8-9, fig. 9 is a simplified illustration of fig. 8 for a more visual and brief explanation, and X _ A, X _ B, X _ Z, Y _ A, Y _ B, Y _ Z are encoder signals of X, Y axes respectively after being processed by hardware of the control system; x _ R, Y _ R is the coordinate of the target point position of the X axis and the Y axis respectively; CountCntX and CountCntY are real-time coordinate values of the control system after filtering respectively; PerMitError is set to 9 in the set allowable error map; TrigHoldtime is trigger hold time, and is set to 2 milliseconds in the figure; the TrigIO is external high-speed IO, and a high-speed glue dispensing valve is controlled in the experiment; StarTrig is a successful comparison and starts the trigger signal. In fig. 9, if the actual coordinate and the target point coordinate are both 100 when detected at the cursor 1, i.e., at the rising edge of the clock cycle T8, it indicates that the actual position passes through the target coordinate, and then the start trigger signal startig is generated, and in fig. 9, if the start trigger signal startig is detected at the cursor 2, i.e., at the rising edge of the clock cycle T9, then the TrigIO is enabled to drive the peripheral device or the external device.

The comparison output function outputs one or more switching values, and the motion process is not influenced. If in the dispensing process of the dispenser, the comparison output function enables the system to run to the set position, and then quick dispensing is started.

The implementation has the following beneficial effects: the actual point location coordinate signal of the industrial equipment is obtained through the pulse signal acquisition module, the target point location coordinate signal of the industrial equipment is obtained through the EtherCAT communication module, and the actual point location coordinate and the target point location coordinate are directly compared.

Compared with the prior art, the path comparison controller is independent in design, optimizes the existing path comparison function, simplifies the replacement steps, saves the replacement cost, and reduces the actual test error range by 2-3 times; the actual comparison speed is improved to more than 2000mm/s, which is greatly higher than the comparison speed in the prior art.

The above embodiments are merely illustrative of the technical ideas and features of the present invention, and are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the scope of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the claims of the present invention.

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

Claims

1. A high-speed high-precision path comparison control method is characterized in that the method is applied to the same FPGA, and the method comprises the following steps:

s10, receiving an instruction of an upper computer, and acquiring a target point position coordinate signal of the industrial equipment from the instruction;

step S20, receiving a pulse signal of a feedback device;

step S21, filtering the pulse signal;

and step S32, if the error is less than or equal to the threshold, outputting a low level or high level electric signal through an output port.

2. The high-speed high-precision path comparison control method according to claim 1, further comprising a step S33 after the step S31:

and if the error is larger than the threshold value, immediately terminating the execution.

3. A high-speed high-precision path comparison controller, the path comparison controller comprising: the EtherCAT communication module (31) is used for communicating with other equipment on the EtherCAT bus communication, acquiring an instruction of the industrial computer (10), and acquiring a target point position coordinate signal of the industrial equipment to reach a preset position from the instruction;

The pulse signal acquisition module (24) is used for receiving a pulse signal of the motor encoder (13);

a pulse signal filtering module (25) for filtering the pulse signal;

a path comparison module (22) for comparing the target point coordinate signal with the actual point coordinate signal and judging whether the error of the comparison result is less than or equal to a threshold value;

a storage module (21) for storing the target point bit coordinate signal and the threshold parameter;

the ultra-high speed output module (23) is used for sending the result of the operation comparison to an output port;

the path comparison module (22) is respectively connected with the pulse signal filtering module (25), the storage module (21) and the ultra-high speed output module (23), the storage module (21) is connected with the EtherCAT communication module (31), and the pulse signal filtering module (25) is connected with the pulse signal acquisition module (24).

4. A high speed high precision path comparison controller according to claim 3 wherein said memory module (21) is a high speed hardware FIFO memory module.

5. A high-speed high-precision path comparison controller according to claim 3, wherein the storage module (21), the path comparison module (22), the ultra-high speed output module (23), the pulse signal acquisition module (24) and the pulse signal filtering module (25) are arranged in an FPGA system (20).

6. A high-speed high-precision path comparison controller according to claim 3, further comprising a high-speed output module (33) for outputting the result of the coordinate comparison, wherein the high-speed output module (33) is disposed outside the FPGA system (20), and the high-speed output module (33) is connected to the path comparison module (22).

7. A high speed high accuracy path comparison controller according to claim 3 wherein said pulse signal filtering module (25) is an infinite impulse response filtering module.

8. A high speed high precision path comparison controller according to claim 3 wherein the EtherCAT communication module (31) is a two-way EtherCAT ad hoc network communication module.

9. A high speed high accuracy path compare controller as recited in claim 3 further comprising a control module for controlling the comparison of multiple independent high speed output coordinates.

10. A high speed high precision path comparison controller according to claim 3 further comprising a filter module (32), said filter module (32) being disposed outside said FPGA system (20).