CN111857012A - Multi-path high-performance communication system based on OpenVpx standard - Google Patents
Multi-path high-performance communication system based on OpenVpx standard Download PDFInfo
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- CN111857012A CN111857012A CN202010771489.8A CN202010771489A CN111857012A CN 111857012 A CN111857012 A CN 111857012A CN 202010771489 A CN202010771489 A CN 202010771489A CN 111857012 A CN111857012 A CN 111857012A
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- openvpx
- communication system
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- interface
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25174—Ethernet
Abstract
The invention discloses a multi-path high-performance communication system based on an OpenVpx standard, which comprises an FPGA controller and an OpenVPX interface; the controller communicates with the OpenVPX interface via a bus that includes an ethernet circuit, a GTX circuit, and an RS422 circuit. The invention can realize the communication function with each module and the external device in the whole machine by taking the FPGA as the information exchange center, the communication between each module in the machine is completed through the gigabit Ethernet bus, and the communication with the outside is carried out by adopting the Ethernet circuit, the GTX circuit and the RS422 circuit, thereby meeting the functional requirements of different users and providing the compatibility and the expansibility of system transmission data.
Description
Technical Field
The invention relates to the technical field of communication control, in particular to a multi-path high-performance communication system based on the OpenVpx standard.
Background
With the progress of technology, the communication quality is more and more emphasized, and this requires excellent performance of the communication substrate. In addition, in order to meet the functional requirements of the current user, a user-defined parallel bus is generally used, so that the bandwidth is low, the expandability is poor, equipment of each manufacturer and a board card are incompatible, and the communication is easy to be unstable; the base plate needs to be developed by itself, the product development period is long, and the production and maintenance cost is high. Conventional bus architectures have not been able to accommodate the requirements of current systems.
Disclosure of Invention
Aiming at the problems of low bandwidth, poor expansibility and incompatibility of switching equipment in the prior art, the invention provides a multi-path high-performance communication system based on the OpenVpx standard, which can realize the communication function with each module in the whole machine and each single machine outside by using an FPGA as an information switching center, complete the communication among the modules in the machine through a gigabit Ethernet bus, and improve the compatibility and expansibility of the system by adopting different buses for communication with the outside.
In order to achieve the purpose, the invention provides the following technical scheme:
a multi-path high-performance communication system based on an OpenVpx standard comprises a controller and an OpenVPX interface; the controller communicates with the OpenVPX interface via a bus that includes an ethernet circuit, a GTX circuit, and an RS422 circuit.
Preferably, the controller is an FPGA controller, which is of the type XC7VX 690T.
Preferably, the power supply circuit is used for supplying power to a system, and the self-checking circuit is used for self-checking input voltage; and the power supply circuit and the self-checking circuit are respectively connected with the controller.
Preferably, the bus further comprises 8 paths of GPIO circuits to realize interface expansion application of the controller.
Preferably, the system also comprises an ARM processor which is used for processing and allocating the transaction information; the ARM processor is connected with the controller in a bidirectional mode.
Preferably, the ethernet circuit includes a PHY chip and a transformer, the controller is bidirectionally connected to the PHY chip through an RGMII interface, and the PHY chip is connected to the OpenVPX interface after passing through the transformer.
Preferably, the FPGA controller includes a peripheral module, a peripheral interface, and a storage configuration unit.
Preferably, the peripheral module includes a clock module, a power module, a JTAG configuration module, and a reset module.
Preferably, the storage configuration unit comprises a DDR3SDRAM external memory and a Flash configuration module; the Flash configuration module is used for storing configuration information, and the DDR3SDRAM external memory is used for data caching.
Preferably, the peripheral interface comprises an RS422 serial port and a GTX interface; and the RS422 serial port is used for data interaction between the FPGA controller and external equipment, and the GTX is a high-speed interface.
In summary, due to the adoption of the technical scheme, compared with the prior art, the invention at least has the following beneficial effects:
the invention can realize the communication function with each module and the external device in the whole machine by taking the FPGA as the information exchange center, the communication between each module in the machine is completed through the gigabit Ethernet bus, and the communication with the outside is carried out by adopting the Ethernet circuit, the GTX circuit and the RS422 circuit, thereby meeting the functional requirements of different users and providing the compatibility and the expansibility of system transmission data.
Description of the drawings:
fig. 1 is a schematic diagram of a multi-path high-performance communication system based on the OpenVpx standard according to an exemplary embodiment of the present invention.
Fig. 2 is a schematic diagram of ethernet communication according to an exemplary embodiment of the present invention.
Fig. 3 is a front view of a multi-path high-performance communication board based on the OpenVpx standard according to an exemplary embodiment of the present invention.
Fig. 4 is a side view of a plurality of high-performance communication boards based on the OpenVpx standard according to an exemplary embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and embodiments. It should be understood that the scope of the above-described subject matter is not limited to the following examples, and any techniques implemented based on the disclosure of the present invention are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience of description and for simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
As shown in fig. 1, the present invention provides a multi-path high performance communication system based on the OpenVpx standard, which includes an FPGA controller, a power supply circuit, a self-test circuit, and an OpenVpx interface;
the power supply circuit and the self-checking circuit are respectively connected with the FPGA controller, and the FPGA controller is communicated with the OpenVPX interface through a bus.
The power circuit can adopt a DC/DC module, and the model can adopt LT4644IY for supplying power to the system (for example, 5V input voltage); the FPGA controller is used for transmitting and processing various data information (voltage, communication data and the like); the self-checking circuit (existing voltage self-checking circuit) is used for self-checking the input 5V voltage.
In this embodiment, a bus through which the FPGA controller communicates with the OpenVPX interface includes 20 channels of gigabit ethernet circuits, 10 channels of GTX circuits, and 1 channel of RS422 circuits. The gigabit Ethernet circuit realizes the processing from the PHY layer to the MAC layer of the Ethernet data; the GTX circuit realizes high-speed signal data transmission; the RS422 circuit realizes low-speed signal data transmission.
In this embodiment, the bus further includes 8 GPIO circuits to implement interface expansion application of the FPGA controller.
In this embodiment, in order to meet the requirement of transaction management, the system further includes an ARM processor for processing and allocating transaction information; the ARM processor is in bidirectional connection with the FPGA controller.
As shown in fig. 2, in this embodiment, the ethernet circuit includes a PHY chip and a transformer, the FPGA controller is bidirectionally connected to the PHY chip through an RGMII interface, and the PHY chip is connected to the OpenVPX through the transformer. The structure can play a role in electrical isolation, prevent the PHY chip from being damaged, and simultaneously can enhance signals and improve transmission distance.
In this embodiment, the FPGA controller may adopt XC7VX690T of Xilinx corporation, which has low power consumption, high performance, high flexibility, and expandability.
In this embodiment, the FPGA controller includes a peripheral module, a peripheral interface, and a storage configuration unit.
The peripheral module comprises a clock module, a power module, a JTAG configuration module and a reset module, so that the system has a power-on reset function and an external reset signal receiving function and is used for resetting the system; the peripheral interface mainly comprises an RS422 serial port and a GTX high-speed interface, the RS422 serial port is used for data interaction between the FPGA controller and external equipment, the GTX is a high-speed interface, and a 125Mhz clock can be configured and selected through the GTX controller on the FPGA to realize the transmission rate of 2.5Gb/s, and the maximum transmission rate can reach 12.5 Gb/s; the storage configuration unit comprises a 2GB DDR3SDRAM external storage and a Flash configuration module, wherein the Flash configuration module is used for storing configuration information, and the DDR3SDRAM is used for data caching.
As shown in fig. 3 and 4, the present invention further provides a communication board, where the board is in a 6U structure, the heat dissipation requirement is fully considered, the board is designed according to the standards of VITA46, VITA48, and VITA65, the board includes a printed board, a front cover, and a rear cover, the printed board is loaded with the above multi-path high performance communication system based on the OpenVpx standard, and the printed board is connected to an OpenVpx interface.
In this embodiment, the length L1 of the front cover is 214.75mm, the width H1 is 147mm, and the chamfer distance d1 is 12.1 mm; the length L2 of the rear cover is 210.75mm, the width H2 is 141.3mm, and the chamfer distance d2 is 13.3 mm; the chamfer angles a are all 135 degrees; and the front cover and the rear cover are fixed through screw holes, and the diameter R of each screw hole is 6 mm.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A multi-path high-performance communication system based on the OpenVpx standard is characterized by comprising a controller and an OpenVPX interface; the controller communicates with the OpenVPX interface via a bus that includes an ethernet circuit, a GTX circuit, and an RS422 circuit.
2. The OpenVpx standard-based multi-path high-performance communication system of claim 1, wherein the controller is an FPGA controller having a model number XC7VX 690T.
3. The multi-path high-performance communication system based on the OpenVpx standard according to claim 1, further comprising a power supply circuit for supplying power to the system and a self-test circuit for performing self-test on an input voltage; and the power supply circuit and the self-checking circuit are respectively connected with the controller.
4. The OpenVpx standard-based multi-path high-performance communication system of claim 1, wherein the bus further comprises 8-path GPIO circuitry to implement an interface extension application for the controller.
5. The OpenVpx-standard-based multi-path high-performance communication system of claim 1, further comprising an ARM processor for processing and coordinating transaction information; the ARM processor is connected with the controller in a bidirectional mode.
6. The multi-path high-performance communication system according to claim 1, wherein the ethernet circuit comprises a PHY chip and a transformer, the controller is bidirectionally connected to the PHY chip via an RGMII interface, and the PHY chip is connected to the OpenVpx interface via the transformer.
7. The OpenVpx standard-based multi-path high-performance communication system of claim 2, wherein the FPGA controller comprises a peripheral module, a peripheral interface, and a memory configuration unit.
8. The OpenVpx-standard-based multi-path high-performance communication system of claim 7, wherein the peripheral modules include a clock module, a power module, a JTAG configuration module, and a reset module.
9. The OpenVpx standard-based multi-path high-performance communication system of claim 7, wherein the memory configuration unit comprises a DDR3SDRAM external memory and a Flash configuration module; the Flash configuration module is used for storing configuration information, and the DDR3SDRAM external memory is used for data caching.
10. The OpenVpx standard-based multi-path high-performance communication system of claim 7, wherein the peripheral interface comprises an RS422 serial port and a GTX interface; and the RS422 serial port is used for data interaction between the FPGA controller and external equipment, and the GTX is a high-speed interface.
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| CN202010771489.8A CN111857012A (en) | 2020-08-04 | 2020-08-04 | Multi-path high-performance communication system based on OpenVpx standard |
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| CN202010771489.8A CN111857012A (en) | 2020-08-04 | 2020-08-04 | Multi-path high-performance communication system based on OpenVpx standard |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594627A (en) * | 2012-03-12 | 2012-07-18 | 华中科技大学 | Gigabit Ethernet field bus communication device based on FPGA |
| CN102609389A (en) * | 2011-12-22 | 2012-07-25 | 成都傅立叶电子科技有限公司 | Digital signal processing platform achieved on basis of VPX bus |
| CN105335327A (en) * | 2015-10-13 | 2016-02-17 | 电子科技大学 | Reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc |
| CN105868145A (en) * | 2016-04-25 | 2016-08-17 | 北京中科海讯数字科技股份有限公司 | High-speed serial bus storage device provided with multiple high-speed interfaces |
| CN109120624A (en) * | 2018-08-27 | 2019-01-01 | 北京计算机技术及应用研究所 | A kind of more plane loose coupling high band wide data exchange systems |
| CN210864698U (en) * | 2020-01-10 | 2020-06-26 | 河南普大信息技术有限公司 | Signal processing board card based on VPX structure |
-
2020
- 2020-08-04 CN CN202010771489.8A patent/CN111857012A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102609389A (en) * | 2011-12-22 | 2012-07-25 | 成都傅立叶电子科技有限公司 | Digital signal processing platform achieved on basis of VPX bus |
| CN102594627A (en) * | 2012-03-12 | 2012-07-18 | 华中科技大学 | Gigabit Ethernet field bus communication device based on FPGA |
| CN105335327A (en) * | 2015-10-13 | 2016-02-17 | 电子科技大学 | Reconfigurable/dual redundancy VPX3U signal processing carrier board based on Soc |
| CN105868145A (en) * | 2016-04-25 | 2016-08-17 | 北京中科海讯数字科技股份有限公司 | High-speed serial bus storage device provided with multiple high-speed interfaces |
| CN109120624A (en) * | 2018-08-27 | 2019-01-01 | 北京计算机技术及应用研究所 | A kind of more plane loose coupling high band wide data exchange systems |
| CN210864698U (en) * | 2020-01-10 | 2020-06-26 | 河南普大信息技术有限公司 | Signal processing board card based on VPX structure |
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Application publication date: 20201030 |