CN111835991A - Display data channel circuit - Google Patents
Display data channel circuit Download PDFInfo
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- CN111835991A CN111835991A CN201910310578.XA CN201910310578A CN111835991A CN 111835991 A CN111835991 A CN 111835991A CN 201910310578 A CN201910310578 A CN 201910310578A CN 111835991 A CN111835991 A CN 111835991A
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- display data
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- 239000000872 buffer Substances 0.000 claims abstract description 67
- 230000005540 biological transmission Effects 0.000 claims abstract description 47
- 238000004891 communication Methods 0.000 claims abstract description 39
- 230000003139 buffering effect Effects 0.000 claims abstract description 4
- 230000001629 suppression Effects 0.000 claims description 19
- 230000001052 transient effect Effects 0.000 claims description 19
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000002457 bidirectional effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013016 damping Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
Abstract
A display data channel circuit for realizing a communication connection between a transmission source device and a display device. The display data channel circuit comprises a selection circuit, a main control module and a plurality of transmission circuits. Each transmission circuit is electrically connected between the transmission source equipment and the selection circuit. Each transmission circuit comprises a buffer module which is electrically connected between the sending source equipment and the selection circuit and is used for temporarily storing and buffering communication signals sent by the sending source equipment. The selection circuit is used for selecting one transmission circuit from the plurality of transmission circuits to transmit the communication signals in the buffer module to the main control module. The main control module is electrically connected with the selection circuit and is used for correspondingly receiving the audio and video signals sent by the sending source equipment according to the communication signals. Therefore, the problem of signal attenuation caused by long-distance transmission can be avoided.
Description
Technical Field
The invention relates to a display data channel circuit.
Background
Generally, due to the outstanding advantage of High Definition Multimedia Interface (HDMI) technology in transmitting digital audio/video signals, since the 2002 HDMI1.0 standard was introduced, more and more HDMI interfaces are installed on the HDMI Interface. Meanwhile, the HDMI specification requires that the input capacity of a Display Data Channel (DDC) of the HDMI is lower than 50 PF.
In the prior art, when the distance between the main control chip of the receiving device and the HDMI interface is long, a long line will cause signal attenuation when transmitting signals.
Disclosure of Invention
Accordingly, there is a need for a display data channel circuit that avoids signal degradation caused by long distance transmission.
A display data channel circuit is used for realizing communication connection between a sending source device and a display device and comprises a selection circuit, a main control module and a plurality of transmission circuits;
each transmission circuit is electrically connected between the sending source equipment and the selection circuit, each transmission circuit comprises a buffer module, the buffer module is electrically connected between the sending source equipment and the selection circuit, and the buffer module is used for temporarily storing and buffering communication signals sent by the sending source equipment;
the selection circuit is used for selecting one transmission circuit from the plurality of transmission circuits to transmit the communication signals in the buffer module to the master control module; and
the master control module is electrically connected with the selection circuit and is used for correspondingly receiving the audio and video signals sent by the sending source equipment according to the communication signals.
Furthermore, each transmission circuit further comprises an interface, and the interface is used for being electrically connected with the interface of the transmission source device.
Furthermore, each transmission circuit further comprises a storage module, each storage module is electrically connected with each buffer module, and the storage module is used for recording address information of the corresponding communication signal.
Further, the interface is a high-definition multimedia interface.
Further, the communication signal is an integrated circuit bus signal.
Further, the buffer module comprises a buffer device, which is PCA 9617A.
Furthermore, the buffer module further includes a first resistor and a second resistor, the first clock pin and the first data pin of the buffer device are connected to the interface, the first power pin of the buffer device is connected to a power supply, the first data pin is connected to the power supply through the first resistor, and the first clock pin is connected to the power supply through the second resistor.
Furthermore, the buffer module further includes a first bidirectional transient suppression diode, a second bidirectional transient suppression diode, a first capacitor and a second capacitor, the first data pin is further grounded through the first bidirectional transient suppression diode, two ends of the first capacitor are respectively connected to two ends of the first bidirectional transient suppression diode, the first clock pin is further grounded through the second bidirectional transient suppression diode, and two ends of the second capacitor are respectively connected to two ends of the second bidirectional transient suppression diode.
Furthermore, the buffer module further includes a third capacitor, a third resistor, a fourth resistor, and a fifth resistor, a second power pin of the buffer device is connected to the power supply, the second power pin is further grounded through the third capacitor, an enable pin of the buffer device is connected to the second power pin through the fifth resistor, a second clock pin and a second data pin of the buffer device are respectively connected to the memory module through the third resistor and the fourth resistor, and the second clock pin and the second data pin of the buffer device are further respectively connected to the selection circuit through the third resistor and the fourth resistor.
Further, the storage module is a charged erasable programmable read-only memory.
The display data channel circuit is divided into two parts by connecting the buffer module between the interface and the storage module, so that the capacitance value of each part is reduced, and signal attenuation caused by long-distance signal transmission is avoided.
Drawings
FIG. 1 is a block diagram showing a preferred embodiment of a data channel circuit.
Fig. 2 is a circuit diagram of a preferred embodiment of the buffer module of fig. 1.
Description of the main elements
Display data channel circuit 100
Resistors R1, R2, R3, R4 and R5
Bidirectional transient suppression diodes D1, D2
Capacitors C1, C2 and C3
Power VCC
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the display data channel circuit of the present invention will be described in detail with reference to the accompanying drawings and embodiments.
Referring to fig. 1, in a preferred embodiment of the present invention, a display data channel circuit 100 is used to implement a communication connection between a transmission source device 200 and a display device 300. The display data channel circuit 100 includes a plurality of transmission circuits 10, a selection circuit 20 and a main control module 30.
The plurality of transmission circuits 10 are electrically connected between the transmission source device 200 and the selection circuit 20, and the main control module 30 is electrically connected between the selection circuit 20 and the display device 300.
Each of the transmission circuits 10 includes an interface 12, a buffer module 14, and a storage module 16. The buffer module 14 is electrically connected between the interface 12 and the storage module 16, the interface 12 is electrically connected to the transmission source device 200, and the buffer module 14 is electrically connected to the selection circuit 20. In this embodiment, the number of the transmission circuits 10 is two. In other embodiments, the number of transmission circuits 10 may also be more than two.
The interface 12 is configured to be plugged into an interface (not shown) of the transmission source device 200, when the interface 12 is plugged into the interface of the transmission source device 200, the transmission source device 200 is electrically connected to the display data channel circuit 100, and the transmission source device 200 transmits a source signal to the display data channel circuit 100 and the display device 300 through the interface 12. The source signal comprises an audio and video signal and a communication signal, and the communication signal comprises address information of the source signal, namely interface information corresponding to the source signal during transmission. The interface 12 transmits the communication signal to the buffer module 14 connected correspondingly.
The buffer module 14 is configured to receive the communication signal transmitted by the interface 12 and temporarily buffer the communication signal. As such, the buffer module 14 may divide the display data channel circuit 100 into two portions of circuits. Specifically, the first part of the circuits is the circuits from the interface 12 to the buffer module 14, and the second part of the circuits is the circuits from the buffer module 14 to the main control module 30. In this way, the capacitance of each part of the circuit can be relatively reduced to make the input capacitance of the display data channel circuit 100 meet the requirement, and signal attenuation caused by long-distance signal transmission can be avoided.
The buffer module 14 transmits the communication signal to the storage module 16. The storage module 16 is configured to record address information of the corresponding communication signal.
In this embodiment, the storage module 16 may be a charged erasable Programmable read only memory (EEPROM).
In this embodiment, the interface 12 is a High Definition Multimedia Interface (HDMI), the HDMI is connected to the transmission source device 200 through a cable of the HDMI, and the source signal is a High Definition multimedia signal. The interface 12, the buffer module 14, the storage module 16, the selection Circuit 20, and the main control module 30 are all connected through an integrated Circuit bus (I2C), and the communication signal is an integrated Circuit bus signal.
The selection circuit 20 selects to establish a communication connection with one transmission circuit 10 of the plurality of transmission circuits 10 under the control of a control unit (not shown), so as to receive the communication signal transmitted by the buffer module 14 and transmit the communication signal to the main control module 30. Specifically, the control unit selects the corresponding transmission circuit 10 to establish communication connection with the selection circuit 20 according to the address information in the storage module 16.
The main control module 30 receives the communication signal transmitted by the selection circuit 20, and receives the corresponding audio/video signal transmitted by the interface 12 according to the communication signal. The main control module 30 further controls the display device 300 to output display information according to the audio/video signal.
Referring to fig. 2, fig. 2 is a circuit diagram of the buffer module 14 in the present embodiment. The snubber module 14 includes a snubber device 142, five resistors R1-R5, two bidirectional transient suppression diodes D1-D2, and three capacitors C1-C3.
The first clock pin SCLA and the first data pin SDAA of the buffer device 142 are both connected to the interface 12. The first power pin VCC _ a of the buffer device 142 is connected to the power VCC. The first data pin SDAA is further connected to the power supply VCC through the resistor R1. The first clock pin SCLA is also connected to the power source VCC through the resistor R2. The first data pin SDAA is further grounded through the bidirectional transient suppression diode D1, and two ends of the capacitor C1 are respectively connected to two ends of the bidirectional transient suppression diode D1. The first clock pin SCLA is also grounded through the bidirectional transient suppression diode D2, and two ends of the capacitor C2 are connected to two ends of the bidirectional transient suppression diode D2, respectively. The bidirectional transient suppression diodes D1 and D2 are used to improve the overvoltage protection capability of the first clock pin SCLA and the first data pin SDAA, respectively.
The second power supply pin VCC _ B of the buffer device 142 is connected to the power supply VCC, and the second power supply pin VCC _ B of the buffer device 142 is also grounded through a capacitor C3. The enable pin EN of the buffer device 142 is connected to the second power supply pin VCC _ B through the resistor R5. The second clock pin SCLB and the second data pin SDAB of the buffer device 142 are connected to the memory module 16 through the resistor R3 and the resistor R4, respectively. The second clock pin SCLB and the second data pin SDAB of the buffer device 142 are connected to the selection circuit 20 through the resistor R3 and the resistor R4, respectively. The pin GND of the buffer device 142 is grounded.
In this embodiment, the damping device 142 is a PCA 9617A. The power VCC is a 5V power. The resistance values of the resistor R1 and the resistor R2 are both 10K ohms.
The buffer device 142 in this embodiment operates at a frequency of up to 1 mhz, and is compatible with the fast mode (400KHz) and the standard mode (100KHz) of the integrated circuit bus, whereas the operating frequency of the integrated circuit bus in this embodiment is 100 KHz. The buffer device 142 can ensure that the working mode of the integrated circuit bus in this embodiment is unchanged, thereby playing a role of temporary storage and buffering for communication signals in the transmission process.
The operation of the display data channel circuit 100 according to the present invention will be described in detail below.
In operation, the transmission source device 200 transmits a communication signal to the first clock pin SCLA and the first data pin SDAA of the buffer device 142 through the interface 12, the buffer device 142 buffers the communication signal temporarily, and transmits the communication signal to the selection circuit 20 through the second clock pin SCLB and the second data pin SDAB. The selection circuit 20 selects and receives a communication signal transmitted by the buffer module 14 under the control of the control unit, and transmits the communication signal to the main control module 30. The main control module 30 receives the communication signal transmitted by the selection circuit 20, and receives the corresponding audio/video signal transmitted by the interface 12 according to the communication signal, and the main control module 30 controls the display device 300 to output display information according to the audio/video signal.
The display data channel circuit 100 divides the display data channel circuit 100 into two parts by connecting the buffer module 14 between the interface 12 and the memory module 16, so that the input capacitance value of the display data channel circuit 100 meets the requirement, and signal attenuation caused by long-distance transmission can be avoided.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited, although the present invention is described in detail with reference to the preferred embodiments.
It will be understood by those skilled in the art that various modifications and equivalent arrangements can be made without departing from the spirit and scope of the present invention.
Moreover, based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without any creative effort will fall within the protection scope of the present invention.
Claims (10)
1. A display data channel circuit is used for realizing communication connection between a sending source device and a display device and is characterized in that the display data channel circuit comprises a selection circuit, a main control module and a plurality of transmission circuits;
each transmission circuit is electrically connected between the sending source equipment and the selection circuit, each transmission circuit comprises a buffer module, the buffer module is electrically connected between the sending source equipment and the selection circuit, and the buffer module is used for temporarily storing and buffering communication signals sent by the sending source equipment;
the selection circuit is used for selecting one transmission circuit from the plurality of transmission circuits to transmit the communication signals in the buffer module to the master control module; and
the master control module is electrically connected with the selection circuit and is used for correspondingly receiving the audio and video signals sent by the sending source equipment according to the communication signals.
2. The display data channel circuit of claim 1, wherein each of the transmission circuits further comprises an interface for electrically connecting with an interface of the transmission source device.
3. The display data channel circuit of claim 2, wherein each of the transmission circuits further comprises a memory module, each of the memory modules is electrically connected to each of the buffer modules, and the memory modules are configured to record address information of the corresponding communication signals.
4. The display data channel circuit of claim 3, wherein the interface is a high definition multimedia interface.
5. The display data channel circuit of claim 4, wherein the communication signal is an integrated circuit bus signal.
6. The display data channel circuit of claim 5, wherein the buffer module comprises a buffer device, the buffer device being PCA 9617A.
7. The display data channel circuit of claim 6, wherein the buffer module further comprises a first resistor and a second resistor, a first clock pin and a first data pin of the buffer device are connected to the interface, a first power pin of the buffer device is connected to a power supply, the first data pin is connected to the power supply through the first resistor, and the first clock pin is connected to the power supply through the second resistor.
8. The display data channel circuit of claim 7, wherein the buffer module further comprises a first bi-directional transient suppression diode, a second bi-directional transient suppression diode, a first capacitor, and a second capacitor, the first data pin is further coupled to ground through the first bi-directional transient suppression diode, two ends of the first capacitor are respectively coupled to two ends of the first bi-directional transient suppression diode, the first clock pin is further coupled to ground through the second bi-directional transient suppression diode, and two ends of the second capacitor are respectively coupled to two ends of the second bi-directional transient suppression diode.
9. The display data channel circuit of claim 8, wherein the buffer module further comprises a third capacitor, a third resistor, a fourth resistor, and a fifth resistor, the second power pin of the buffer device is connected to the power supply, the second power pin is further connected to ground through the third capacitor, the enable pin of the buffer device is connected to the second power pin through the fifth resistor, the second clock pin and the second data pin of the buffer device are connected to the memory module through the third resistor and the fourth resistor, respectively, and the second clock pin and the second data pin of the buffer device are further connected to the selection circuit through the third resistor and the fourth resistor, respectively.
10. The display data channel circuit of claim 4, wherein the memory module is a powered erasable programmable read only memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910310578.XA CN111835991B (en) | 2019-04-17 | 2019-04-17 | Display data channel circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910310578.XA CN111835991B (en) | 2019-04-17 | 2019-04-17 | Display data channel circuit |
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| Publication Number | Publication Date |
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| CN111835991A true CN111835991A (en) | 2020-10-27 |
| CN111835991B CN111835991B (en) | 2024-04-02 |
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| CN201910310578.XA Active CN111835991B (en) | 2019-04-17 | 2019-04-17 | Display data channel circuit |
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| CN108965761A (en) * | 2017-05-18 | 2018-12-07 | 亚德诺半导体集团 | High speed serialization link for video interface |
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| CN109600532A (en) * | 2018-12-13 | 2019-04-09 | 中国科学院西安光学精密机械研究所 | Unmanned plane multi-channel video seamless switch-over system and method |
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2019
- 2019-04-17 CN CN201910310578.XA patent/CN111835991B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090022176A1 (en) * | 2007-07-21 | 2009-01-22 | Nguyen James T | System and method for converting communication interfaces and protocols |
| CN102065231A (en) * | 2010-11-26 | 2011-05-18 | 深圳中兴力维技术有限公司 | Multipath data fusion device, realization method thereof and multipath audio data processing system |
| CN103686039A (en) * | 2012-09-11 | 2014-03-26 | 北京同步科技有限公司 | Multichannel video capture card and processing method thereof |
| CN204697177U (en) * | 2015-06-15 | 2015-10-07 | 深圳市尼得科技有限公司 | A kind of automatic switching control circuit of multi-channel video monitor |
| CN205726099U (en) * | 2016-05-05 | 2016-11-23 | 深圳市汉普锐科技有限公司 | The video matrix system that a kind of multi-format video signal is switched fast |
| CN205901911U (en) * | 2016-06-27 | 2017-01-18 | 广州格芬电子科技有限公司 | HDMI information source multiple entry multichannel output matrix distributes switch |
| CN108965761A (en) * | 2017-05-18 | 2018-12-07 | 亚德诺半导体集团 | High speed serialization link for video interface |
| CN109101204A (en) * | 2017-06-21 | 2018-12-28 | 鸿富锦精密工业(武汉)有限公司 | The communication system of signal circuit and the application signal circuit |
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| CN111835991B (en) | 2024-04-02 |
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