CN111834290A - Method of manufacturing integrated circuit device - Google Patents

Method of manufacturing integrated circuit device Download PDF

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Publication number
CN111834290A
CN111834290A CN202010079164.3A CN202010079164A CN111834290A CN 111834290 A CN111834290 A CN 111834290A CN 202010079164 A CN202010079164 A CN 202010079164A CN 111834290 A CN111834290 A CN 111834290A
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China
Prior art keywords
wiring
mask layer
layer
hard mask
groove
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Application number
CN202010079164.3A
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Chinese (zh)
Inventor
权渡玹
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN111834290A publication Critical patent/CN111834290A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a method of manufacturing an integrated circuit device. The method of manufacturing an integrated circuit device includes: a device layer, a wiring insulating layer and a hard mask layer are sequentially formed on a semiconductor substrate. The method includes sequentially removing a first region and a second region of the hard mask layer using a first mask layer having a first opening and a second mask layer having a second opening as etch masks, respectively. The method includes forming a first wiring groove and a second wiring groove by removing a portion of the wiring insulating layer using a portion of the hard mask layer as an etching mask, the first wiring groove passing through the wiring insulating layer, the second wiring groove having a depth smaller than a depth of the first wiring groove. Further, the method includes forming a wiring structure in the first and second wiring grooves.

Description

Method of manufacturing integrated circuit device
[ CROSS-REFERENCE TO RELATED APPLICATIONS ]
This application claims the right of korean patent application No. 10-2019-0045134, which was filed by the korean intellectual property office on 17.4.2019, the entire disclosure of which is incorporated herein by reference.
Technical Field
The present disclosure relates to methods of manufacturing integrated circuit devices.
Background
As electronic technology advances, the scaling of integrated circuit devices is rapidly progressing. In a scaled down integrated circuit device, a process margin of a process for interconnecting the wiring layer and the via plug may be reduced.
Disclosure of Invention
The present inventive concept provides a method of manufacturing an integrated circuit device, which is capable of interconnecting a wiring layer and a via plug even when a process margin for forming the wiring layer and the via plug is reduced according to the shrinkage of the integrated circuit device.
To overcome the above technical problems, the present inventive concept provides a method of manufacturing an integrated circuit device. According to some embodiments herein, a method of manufacturing an integrated circuit device may comprise: a device layer, a wiring insulating layer and a hard mask layer are sequentially formed on a semiconductor substrate. The device layer may include a plurality of semiconductor devices. The method may include sequentially removing a first region and a second region of the hard mask layer using a first mask layer having a first opening extending in a first horizontal direction and a second mask layer having a second opening extending in the first horizontal direction as etch masks, respectively. A portion of the second opening may overlap a stitching region including the first portion of the wiring insulating layer in a vertical direction and may overlap a portion of the first opening in the vertical direction. The method may include forming a first wiring groove and a second wiring groove by removing the first portion of the wiring insulating layer using a third region of the hard mask layer remaining after removing the first region and the second region of the hard mask layer as an etching mask, the first wiring groove passing through the wiring insulating layer, the second wiring groove having a depth smaller than a depth of the first wiring groove. Further, the method may include forming a wiring structure in the first and second wiring grooves and electrically connected to the plurality of semiconductor devices.
According to some embodiments herein, a method of manufacturing an integrated circuit device may comprise: a device layer, a wiring insulating layer, an etching stop film and a hard mask layer are sequentially formed on a semiconductor substrate, wherein the semiconductor substrate comprises a part positioned in a splicing area of an integrated circuit device. The device layer may include a plurality of semiconductor devices. The method may include forming a first groove in a hard mask layer by removing a first region of the hard mask layer using the first mask layer having a first opening as an etch mask, the first opening having a portion located in the split region and extending in a first horizontal direction. The method may include forming a second groove by removing a second region of the hard mask layer using a second mask layer having a second opening as an etch mask, the second opening having a portion located in the split region and extending in the first horizontal direction. The method may include removing a first portion of the etch stop film located in the split region. The method may include removing a third region of the hard mask layer and a second portion of the etch stop film through the first groove, removing a fourth region of the hard mask layer and a third portion of the etch stop film through the second groove, and removing a portion of the upper first portion of the wiring insulating layer located in the split region. Further, the method may include forming a first wiring groove and forming a second wiring groove by removing a second portion of the wiring insulating layer using a fifth region of the hard mask layer remaining after removing the third region and the fourth region of the hard mask layer as an etching mask, the first wiring groove penetrating the wiring insulating layer in the split region, the second wiring groove having a depth smaller than a depth of the first wiring groove.
According to some embodiments herein, a method of manufacturing an integrated circuit device may comprise: a semiconductor substrate having a split region, a wiring insulating layer, an etching stopper film, a first hard mask layer and a second hard mask layer is sequentially formed. The method may include forming a first groove by removing a first region of the second hard mask layer using a first mask layer having a first opening extending in a first horizontal direction and having a portion located in the split region as an etch mask. The method may include forming a second recess by removing a second region of the second hard mask layer and a first portion of the first hard mask layer located in the split region using a second mask layer having a second opening as an etch mask, the second opening extending in the first horizontal direction and having a first portion located in the split region and a second portion different from the first opening. The method may include removing a first portion of the etch stop film located in the split region. The method may include removing a second portion of the first hard mask layer and a second portion of the etch stop film through the first groove, removing a third portion of the first hard mask layer and a third portion of the etch stop film through the second groove, and removing a portion of the upper first portion of the wiring insulating layer in the split region. Further, the method may include forming a first wiring groove and a second wiring groove by removing a second portion of the wiring insulating layer using the fourth portion of the first hard mask layer as an etching mask, the first wiring groove passing through the wiring insulating layer, the second wiring groove having a depth smaller than a depth of the first wiring groove. The first wiring groove may be formed in the split region.
Drawings
Embodiments of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which:
fig. 1A to 9C are plan and cross-sectional views shown according to a process sequence for explaining a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept, wherein, specifically, each of fig. 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, and 9B and each of fig. 1C, 2C, 3C, 4C, 5C, 6C, 7C, 8C, and 9C are cross-sectional views taken along lines B-B 'and C-C' of each of fig. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, and 9A.
Fig. 10A to 10C are plan and cross-sectional views shown to explain a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept, wherein, in particular, fig. 10B and 10C are cross-sectional views taken along lines B-B 'and C-C' in fig. 10A.
Fig. 11A through 15C are plan and cross-sectional views shown in accordance with a process sequence for explaining a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept, wherein, in particular, each of fig. 11B, 12B, 13B, 14B, and 15B and each of fig. 11C, 12C, 13C, 14C, and 15C are cross-sectional views taken along lines B-B 'and C-C' of each of fig. 11A, 12A, 13A, 14A, and 15A.
Fig. 16A to 16C are plan and cross-sectional views shown to explain a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept, in which, in particular, fig. 16B and 16C are cross-sectional views taken along lines B-B 'and C-C' in fig. 16A.
Detailed Description
Fig. 1A to 9C are plan and cross-sectional views illustrating a process sequence according to a method for explaining an exemplary embodiment of the method of manufacturing an integrated circuit device according to the inventive concept. Specifically, each of fig. 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, and 9B and each of fig. 1C, 2C, 3C, 4C, 5C, 6C, 7C, 8C, and 9C are cross-sectional views taken along line B-B 'and line C-C' of each of fig. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, and 9A.
Referring to fig. 1A to 1C, a device layer 120 is formed on a semiconductor substrate 110, the device layer 120 including a plurality of semiconductor devices 150. For example, the semiconductor substrate 110 may include silicon (Si). Alternatively, the semiconductor substrate 110 may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The semiconductor substrate 110 may also include a Silicon On Insulator (SOI) structure. For example, the semiconductor substrate 110 may include a Buried Oxide (BOX) layer. The semiconductor substrate 110 may include a conductive region such as a well doped with impurities or a structure doped with impurities. In addition, the semiconductor substrate 110 may include various device isolation structures, such as a Shallow Trench Isolation (STI) structure. The semiconductor substrate 110 may include an active surface and a passive surface opposite the active surface.
The device layer 120 including the plurality of semiconductor devices 150 may be formed on the active surface of the semiconductor substrate 110.
At least a portion of the plurality of semiconductor devices 150 may include transistors. For example, at least a portion of the plurality of semiconductor devices 150 may include Bipolar Junction Transistors (BJTs) or Field Effect Transistors (FETs). For example, at least a portion of the plurality of semiconductor devices 150 may comprise planar transistors (planar transistors) or Fin field effect transistors (finfets). When at least a portion of the plurality of semiconductor devices 150 includes finfets, a plurality of fin-type active regions may protrude and extend in parallel to each other in a horizontal direction (X-direction or Y-direction) in the semiconductor base 110.
The plurality of semiconductor devices 150 may constitute a logic unit. The logic cells may be variously configured to include a plurality of circuit elements, such as transistors, resistors, and the like. The logic units may constitute, for example, AND, NAND, OR, NOR, XOR, XNOR (XNOR), Inverter (INV), Adder (ADD), Buffer (BUF), Delay (DLY), Filter (FIL), multiplexer (MXT/MXIT), OAI (or/and/inverter), AO (and/or), AOI (and/or/inverter), D flip-flop, reset flip-flop, master-slave flip-flop, latch, and the like. The logic cells may also constitute standard cells that perform desired logic functions (e.g., counters, buffers, etc.).
The plurality of semiconductor devices 150 may include various individual devices for constituting a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), an Application Processor (AP), etc., or various individual devices for constituting a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, an electrically erasable programmable read-only memory (EEPROM) device, a phase-change random access memory (PRAM) device, a Magnetic Random Access Memory (MRAM) device, and a resistive random access memory (MRAM), etc.
The device layer 120 may include semiconductor devices 150, conductive lines and plugs for connecting the semiconductor devices 150 to each other, and an insulating layer filling a space between the semiconductor devices 150. The device layer 120 may include various types and shapes of conductive, semiconductive, and insulative materials. In addition, the insulating layer can be positioned on the conducting wire and the conducting plug.
The lower wiring structure 200 may be formed on the device layer 120. In some embodiments, the lower wiring structure 200 may be formed using a dual damascene process. The lower wiring structure 200 may be electrically connected to each semiconductor device 150 such that the lower wiring structure 200 may provide electrical connections between the plurality of semiconductor devices 150 and the reference wiring structure 300 described with reference to fig. 10A through 10C.
The lower wiring structure 200 may include a lower wiring layer 210 and a lower via plug 220 connected to the lower wiring layer 210. The lower wiring insulating layer 250 may fill a space between the lower wiring layer 210 and the lower via plug 220 and a space adjacent to the lower wiring layer 210 and the lower via plug 220. In some embodiments, the lower wiring layer 210 and the lower via plug 220 may contact each other and may be integrally formed.
For example, the lower wiring layer 210 may include a plurality of lines extending in a line shape in the first horizontal direction (X direction) in parallel with each other. The extension length of the lower wiring layer 210 in the first horizontal direction (X direction) shown in fig. 1A and 1B is an illustrative example, and is not limited thereto.
The lower wiring structure 200 may also include a lower barrier layer 230, the lower barrier layer 230 surrounding the bottom and side surfaces of the lower wiring layer 210 and the lower via plug 220. The lower barrier layer 230 may be disposed between (a) the lower wiring layer 210 and the lower via plug 220, and (b) the lower wiring insulation layer 250. In some embodiments, the lower barrier layer 230 may also be disposed between the lower via plug 220 and a conductive layer in contact with the bottom surface of the lower via plug 220. In some embodiments, the lower wiring structure 200 may further include a lower cover layer 240 covering an upper surface of the lower wiring layer 210.
For example, the lower wiring layer 210 and the lower via plug 220 may include a metal material, such as tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), ruthenium (Ru), manganese (Mn), or cobalt (Co). For example, the lower barrier layer 230 may include a nitride or oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or may include an alloy such as cobalt tungsten phosphide (CoWP), cobalt tungsten boron (CoWB), cobalt tungsten boron phosphide (CoWBP), or the like. For example, the lower capping layer 240 may include a metal material, such as W, Ti, Ta, Ru, Mn, or Co. For example, the lower wiring insulating layer 250 may include silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the lower wiring insulating layer 250 may include a tetraethyl orthosilicate (TEOS) film or an Ultra Low K (ULK) film having an ultra low K of 2.2 to 2.4. The ULK film may include a silicon oxycarbide (SiOC) film or a carbon-doped silicon oxide (SiCOH) film.
A lower etch stop film 290 may be formed on the lower wiring structure 200 and the lower wiring insulating layer 250 to cover the upper surface of the lower wiring layer 210 and the upper surface of the lower wiring insulating layer 250. In some embodiments, when the lower cover layer 240 covers the upper surface of the lower wiring layer 210, the lower etch stop film 290 may cover the upper surface of the lower cover layer 240 and the upper surface of the lower wiring insulation layer 250. For example, the lower etch stop film 290 may include a nitride, such as silicon nitride (SiN) or aluminum nitride (AlN). In some embodiments, the lower etch stop film 290 may comprise a material that does not include carbon.
A reference wiring insulating layer 350 may be formed on the lower etch stop film 290 to cover the lower wiring structure 200 and the lower wiring insulating layer 250. For example, the reference wiring insulating layer 350 may include silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the reference wiring insulating layer 350 may include a TEOS film or an ULK film having an ultra-low dielectric constant of 2.2 to 2.4. The ULK film may include a SiOC film or a SiCOH film.
In some embodiments, after the lower etch stop film 290 covering the device layer 120 is formed without forming the lower wiring structure 200 and the lower wiring insulating layer 250, the reference wiring insulating layer 350 covering the lower etch stop film 290 may be formed.
A reference etch stop film 390 and a reference hard mask layer 410 may be sequentially formed on the reference wiring insulating layer 350. For example, the reference etch stop film 390 may comprise silicon carbon nitride (SiCN) or may comprise a stack structure of SiCN/SiN or SiCN/SiN/AlN. In some embodiments, the reference etch stop film 390 may include a carbon-containing material. The reference hard mask layer 410 may include titanium nitride (TiN) or silicon oxynitride (SiON) or may include a stack structure of SiON/TiN. In some embodiments, the reference hard mask layer 410 may include a first reference hard mask layer 412 and a second reference hard mask layer 414 stacked on the first reference hard mask layer 412. For example, the first reference hard mask layer 412 may comprise a metal nitride such as TiN, and the second reference hard mask layer 414 may comprise an oxynitride such as SiON. In some embodiments, the first reference hard mask layer 412 may comprise a metal nitride such as TiN and the second reference hard mask layer 414 may comprise a carbon-containing material such as SiC or SiCN, and in this case, the reference etch stop film 390 may comprise a material that does not contain carbon, for example, a nitride (e.g., SiN or AlN). Each of the reference etch stop film 390, the first reference hard mask layer 412, and the second reference hard mask layer 414 may include different ones of (i) a metal nitride material, (ii) an oxynitride material, and (iii) a material including carbon.
The first reference hard mask layer 412 and the second reference hard mask layer 414 may have a large etching selectivity ratio or may have similar etching characteristics according to the conditions of the etching process.
A first mask layer MK1 having a first opening MO1 may be formed on the reference hard mask layer 410. For example, first mask layer MK1 may include or may be formed using photoresist. In some embodiments, the first anti-reflection film 510 may be formed on the reference hard mask layer 410 before the first mask layer MK1 is formed.
For example, the first opening MO1 may be formed in a plurality of line shapes extending in the second horizontal direction (Y direction) in parallel with each other. In some embodiments, the first horizontal direction (X-direction) and the second horizontal direction (Y-direction) may be perpendicular to each other. The first opening MO1 may include a first cut opening MO1a and a first extended opening MO1 b. An extension length of the first cutting opening MO1a in the second horizontal direction (Y direction) may be less than an extension length of the first extension opening MO1 b. For example, a portion of the first cutting opening MO1a may overlap a portion of the lower wiring layer 210 under the first cutting opening MO1a, and one end portion of the first cutting opening MO1a in the second horizontal direction (Y direction) may overlap a portion adjacent to a side surface of the lower wiring layer 210 under the first cutting opening MO1a in the vertical direction (Z direction). In some embodiments, one end portion of the first cut opening MO1a may be aligned in a vertical direction (Z direction) with a portion of a side surface of the lower wiring layer 210 below the first cut opening MO1 a.
In the first cutting opening MO1a, a portion adjacent to one end portion of the first cutting opening MO1a and overlapping a portion of the lower wiring layer 210 under the first cutting opening MO1a may be defined as a first mask split region MS 1. The first mask split region MS1 of the first opening MO1 may correspond to a portion overlapping the second opening MO2 illustrated in fig. 3A to 3C in the vertical direction (Z direction). A portion of the second opening MO2 overlapping the first mask split region MS1 in the vertical direction (Z direction) may be defined as a second mask split region MS 2.
As used herein, the term "mosaic region" may refer to any portion of the integrated circuit device that overlaps first mask mosaic region MS1 and/or second mask mosaic region MS2 in the vertical direction (Z-direction). For example, the split region may include a portion of the reference wiring insulating layer 350 overlapping the first mask split region MS1 and/or the second mask split region MS2 in the vertical direction (Z direction). Further, in some embodiments, the stitching region may extend vertically from the top of the integrated circuit device to the bottom of the integrated circuit device.
Herein, a portion of the first opening MO1 (i.e., the first mask split region MS1) may overlap a portion of the second opening MO2 (i.e., the second mask split region MS2) may mean a portion of the semiconductor substrate 110, a portion of the lower wiring layer 210, and a portion of the reference wiring insulating layer 350 that overlap the first mask split region MS1 of the first opening MO1 in a vertical direction, and may be the same portion as a portion of the semiconductor substrate 110, a portion of the lower wiring layer 210, and a portion of the reference wiring insulating layer 350 that overlap the second mask split region MS2 in a vertical direction, respectively.
Meanwhile, for convenience of explanation and easy indication of a relationship with other elements, the terms "reference", "upper" and "lower" included in element names are used herein. For example, except for the words consisting of the terms "reference," "upper," and "lower," themselves, elements having the same or similar designation and including the terms "upper" and "lower" may be used herein to refer to elements arranged in an "upper" position and a "lower" position, respectively, by using an element including the term "reference" as a reference. Thus, elements including the terms "reference," "upper," and "lower" may be used herein to refer to the same elements, while the terms "reference," "upper," and "lower" are omitted when there is no need to compare positional relationships with one another. For example, each of the reference wiring insulation layer 350, the reference etch stop film 390, the reference hard mask layer 410, the first reference hard mask layer 412, and the second reference hard mask layer 414 may refer to the wiring insulation layer 350, the etch stop film 390, the hard mask layer 410, the first hard mask layer 412, and the second hard mask layer 414, respectively.
Referring to fig. 1A to 2C together, the first groove 414O1 may be formed by removing the first region 410R1, which is a portion of the reference hard mask layer 410, using the first mask layer MK1 as an etch mask. The first region 410R1 may be a portion of the reference hard mask layer 410 located below the first opening MO1 of the first mask layer MK1 and the first groove 414O1 may be a portion of the reference hard mask layer 410 where the first region 410R1 is removed. After the first groove 414O1 is formed, the first mask layer MK1 and the first anti-reflection film 510 may be removed.
The first groove 414O1 may extend from the upper surface of the reference hard mask layer 410 toward the semiconductor substrate 110 in the vertical direction (Z direction), but the reference etch stop film 390 may not be exposed at the bottom level of the first groove 414O1 (e.g., may not be exposed through/may not be exposed via the lower region). That is, the depth of the first recess 414O1 in the vertical direction (Z direction) may be less than the thickness of the reference hard mask layer 410.
When the reference hard mask layer 410 includes the first reference hard mask layer 412 and the second reference hard mask layer 414 stacked on the first reference hard mask layer 412, the first groove 414O1 may pass through the second reference hard mask layer 414 and then expose the first reference hard mask layer 412 at the bottom level of the first groove 414O 1. That is, the first groove 414O1 may be formed by removing a portion of the second reference hard mask layer 414 using the first mask layer MK1 as an etch mask. The depth of the first recess 414O1 in the vertical direction (Z direction) may be equal to or greater than the thickness of the second reference hard mask layer 414.
The first groove 414O1 may include a first cut groove 414O1a corresponding to the first cut opening MO1a of the first mask layer MK1 and a first extension groove 414O1b corresponding to the first extension opening MO1b of the first mask layer MK 1. The extension length of the first cutting groove 414O1a in the second horizontal direction (Y direction) may be less than the extension length of the first extension groove 414O1 b. For example, a portion of the first cutting groove 414O1a may overlap a portion of the lower wiring layer 210 below the first cutting groove 414O1a, and one end portion of the first cutting groove 414O1a in the second horizontal direction (Y direction) may overlap a portion adjacent to a side surface of the lower wiring layer 210 below the first cutting groove 414O1a in the vertical direction (Z direction). In some embodiments, one end portion of the first cutting groove 414O1a may be aligned in the vertical direction (Z direction) with a portion of the side surface of the lower wiring layer 210 below the first cutting groove 414O1 a.
In the first cutting groove 414O1a, a portion adjacent to one end portion of the first cutting groove 414O1a and overlapping with a portion of the lower wiring layer 210 under the first cutting groove 414O1a may be defined as a first groove tap region 414S.
Referring to fig. 3A to 3C together, a second mask layer MK2 having a second opening MO2 may be formed on the reference hard mask layer 410 having the first groove 414O 1. For example, second mask layer MK2 may include or may be formed using photoresist. In some embodiments, a second anti-reflection film 520 may be formed on the reference hard mask layer 410 before forming the second mask layer MK 2.
For example, the second opening MO2 may be formed in a plurality of line shapes extending in the second horizontal direction (Y direction) in parallel with each other. The second opening MO2 may include a second cutting opening MO2a and a second extending opening MO2 b. An extension length of the second cutting opening MO2a in the second horizontal direction (Y direction) may be less than an extension length of the second extension opening MO2 b. Further, the widths of each of the first and second cutting openings MO1a and MO2a in the first horizontal direction (X direction) may have the same value.
A portion of the second opening MO2 and a portion of the first groove 414O1 may overlap each other in the vertical direction (Z direction). For example, a portion of the second cutting opening MO2a and a portion of the first cutting groove 414O1a may overlap each other in the vertical direction (Z direction), and the second extension opening MO2b and the first extension groove 414O1b may not overlap each other in the vertical direction (Z direction). Specifically, a portion of the second cutting opening MO2a may overlap the first groove split region 414S in the vertical direction (Z direction).
For example, a portion of the second cut opening MO2a may overlap a portion of the lower wiring layer 210 under the second cut opening MO2a, and one end portion of the second cut opening MO2a in the second horizontal direction (Y direction) may overlap a portion adjacent to a side surface of the lower wiring layer 210 under the second cut opening MO2a in the vertical direction (Z direction). In some embodiments, one end portion of the second cut opening MO2a may be aligned in the vertical direction (Z direction) with a portion of the side surface of the lower wiring layer 210 below the second cut opening MO2 a.
A portion of the second cutting opening MO2a overlapping the first groove tap region 414S in the vertical direction (Z direction) may be defined as a second mask tap region MS 2. The second mask split region MS2 may be a portion overlapping with a portion of the lower wiring layer 210 located below.
Referring to fig. 3A to 4C together, the second groove 414O2 may be formed by removing the second region 410R2, which is a portion of the reference hard mask layer 410, using the second mask layer MK2 as an etch mask. The second region 410R2 may be a portion of the reference hard mask layer 410 located under the second opening MO2 of the second mask layer MK2 and the second groove 414O2 may be a portion of the reference hard mask layer 410 where the second region 410R2 is removed. After the second groove 414O2 is formed, the second mask layer MK2 and the second anti-reflection film 520 may be removed.
The second groove 414O2 may include a second cut groove 414O2a corresponding to the second cut opening MO2a of the second mask layer MK2 and a second extension groove 414O2b corresponding to the second extension opening MO2b of the second mask layer MK 2. The second cutting groove 414O2a may communicate with the first cutting groove 414O1 a. The first groove 414O1 and the second groove 414O2 together may constitute a reference groove 410O.
The reference recess 410O may extend from the upper surface of the reference hard mask layer 410 toward the semiconductor substrate 110 in the vertical direction (Z direction), but the reference etch stop film 390 may be exposed at a portion of the bottom level of the reference recess 410O (e.g., may be exposed through/may be exposed through the first portion), and the reference etch stop film 390 may not be exposed at another portion of the bottom level of the reference recess 410O (e.g., may not be exposed through/may not be exposed through the second portion). Specifically, the reference etch stop film 390 may be exposed at a bottom level of a portion of the reference groove 410O corresponding to the second mask split region MS2, and the reference etch stop film 390 may not be exposed at a bottom level of the remaining portion of the reference groove 410O.
A portion of the reference groove 410O formed corresponding to the second mask split region MS2 may be defined as a reference groove split region 410S. The reference groove tap region 410S may pass through the reference hard mask layer 410 in the vertical direction (Z direction), and then the reference etch stop film 390 may be exposed at the bottom level of the reference groove tap region 410S. The reference groove tap region 410S may include a first groove tap region 414S passing through the second reference hard mask layer 414 in the vertical direction (Z direction) and a second groove tap region 412S passing through the first reference hard mask layer 412 in the vertical direction (Z direction), wherein the first groove tap region 414S and the second groove tap region 412S may communicate with each other. The first groove tap region 414S may be a portion formed using the first mask layer MK1 shown in fig. 1A to 1C, and the second groove tap region 412S may be a portion formed using the second mask layer MK2 shown in fig. 3A to 3C. That is, the reference groove splicing region 410S may be formed in a portion corresponding to a portion where the first opening MO1 of the first mask layer MK1 and the second opening MO2 of the second mask layer MK2 overlap.
The reference etch stop film 390 may be exposed at a bottom level of a first portion of the reference groove split region 410S in the reference groove 410O, and the first reference hard mask layer 412 may be exposed at a bottom level of a second portion of the reference groove region 410O.
Referring collectively to fig. 4A-5C, a portion of the reference hard mask layer 410 may be removed to form a hard mask opening 412O. In the process of forming the hard mask opening 412O, the second reference hard mask layer 414 of the reference hard mask layer 410 may be removed, and a portion of the first reference hard mask layer 412 may remain. For example, with respect to the results shown in fig. 4A-4C, a blanket etch (blanket etch) may be performed to remove the second reference hard mask layer 414 and the exposed portion of the first reference hard mask layer 412. At this time, a portion of the reference etch stop film 390 exposed at the bottom of the reference groove tap region 410S may also be removed to form a first etch opening 390O1 exposing the reference wiring insulation layer 350 in a portion of the reference etch stop film 390 corresponding to the reference groove tap region 410S. First etch opening 390O1 may be in communication with hard mask opening 412O.
Referring to fig. 1A to 5C together, the hard mask opening 412O may correspond to the first opening MO1 of the first mask layer MK1 and the second opening MO2 of the second mask layer MK2, and may be formed in a portion of the reference hard mask layer 410 overlapping therewith in the vertical direction (Z direction), i.e., a portion of the first reference hard mask layer 412.
In this case, the first etch opening 390O1 may be formed in a portion of the reference etch stop film 390 corresponding to a portion of the first opening MO1 of the first mask layer MK1 overlapping the second opening MO2 of the second mask layer MK2 in the vertical direction (Z direction), and the first etch opening 390O1 may communicate with the hard mask opening 412O. Specifically, the first etch opening 390O1 may be formed in a portion of the reference etch stop film 390 corresponding to a portion adjacent to and overlapping one end of each of the first cut opening MO1a of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2 in the vertical direction (Z direction), and the first etch opening 390O1 may communicate with the hard mask opening 412O.
Center lines (e.g., line C-C' in fig. 1A to 5C) of the first cut opening MO1A of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2, which partially overlap each other, in a long axis direction (e.g., Y direction) may be located on the same straight line, and widths of the first cut opening MO1A of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2 in a short axis direction (e.g., X direction) may be the same. That is, the center lines of the first cut opening MO1A of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2, which partially overlap each other, in the long axis direction (e.g., Y direction) may be located on the same straight line (e.g., line C-C' in fig. 1A to 5C) on the semiconductor substrate 110, the lower wiring layer 210, and the reference wiring insulating layer 350, which overlap each other in the vertical direction (Z direction). Accordingly, the hard mask opening 412O formed corresponding to the first cut opening MO1a of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2 may have a shape extending in the second horizontal direction (Y direction) and having a constant width in the first horizontal direction (X direction), similar to the hard mask opening 412O formed corresponding to the first extended opening MO1b of the first mask layer MK1 and the second extended opening MO2b of the second mask layer MK 2. However, unlike the hard mask opening 412O formed corresponding to the first extension opening MO1b of the first mask layer MK1 and the second extension opening MO2b of the second mask layer MK2, the hard mask opening 412O formed corresponding to the first cut opening MO1a of the first mask layer MK1 and the second cut opening MO2a of the second mask layer MK2 may be formed to communicate with the first etch opening 390O 1.
Herein, for convenience of understanding, the first opening MO1 of the first mask layer MK1 is separately described by dividing the first opening MO1 of the first mask layer MK1 into a first cut opening MO1a and a first extended opening MO1b, and the second opening MO2 of the second mask layer MK2 is also separately described by dividing the second opening MO2 of the second mask layer MK2 into a second cut opening MO2a and a second extended opening MO2 b. That is, even though an overlapping portion of the first opening MO1 of the first mask layer MK1 overlapping the second opening MO2 of the second mask layer MK2 and a connection portion connected to the overlapping portion adjacent thereto are separately described as conceptually a first cut opening MO1a, and another portion of the first opening MO1 of the first mask layer MK1 is conceptually referred to as conceptually a first extended opening MO1b, the first cut opening MO1a and the first extended opening MO1b in the first mask layer MK1 may be referred to oppositely in another region, depending on the positions to be shown in other drawings than these drawings. Similarly, the second cut opening MO2a and the second extension opening MO2b in the second mask layer MK2 may be referred to oppositely in another region depending on the positions to be shown in other drawings than these drawings.
Herein, all of the reference groove tap region 410S of the reference hard mask layer 410, the second groove tap region 412S of the first reference hard mask layer 412, the first groove tap region 414S of the second reference hard mask layer 414, the first mask tap region MS1 of the first opening MO1, and the second mask tap region MS2 of the second opening MO2 may substantially overlap each other in a vertical direction (Z direction) with respect to the semiconductor substrate 110. Accordingly, any portion of the integrated circuit device corresponding to the reference groove tap region 410S, the first groove tap region 414S, the second groove tap region 412S, the first mask tap region MS1, and the second mask tap region MS2 that overlap each other in the vertical direction (Z direction) with respect to the semiconductor substrate 110 (e.g., the reference groove tap region 410S, the first groove tap region 414S, the second groove tap region 412S, the first mask tap region MS1, and the second mask tap region MS2 that overlap each other in the vertical direction (Z direction) may be defined as a tap region.
Referring to fig. 6A to 6C together, a portion of the reference etch stop film 390 may be removed using the first reference hard mask layer 412 having the hard mask opening 412O as an etch mask to form a second etch opening 390O2 exposing the reference wiring insulating layer 350. In the process of forming the second etch opening 390O2, a portion of the upper portion of the reference wiring insulating layer 350 exposed under the first etch opening 390O1 may also be removed, and thus the preliminary reference wiring groove 350R1p may be formed. The preliminary reference wiring groove 350R1p may extend downward from the upper surface of the reference wiring insulation layer 350, and the lower level of the preliminary reference wiring groove 350R1p may be lower than the level of the upper surface of the reference wiring insulation layer 350 and may be higher than the lower surface of the reference wiring insulation layer 350 so that a portion of the reference wiring insulation layer 350 may be maintained in an exposed state at the lower level of the preliminary reference wiring groove 350R1 p.
First etch opening 390O1 and second etch opening 390O2 may together form a reference etch opening 390O.
Referring to fig. 7A to 7C together, the reference wiring groove 350R may be formed by removing a portion of the reference wiring insulating layer 350 using the reference etch stop film 390 (which uses the reference etch opening 390O) as an etch mask. The reference wiring groove 350R may include a first reference wiring groove 350R1 and a second reference wiring groove 350R 2.
Since a portion of the reference wiring insulating layer 350 is removed under the condition that the preliminary reference wiring groove 350R1p shown in fig. 6A to 6C is formed on the lower side of the first etched opening 390O1, the depth of the first reference wiring groove 350R1, which is a portion of the reference wiring groove 350R formed on the lower side of the first etched opening 390O1, may be greater than the depth of the second reference wiring groove 350R2, which is a portion of the reference wiring groove 350R formed on the lower side of the second etched opening 390O 2.
The first reference wiring groove 350R1 may extend from an upper surface of the reference wiring insulation layer 350 to a lower surface of the reference wiring insulation layer 350 such that the lower wiring structure 200 may be exposed through/via a lower level of the first reference wiring groove 350R 1. The second reference wiring groove 350R2 may extend downward from the upper surface of the reference wiring insulating layer 350, and the lower level of the second reference wiring groove 350R2 may be lower than the level of the upper surface of the reference wiring insulating layer 350 and may be higher than the lower surface of the reference wiring insulating layer 350 so that a portion of the reference wiring insulating layer 350 may be maintained in an exposed state at the lower level of the second reference wiring groove 350R 2. That is, the first reference wiring groove 350R1 may be formed by removing the reference wiring insulating layer 350 from the upper surface to the lower surface of the reference wiring insulating layer 350, and the second reference wiring groove 350R2 may be formed by removing a portion of the upper portion of the reference wiring insulating layer 350.
Referring to fig. 8A to 8C together, after forming the reference barrier layer 330 covering the reference etch stop film 390 and the exposed surface of the reference wiring insulating layer 350 having the reference wiring groove 350R, a reference wiring material layer 315 may be formed on the reference barrier layer 330. The reference barrier layer 330 may be conformally formed on the reference etch stop film 390 and the exposed surface of the reference wiring insulating layer 350 having the reference wiring groove 350R. The reference wiring material layer 315 may be formed in the reference wiring groove 350R (e.g., filling the reference wiring groove 350R) and on an upper surface of the reference etch stop film 390 (e.g., covering the upper surface of the reference etch stop film 390).
The reference barrier layer 330 may include a nitride or oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or may include an alloy such as CoWP, CoWB, CoWBP, or the like. The reference wiring material layer 315 may include a metal material such as W, Cu, Ti, Ta, Ru, Mn, or Co.
Referring to fig. 8A to 9C together, a portion of the reference wiring material layer 315 on the upper surface of the reference etch stop film 390 (e.g., covering the upper surface of the reference etch stop film 390) may be removed to form the reference wiring layer 310 and the reference via plug 320. The reference wiring layer 310 may refer to a portion of the remaining portion of the reference wiring material layer 315 located at a level higher than the bottom level of the second reference wiring groove 350R2, and the reference via plug 320 may refer to a portion of the remaining portion of the reference wiring material layer 315 located at a level lower than the bottom of the second reference wiring groove 350R2 and connected to the reference wiring layer 310. Accordingly, the reference wiring layer 310 may have a substantially constant height and width and may extend in the second horizontal direction (Y direction), and the reference via plug 320 may have a substantially constant horizontal area below the reference wiring layer 310 or may extend in the vertical direction (Z direction) toward the semiconductor substrate 110 while the horizontal area continues to decrease or increase.
In the process of forming the reference wiring layer 310 and the reference via plug 320, a portion of the reference barrier layer 330 covering the upper surface of the reference etch stop film 390 and the reference etch stop film 390 may be removed together so that the upper surface of the reference wiring insulation layer 350 may be exposed.
To form the reference wiring layer 310 and the reference via plug 320, a process of removing a portion of the reference wiring material layer 315 may be performed by a chemical-mechanical polishing (CMP) method. In the process of forming the reference wiring layer 310 and the reference via plug 320, the reference etch stop film 390 may be completely removed.
Fig. 10A to 10C are plan and cross-sectional views shown to explain a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept. Specifically, fig. 10B and 10C are cross-sectional views taken along lines B-B 'and C-C' in fig. 10A. In fig. 10A to 10C, the same reference numerals as in fig. 1A to 9C denote the same components, and repeated detailed descriptions thereof may be omitted herein.
Referring to fig. 10A to 10C, the integrated circuit device 1 may include a device layer 120 including a plurality of semiconductor devices 150, a lower wiring structure 200, and a reference wiring structure 300. The lower wiring structure 200 may be electrically connected to each semiconductor device 150 such that the lower wiring structure 200 may provide electrical connections between the plurality of semiconductor devices 150 and the reference wiring structure 300.
The lower wiring structure 200 may include a lower wiring layer 210 and a lower via plug 220 connected to the lower wiring layer 210. The lower wiring insulating layer 250 may fill a space between the lower wiring layer 210 and the lower via plug 220. In some embodiments, the lower wiring layer 210 and the lower via plug 220 contacting each other may be integrally formed.
The lower wiring layer 210 may be formed in a plurality of line shapes extending in parallel to each other in the first horizontal direction (X direction). The lower via plug 220 may extend from the bottom surface of the lower wiring layer 210 toward the semiconductor substrate 110.
The lower wiring structure 200 may also include a lower barrier layer 230, the lower barrier layer 230 surrounding the bottom and side surfaces of the lower wiring layer 210 and the lower via plug 220. The lower barrier layer 230 may be disposed between (a) the lower wiring layer 210 and the lower via plug 220, and (b) the lower wiring insulation layer 250. In some embodiments, the lower wiring structure 200 may further include a lower cover layer 240 covering an upper surface of the lower wiring layer 210.
The lower etch stop film 290 may cover the upper surface of the lower wiring structure 200 and the upper surface of the lower wiring insulating layer 250. The lower etch stop film 290 may cover a portion of the upper surface of the lower wiring layer 210 or a portion of the upper surface of the lower cover layer 240. The reference wiring structure 300 may be connected to a portion of the upper surface of the lower wiring layer 210 or the upper surface of the lower cover layer 240 that is not covered by the lower etch stop film 290.
The reference wiring structure 300 may include a reference wiring layer 310 and a reference via plug 320 connected to the reference wiring layer 310. The reference wiring insulating layer 350 may fill a space between the reference wiring layer 310 and the reference via plug 320. In some embodiments, the reference wiring layer 310 and the reference via plug 320 contacting each other may be integrally formed.
The reference wiring layers 310 may be formed in plural in a line shape extending in the second horizontal direction (Y direction) in parallel to each other. The reference via plug 320 may extend from the bottom surface of the reference wiring layer 310 toward the semiconductor substrate 110 to be electrically connected to the lower wiring structure 200.
The reference wiring structure 300 may also include a reference barrier layer 330, the reference barrier layer 330 surrounding the reference wiring layer 310 and the bottom and side surfaces of the reference via plug 320. The reference barrier layer 330 may be disposed between (a) the reference wiring layer 310 and the reference via plug 320, and (b) the reference wiring insulation layer 350. In some embodiments, the reference routing structure 300 may also include a reference capping layer 340 that covers an upper surface of the reference routing layer 310.
The lower etch stop film 290 may be disposed between the lower wiring insulating layer 250 and the reference wiring insulating layer 350. However, since the reference etch stop film 390 shown in fig. 1A to 8C may be completely removed as described with reference to fig. 9A to 9C, the reference etch stop film 390 may not remain on the reference wiring insulating layer 350 and the reference wiring structure 300. Accordingly, the reference etch stop film 390 may not be disposed between the reference wiring insulating layer 350 and an insulating layer (e.g., the upper wiring insulating layer 650 shown in fig. 11A to 11C) disposed on an upper side of the reference wiring insulating layer 350, so that an upper surface of the reference wiring insulating layer 350 and a lower surface of the upper wiring insulating layer 650 may contact each other.
Referring to fig. 1A to 10C together, the reference via plug 320 included in the integrated circuit device 1 according to the concept of the present invention may be a full-aligned-via (FAV). The reference via plug 320 may be formed in a portion of the reference wiring insulating layer 350 corresponding to a portion where the first opening MO1 of the first mask layer MK1 and the second opening MO2 of the second mask layer MK2 overlap (i.e., a portion where the first mask split region MS1 and the second mask split region MS2 overlap).
Specifically, the reference via plug 320 may be aligned with a width in the first horizontal direction (X direction) of each of the first and second openings MO1 and MO2, and thus the width in the first horizontal direction (X direction) of the reference via plug 320 may be determined/controlled, and may also be aligned with a width in the second horizontal direction (Y direction) of a portion of the first and second openings MO1 and MO2 overlapping each other (i.e., a portion of the first and second mask split regions MS1 and MS2 overlapping each other), and thus the width in the second horizontal direction (Y direction) of the reference via plug 320 may be determined/controlled.
Therefore, unlike a via plug in a self-aligned via (SAV) in which via plugs are aligned with the width of openings of a mask layer for forming a wiring layer and the width of the via plug is limited in only one direction (for example, limited in a first horizontal direction (X direction)), the width of the reference via plug 320 in both a first horizontal direction (X direction) and a second horizontal direction (Y direction) perpendicular to each other can be limited, and thus the electrical reliability of the integrated circuit device 1 can be improved.
In some embodiments, the lower via plug 220 may be, but is not limited to, a SAV, and may be a FAV.
Fig. 11A to 15C are plan and cross-sectional views illustrating a process sequence according to a method for explaining an exemplary embodiment of the method of manufacturing an integrated circuit device according to the inventive concept. Specifically, each of fig. 11B, 12B, 13B, 14B, and 15B and each of fig. 11C, 12C, 13C, 14C, and 15C are cross-sectional views taken along line B-B 'and line C-C' of each of fig. 11A, 12A, 13A, 14A, and 15A. In fig. 11A to 15C, the same reference numerals as in fig. 1A to 10C denote the same components, and repeated detailed descriptions thereof may be omitted herein.
Referring to fig. 11A to 11C together, an upper wiring insulating layer 650 may be formed on the resultant structure of fig. 10A to 10C, i.e., on the reference wiring structure 300 and the reference wiring insulating layer 350. An upper surface of the reference wiring insulating layer 350 and a lower surface of the upper wiring insulating layer 650 may contact each other.
For example, the upper wiring insulating layer 650 may include silicon oxide or an insulating material having a dielectric constant lower than that of silicon oxide. In some embodiments, the upper wiring insulating layer 650 may include a TEOS film or an ULK film having an ultra-low dielectric constant of 2.2 to 2.4. The ULK film may include a SiOC film or a SiCOH film.
Referring to fig. 12A to 12C together, an upper etch stop film 690 and an upper hard mask layer 430 may be sequentially formed on the upper wiring insulating layer 650. For example, the upper etch stop film 690 may comprise SiCN or may comprise a stack structure of SiCN/SiN or SiCN/SiN/AlN. In some embodiments, upper etch stop film 690 may comprise a carbon-containing material. The upper hard mask layer 430 may include TiN or SiON or may include a SiON/TiN stack structure. In some embodiments, the upper hard mask layer 430 may include a first upper hard mask layer 432 and a second upper hard mask layer 434 stacked on the first upper hard mask layer 432. For example, the first upper hard mask layer 432 may comprise a metal nitride such as TiN, and the second upper hard mask layer 434 may comprise an oxynitride such as SiON. The first and second upper hard mask layers 432 and 434 may have a large etching selectivity ratio or may have similar etching characteristics according to the conditions of the etching process.
On the upper hard mask layer 430, a third mask layer MK3 having a third opening MO3 may be formed. For example, third mask layer MK3 may include or may be formed using photoresist. In some embodiments, a third anti-reflection film 530 may be formed on the upper hard mask layer 430 before forming the third mask layer MK 3.
For example, the third opening MO3 may be formed in a plurality of line shapes extending in the first horizontal direction (X direction) in parallel with each other. The third opening MO3 may include a third cut opening MO3a and a third extended opening MO3 b. An extension length of the third cutting opening MO3a in the first horizontal direction (X direction) may be less than an extension length of the third extension opening MO3 b. For example, a portion of the third cutout opening MO3a may overlap a portion of the reference wiring layer 310, and one end portion of the third cutout opening MO3a may overlap a portion adjacent to a side surface of the reference wiring layer 310 in the vertical direction (Z direction). In some embodiments, one end portion of the third cut opening MO3a may be aligned with a portion of the side surface of the reference wiring layer 310 located below in the vertical direction (Z direction).
A portion of the third cut opening MO3a adjacent to one end portion of the third cut opening MO3a and overlapping a portion of the reference wiring layer 310 under the third cut opening MO3a may be defined as a third mask split region MS 3. The third mask split region MS3 of the third opening MO3 may correspond to a portion overlapping with the fourth opening MO4 illustrated in fig. 13A to 13C in the vertical direction (Z direction). A portion of the fourth opening MO4 overlapping the third mask tap region MS3 in the vertical direction (Z direction) may be defined as a fourth mask tap region MS 4.
Referring to fig. 12A to 13C together, similar to the method set forth in fig. 2A to 3C, the third region 430R1, which is a portion of the upper hard mask layer 430, may be removed using the third mask layer MK3 as an etch mask to form a third groove 434O 1. The third region 430R1 may be a portion of the upper hard mask layer 430 located under the third opening MO3 of the third mask layer MK3, and thus the third groove 434O1 may be a portion removed from the upper hard mask layer 430. After the third groove 434O1 is formed, the third mask layer MK3 and the third anti-reflection film 530 may be removed.
The third groove 434O1 may extend from the upper surface of the upper hard mask layer 430 toward the semiconductor substrate 110 in the vertical direction (Z direction), but the upper etch stop film 690 may not be exposed at/through the lower level of the third groove 434O 1. That is, the depth of the third groove 434O1 in the vertical direction (Z direction) may have a value smaller than the thickness of the upper hard mask layer 430.
When the upper hard mask layer 430 includes the first upper hard mask layer 432 and the second upper hard mask layer 434 stacked on the first upper hard mask layer 432, the third groove 434O1 may pass through the second upper hard mask layer 434 and then expose the first upper hard mask layer 432 through/via the bottom level of the third groove 434O 1. That is, the third groove 434O1 may be formed by removing a portion of the second upper hard mask layer 434 using the third mask layer MK3 as an etch mask. The depth of the third groove 434O1 in the vertical direction (Z direction) may be equal to or greater than the thickness of the second upper hard mask layer 434.
The third groove 434O1 may include a third cutting groove 434O1a and a third extension groove 434O1b formed corresponding to the third cutting opening MO3a and the third extension opening MO3b of the third mask layer MK3, respectively. The extension length of the third cutting groove 434O1a in the first horizontal direction (X direction) may be less than that of the third extension groove 434O1 b. For example, a portion of the third cutting groove 434O1a may overlap a portion of the reference wiring layer 310 located below the third cutting groove 434O1a, and one end of the third cutting groove 434O1a may overlap a portion adjacent to a side surface of the reference wiring layer 310 located below the third cutting groove 434O1a in the vertical direction (Z direction). In some embodiments, one end portion of the third cutting groove 434O1a may be aligned with a portion of the side surface of the reference wiring layer 310 located below the third cutting groove 434O1a in the vertical direction (Z direction).
In the third cutting groove 434O1a, a portion adjacent to one end of the third cutting groove 434O1a and overlapping with a portion of the reference wiring layer 310 located below the third cutting groove 434O1a may be defined as a third groove tap region 434S.
A fourth mask layer MK4 having a fourth opening MO4 may be formed on the upper hard mask layer 430 having the third groove 434O 1. For example, fourth mask layer MK4 may include or may be formed using photoresist. In some embodiments, a fourth anti-reflection film 540 may be formed on the upper hard mask layer 430 before forming the fourth mask layer MK 4.
For example, the fourth opening MO4 may be formed in a plurality of line shapes extending in the first horizontal direction (X direction) in parallel with each other. The fourth opening MO4 may include a fourth cut opening MO4a and a fourth extended opening MO4 b. An extension length of the fourth cutting opening MO4a in the first horizontal direction (X direction) may be less than an extension length of the fourth extension opening MO4 b.
A portion of the fourth opening MO4 and a portion of the third groove 434O1 may overlap each other in the vertical direction (Z direction). For example, a portion of the fourth cutting opening MO4a and a portion of the third cutting groove 434O1a may overlap each other in the vertical direction (Z direction), and the fourth extension opening MO4b and the third extension groove 434O1b may not overlap each other in the vertical direction (Z direction). Specifically, a portion of the fourth cutting opening MO4a may overlap the third groove mating zone 434S in the vertical direction (Z direction).
For example, a portion of the fourth cutout opening MO4a may overlap a portion of the reference wiring layer 310 located under the fourth cutout opening MO4a, and one end portion of the fourth cutout opening MO4a may overlap a portion adjacent to a side surface of the reference wiring layer 310 located under the fourth cutout opening MO4a in the vertical direction (Z direction). In some embodiments, one end portion of the fourth cut opening MO4a may be aligned with a portion of the side surface of the reference wiring layer 310 located therebelow in the vertical direction (Z direction).
A portion of the fourth cutting opening MO4a overlapping the third groove tap 434S in the vertical direction (Z direction) may be defined as a fourth mask tap MS 4. Fourth mask split region MS4 may be a portion overlapping a portion of reference wiring layer 310 located therebelow.
Referring to fig. 13A to 14C together, the fourth region 430R2, which is a portion of the upper hard mask layer 430, may be removed using the fourth mask layer MK4 as an etch mask, similar to the method described with reference to fig. 4A to 4C, thereby forming a fourth groove 434O 2. The fourth region 430R2 is a portion of the upper hard mask layer 430 located under the fourth opening MO4 of the fourth mask layer MK4, and thus the fourth groove 434O2 may be a portion formed by removing the fourth region 430R 2. After the fourth groove 434O2 is formed, the fourth mask layer MK4 and the fourth anti-reflection film 540 may be removed.
The fourth groove 434O2 may include a fourth cutting groove 434O2a and a fourth extension groove 434O2b formed corresponding to the fourth cutting opening MO4a and the fourth extension opening MO4b of the fourth mask layer MK4, respectively. The fourth cutting groove 434O2a may communicate with the third cutting groove 434O1 a. The third groove 434O1 and the fourth groove 434O2 may together constitute an upper groove 430O.
The upper recess 430O may extend from the upper surface of the upper hard mask layer 430 toward the semiconductor substrate 110 in the vertical direction (Z direction), but the upper etch stop film 690 may be exposed through/via a portion of the bottom level of the upper recess 430O, and the upper etch stop film 690 may not be exposed through/via another portion of the bottom level of the upper recess 430O. Specifically, the upper etch stop film 690 may be exposed through/via the bottom level of the portion of the upper groove 430O formed corresponding to the fourth mask split region MS4, and the upper etch stop film 690 may not be exposed through/via the bottom level of the remaining portion of the upper groove 430O.
A portion of the upper groove 430O formed corresponding to the fourth mask split region MS4 may be defined as an upper groove split region 430S. The upper groove tap region 430S may pass through the upper hard mask layer 430 in the vertical direction (Z direction), and the bottom level of the upper groove tap region 430S may expose the upper etch stop film 690. The upper groove tap region 430S may include a third groove tap region 434S passing through the second upper hard mask layer 434 in the vertical direction (Z direction) and a fourth groove tap region 432S passing through the first upper hard mask layer 432 in the vertical direction (Z direction), and the third groove tap region 434S and the fourth groove tap region 432S may communicate with each other. The third groove tap region 434S may be a portion formed using the third mask layer MK3 shown in fig. 12A to 12C, and the fourth groove tap region 432S may be a portion formed using the fourth mask layer MK4 shown in fig. 13A to 13C. That is, the upper groove splicing region 430S may be formed in a portion corresponding to a portion where the third opening MO3 of the third mask layer MK3 and the fourth opening MO4 of the fourth mask layer MK4 overlap.
The upper etch stop film 690 may be exposed through/via the bottom level of the upper groove tap region 430S in the upper groove 430O, and the first upper hard mask layer 432 may be exposed through/via the bottom level of the remaining portion of the upper groove region 430O.
Referring collectively to fig. 14A-15C, in a similar manner as described with reference to fig. 5A-7C, a portion of the upper hard mask layer 430 can be removed, wherein the second upper hard mask layer 434 of the upper hard mask layer 430 can be removed, and a portion of the first upper hard mask layer 432 of the upper hard mask layer 430 can remain. At this time, the portion of the upper etch stop film 690 exposed at the bottom of the upper groove splitting region 430S may also be removed to form a third etch opening 690O1 exposing the upper wiring insulation layer 650.
Thereafter, a portion of the upper etch stop film 690 may then be removed using the first upper hard mask layer 432 as an etch mask to form a fourth etch opening 690O2 exposing the upper wiring insulation layer 650. In the process of forming the fourth etch opening 690O2, a portion of the upper wiring insulating layer 650 exposed under the third etch opening 690O1 may be removed. At this point, the remaining portions of the first upper hard mask layer 432 may also be removed. The third etching opening 690O1 and the fourth etching opening 690O2 may together constitute an upper etching opening 690O.
A portion of the upper wiring insulating layer 650 may be removed using the upper etch stop film 690 having the upper etch opening 690O as an etch mask to form an upper wiring groove 650R. The upper wiring groove 650R may include a first upper wiring groove 650R1 and a second upper wiring groove 650R 2.
Since a portion of the upper wiring insulating layer 650 under the third etched opening 690O1 has been removed before the upper wiring groove 650R is formed, a depth of the first upper wiring groove 650R1, which may be a portion of the upper wiring groove 650R and may be formed under the third etched opening 690O1, may be greater than a depth of the second upper wiring groove 650R2, which may be a portion of the upper wiring groove 650R and may be formed under the fourth etched opening 690O 2.
The first upper wiring groove 650R1 may extend from an upper surface of the upper wiring insulation layer 650 to a lower surface of the upper wiring insulation layer 650 such that the reference wiring structure 300 may be exposed through/via a bottom level of the first upper wiring groove 650R 1. The second upper wiring groove 650R2 may extend downward from the upper surface of the upper wiring insulation layer 650, and the bottom level of the second upper wiring groove 650R2 may be lower than the level of the upper surface of the upper wiring insulation layer 650 and higher than the level of the lower surface of the upper wiring insulation layer 650 so that a portion of the upper wiring insulation layer 650 may be maintained in an exposed state at the bottom level of the second upper wiring groove 650R 2.
Fig. 16A to 16C are plan and cross-sectional views shown to explain a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept. Specifically, fig. 16B and 16C are cross-sectional views taken along lines B-B 'and C-C' in fig. 16A. In fig. 16A to 16C, the same reference numerals as in fig. 1A to 15C denote the same members, and repeated detailed descriptions thereof may be omitted herein.
Referring collectively to fig. 16A through 16C, an upper wiring structure 600 may be formed to form an integrated circuit device 1a, in a similar manner to the method of forming the reference wiring structure 300 described with reference to fig. 8A through 10C.
Specifically, after the upper barrier layer 630 covering the exposed surface of the upper etch stop film 690 and the upper wiring insulation layer 650 having the upper wiring groove 650R shown in fig. 11A to 15C may be formed, an upper wiring material layer may be formed on the upper barrier layer 630. An upper barrier layer 630 may be conformally formed on the exposed surface of the upper etch stop film 690 and the upper wiring insulation layer 650 having the upper wiring groove 650R. An upper wiring material layer may be formed to fill the upper wiring groove 650R and be located on an upper surface of the upper etch stop film 690 (e.g., to cover the upper surface of the upper etch stop film 690).
The upper barrier layer 630 may include a nitride or oxide of a metal such as Ti, Ta, Ru, Mn, Co, or W, or may include an alloy such as CoWP, CoWB, CoWBP, or the like. The upper wiring material layer may contain a metal material such as W, Cu, Ti, Ta, Ru, Mn, or Co.
Thereafter, a portion of the upper wiring material layer on the upper surface of the upper etch stop film 690 (e.g., covering the upper surface of the upper etch stop film 690) may be removed to form the upper wiring layer 610 and the upper via plug 620. The upper wiring layer 610 may refer to a portion of the remaining portion of the upper wiring material layer located at a level higher than the bottom level of the second upper wiring groove 650R2, and the upper via plug 620 may refer to a portion of the remaining portion of the upper wiring material layer located at a level lower than the bottom of the second upper wiring groove 650R2 and connected to the upper wiring layer 610. Accordingly, the upper wiring layer 610 may have a substantially constant height and width and may extend in the first horizontal direction (X direction), and the upper via plug 620 may have a substantially constant horizontal area below the upper wiring layer 610 or may extend in the vertical direction (Z direction) toward the semiconductor substrate 110 while the horizontal area continues to decrease or increase.
In the process of forming the upper wiring layer 610 and the upper via plug 620, a portion of the upper barrier layer 630 covering the upper surface of the upper etch stop film 690 and the upper etch stop film 690 may be removed together, so that the upper surface of the upper wiring insulation layer 650 may be exposed.
To form the upper wiring layer 610 and the upper via plug 620, a process of removing a portion of the upper wiring material layer may be performed by a CMP method. In the process of forming the upper wiring layer 610 and the upper via plug 620, the upper etch stop film 690 may be completely removed.
The integrated circuit device 1a may include a device layer 120 including a plurality of semiconductor devices 150, a lower wiring structure 200, a reference wiring structure 300, and an upper wiring structure 600. The lower wiring structure 200 may be electrically connected to each semiconductor device 150 such that the lower wiring structure 200 may provide electrical connections between the plurality of semiconductor devices 150 and the reference wiring structure 300. The reference wiring structure 300 may provide an electrical connection between the lower wiring structure 200 and the upper wiring structure 600.
The upper wiring structure 600 may include an upper wiring layer 610 and an upper via plug 620 connected to the upper wiring layer 610. The upper wiring insulating layer 650 may fill a space between the upper wiring layer 610 and the upper via plug 620. In some embodiments, the upper wiring layer 610 and the upper via plug 620, which contact each other, may be integrally formed.
The upper wiring layer 610 may be formed in a plurality of line shapes extending in the first horizontal direction (X direction) in parallel with each other. The upper via plug 620 may extend from the bottom surface of the upper wiring layer 610 toward the semiconductor substrate 110 to be electrically connected to the reference wiring structure 300.
The upper wiring structure 600 may also include an upper barrier layer 630, the upper barrier layer 630 surrounding the bottom and side surfaces of the upper wiring layer 610 and the upper via plug 620. An upper barrier layer 630 may be disposed between (a) the upper wiring layer 610 and the upper via plug 620, and (b) the upper wiring insulation layer 650. In some embodiments, the upper wiring structure 600 may also include a lower capping layer 640 on an upper surface of the upper wiring layer 610 (e.g., covering the upper surface of the upper wiring layer 610).
All of the upper etch stop films 690 shown in fig. 11A to 15C may be removed, and thus may not remain on the upper wiring insulating layer 650 and the upper wiring structure 600.
Referring to fig. 11A to 15C together, the reference via plug 620 included in the integrated circuit device 1A according to the concept of the present invention may be FAV. The upper via plug 620 may be formed in a portion of the upper wiring insulation layer 650 corresponding to a portion where the third opening MO3 of the third mask layer MK3 and the fourth opening MO4 of the fourth mask layer MK4 overlap (i.e., a portion where the third mask split region MS3 and the fourth mask split region MS4 overlap).
Specifically, the upper via plug 620 may be aligned with a width in the second horizontal direction (Y-direction) of each of the third and fourth openings MO3 and MO4, and thus a width in the second horizontal direction (Y-direction) of the upper via plug 620 may be determined/controlled, and may also be aligned with a width in the first horizontal direction (X-direction) of a portion of the third and fourth openings MO3 and MO4 that overlap each other, that is, a portion of the third and fourth mask split regions MS3 and MS4 that overlap each other, and thus a width in the first horizontal direction (X-direction) of the upper via plug 620 may be determined/controlled.
Accordingly, since widths in the first horizontal direction (X direction) and the second horizontal direction (Y direction) perpendicular to each other can be limited, electrical reliability of the integrated circuit device 1a having the reference via plug 620 can be improved.
Fig. 16A to 16C show that the lower via plug 220 is SAV, and the reference via plug 320 and the upper via plug 620 are FAV, but not limited thereto. For example, when the integrated circuit device has a multilayer wiring structure, all of the via plugs of each of the wiring structures may be FAVs. Alternatively, for example, when the integrated circuit device has a multilayer wiring structure, the via plug of the at least one wiring structure located on the upper side may be an SAV, and the at least one wiring structure located on the lower side may be an FAV.
While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims (20)

1. A method of fabricating an integrated circuit device, the method comprising:
sequentially forming a device layer, a wiring insulating layer and a hard mask layer on a semiconductor substrate, wherein the device layer comprises a plurality of semiconductor devices;
sequentially removing a first region and a second region of the hard mask layer using a first mask layer having a first opening extending in a first horizontal direction and a second mask layer having a second opening extending in the first horizontal direction as an etching mask, respectively, wherein a portion of the second opening overlaps in a vertical direction with a split region including a first portion of the wiring insulating layer and overlaps in the vertical direction with a portion of the first opening;
forming a first wiring groove and a second wiring groove by removing the first portion of the wiring insulating layer using a third region of the hard mask layer remaining after removing the first region and the second region of the hard mask layer as an etching mask, the first wiring groove passing through the wiring insulating layer, the second wiring groove having a depth smaller than a depth of the first wiring groove; and
forming a wiring structure in the first and second wiring grooves and electrically connected to the plurality of semiconductor devices.
2. The method of manufacturing an integrated circuit device of claim 1,
wherein the first opening comprises a first cutting opening and a first extending opening, and the second opening comprises a second cutting opening and a second extending opening, and
wherein the first mask layer and the second mask layer are formed such that each of a portion of the first cutting opening adjacent to one end of the first cutting opening and a portion of the second cutting opening adjacent to one end of the second cutting opening overlaps the split region in the vertical direction.
3. The method of manufacturing an integrated circuit device of claim 2,
wherein the first mask layer and the second mask layer are formed such that center lines of each of the first cut opening and the second cut opening in the first horizontal direction are located on the same straight line on the wiring insulating layer.
4. The method of manufacturing an integrated circuit device according to claim 3,
wherein a width of each of the first and second cutting openings in a second horizontal direction perpendicular to the first horizontal direction has a same value.
5. The method of manufacturing an integrated circuit device of claim 2,
wherein the first mask layer and the second mask layer are formed such that the first extension opening and the second extension opening respectively overlap different portions of the wiring insulating layer.
6. The method of manufacturing an integrated circuit device of claim 1,
wherein the first wiring groove is formed in the split region of the wiring insulating layer.
7. The method of manufacturing an integrated circuit device according to claim 1, wherein the second wiring groove is formed in:
a second portion of the wiring insulating layer overlapping the first opening in the vertical direction outside the split area; and
a third portion of the wiring insulating layer overlapping with the second opening in the vertical direction outside the split area.
8. The method of manufacturing an integrated circuit device of claim 1,
wherein the hard mask layer comprises a first hard mask layer and a second hard mask layer stacked on the first hard mask layer,
wherein the split region further comprises a portion of the first hard mask layer and a first portion of the second hard mask layer overlapping the first portion of the wiring insulating layer in the vertical direction, and
wherein sequentially removing the first region and the second region of the hard mask layer comprises:
removing the first portion of the second hard mask layer using the first mask layer as an etch mask; and
removing a second portion of the second hard mask layer and the portion of the first hard mask layer using the second mask layer as an etch mask.
9. The method of manufacturing an integrated circuit device of claim 8, further comprising:
forming an etching stopper film between the wiring insulating layer and the hard mask layer, wherein the split region further includes a portion of the etching stopper film that overlaps with the first portion of the wiring insulating layer in the vertical direction; and
removing the portion of the etch stop film after sequentially removing the first region and the second region of the hard mask layer.
10. The method of manufacturing an integrated circuit device of claim 9,
wherein each of the first hard mask layer, the second hard mask layer, and the etch stop film comprises a different one of a metal nitride material, an oxynitride material, and a carbon-containing material.
11. A method of fabricating an integrated circuit device, the method comprising:
sequentially forming a device layer, a wiring insulating layer, an etching stop film and a hard mask layer on a semiconductor substrate, wherein the semiconductor substrate comprises a part positioned in a splicing area of an integrated circuit device, and the device layer comprises a plurality of semiconductor devices;
forming a first groove in the hard mask layer by removing a first region of the hard mask layer using a first mask layer having a first opening as an etch mask, the first opening having a portion located in the split region and extending in a first horizontal direction;
forming a second groove by removing a second region of the hard mask layer using a second mask layer having a second opening as an etching mask, the second opening having a portion located in the split region and extending in the first horizontal direction;
removing a first portion of the etch stop film in the stitching region;
removing a third region of the hard mask layer and a second portion of the etch stop film through the first groove, removing a fourth region of the hard mask layer and a third portion of the etch stop film through the second groove, and removing a portion of the upper first portion of the wiring insulating layer in the split region; and
forming a first wiring groove and forming a second wiring groove by removing a second portion of the wiring insulating layer using a fifth region of the hard mask layer remaining after removing the third region and the fourth region of the hard mask layer as an etching mask, the first wiring groove penetrating the wiring insulating layer in the split region, the second wiring groove having a depth smaller than a depth of the first wiring groove.
12. The method of fabricating an integrated circuit device of claim 11, further comprising:
forming a wiring material layer in the first wiring groove and the second wiring groove and on the etching stopper film and the wiring insulating layer; and
forming wiring structures in the first wiring groove and the second wiring groove by removing any remaining portion of the etch stop film and a portion of the wiring material layer on the wiring insulating layer, the wiring structures being electrically connected to the plurality of semiconductor devices,
wherein a first width of the wiring structure is controlled in the first horizontal direction and a second width of the wiring structure is controlled in a second horizontal direction perpendicular to the first horizontal direction by forming the first groove using the first mask layer having the first opening and forming the second groove using the second mask layer having the second opening.
13. The method of manufacturing an integrated circuit device of claim 12,
further comprising: an upper wiring insulating layer is formed on the wiring insulating layer and the wiring structure.
14. The method of manufacturing an integrated circuit device of claim 13,
wherein the upper wiring insulating layer is formed such that a lower surface of the upper wiring insulating layer contacts an upper surface of the wiring insulating layer.
15. The method of manufacturing an integrated circuit device of claim 11,
wherein the hard mask layer comprises a first hard mask layer and a second hard mask layer stacked on the first hard mask layer, an
Wherein the first recess is formed by removing the first region of the second hard mask layer using the first mask layer as an etch mask, and
wherein the second recess is formed by removing the second region of the second hard mask layer and a portion of the first hard mask layer located in the split region using the second mask layer as an etch mask.
16. The method of manufacturing an integrated circuit device of claim 15,
wherein the second groove is formed such that the first portion of the etch stop film in the split region is exposed through the second groove.
17. A method of fabricating an integrated circuit device, the method comprising:
sequentially forming a semiconductor substrate having a split region, a wiring insulating layer, an etching stopper film, a first hard mask layer and a second hard mask layer;
forming a first groove by removing a first region of the second hard mask layer using a first mask layer having a first opening extending in a first horizontal direction and having a portion located in the split region as an etching mask;
forming a second groove by removing a second region of the second hard mask layer and a first portion of the first hard mask layer located in the split region using a second mask layer having a second opening extending in the first horizontal direction and having a first portion located in the split region and a second portion different from the first opening as an etching mask;
removing a first portion of the etch stop film in the stitching region;
removing a second portion of the first hard mask layer and a second portion of the etch stop film through the first groove, removing a third portion of the first hard mask layer and a third portion of the etch stop film through the second groove, and removing a portion of the upper first portion of the wiring insulating layer located in the split region; and
forming a first wiring groove and a second wiring groove by removing a second portion of the wiring insulating layer using a fourth portion of the first hard mask layer as an etching mask, the first wiring groove passing through the wiring insulating layer, the second wiring groove having a depth smaller than that of the first wiring groove, wherein the first wiring groove is formed in the split region.
18. The method of manufacturing an integrated circuit device of claim 17,
wherein the first hard mask layer comprises a metal nitride material and the etch stop film comprises a carbon-containing material.
19. The method of manufacturing an integrated circuit device of claim 17, further comprising:
forming a wiring structure in the first wiring groove and the second wiring groove; and
an upper wiring insulating layer is formed on the wiring insulating layer and the wiring structure, the upper wiring insulating layer having a lower surface in contact with an upper surface of the wiring insulating layer.
20. The method of manufacturing an integrated circuit device of claim 19,
wherein forming the wiring structure includes removing any remaining portion of the etch stop film on the wiring insulating layer.
CN202010079164.3A 2019-04-17 2020-02-03 Method of manufacturing integrated circuit device Pending CN111834290A (en)

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