CN111831521A - Test method of interrupt response time, processor and electronic equipment - Google Patents
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
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- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
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Abstract
The application relates to the technical field of testing, and provides a method for testing interrupt response time, a processor and electronic equipment. The test method of the interrupt response time comprises the following steps: after the response of the processor to the interrupt to be tested is shielded, executing a preset test code, and acquiring the number of clock cycles consumed by executing the test code as a first number of cycles, wherein the test code comprises a trigger code for triggering the interrupt to be tested; enabling the processor to execute the test code after responding to the interrupt to be tested, responding and processing the interrupt to be tested before the test code is executed, and acquiring the number of clock cycles consumed by executing the test code as a second number of cycles; and calculating the difference value of the second period number minus the first period number, and calculating the response time of the processor to the interrupt to be detected according to the difference value. According to the technical scheme of the embodiment of the application, the response time of the processor to the interrupt to be tested can be calculated, and the processing capacity of the processor to the interrupt to be tested is measured.
Description
Technical Field
The present disclosure relates to the field of test technologies, and in particular, to a method for testing interrupt response time, a processor, and an electronic device.
Background
Interrupt is an important technology in computer development, and the occurrence of interrupt greatly frees a CPU and improves the execution efficiency of the CPU. The interruption means that when the CPU normally runs the program, the CPU interrupts the running program due to the prearrangement of the program or internal and external events, and then goes to the program with the interruption event.
The inventor finds that the prior art has at least the following problems: the response time of the CPU to the interrupt is the time from the response to the interrupt to the end of the interrupt, and the response time of the CPU to the interrupt can measure the processing capacity of the CPU to the interrupt, so that the method has important significance.
Disclosure of Invention
Some embodiments of the present application provide a method, a processor, and an electronic device for testing interrupt response time, which are capable of calculating the response time of the processor to an interrupt to be tested.
The embodiment of the application provides a method for testing interrupt response time, which is applied to a processor and comprises the following steps: after the response of the processor to the interrupt to be tested is shielded, executing a preset test code, and acquiring the number of clock cycles consumed by executing the test code as a first number of cycles, wherein the test code comprises a trigger code for triggering the interrupt to be tested; enabling the processor to execute the test code after responding to the interrupt to be tested, responding and processing the interrupt to be tested before the test code is executed, and acquiring the number of clock cycles consumed by executing the test code as a second number of cycles; and calculating the difference value of the second period number minus the first period number, and calculating the response time of the processor to the interrupt to be detected according to the difference value.
The embodiment of the application also provides a processor, wherein the processor is in communication connection with at least one memory; the memory stores instructions executable by the processor, and the instructions are executed by the processor to enable the processor to execute the method for testing the interrupt response time.
The embodiment of the application also provides electronic equipment which comprises the processor.
Compared with the prior art, the method and the device have the advantages that after the response of the processor to the interrupt to be tested is shielded, the preset test code is executed, the test code comprises a trigger code for triggering the interrupt to be tested, the processor is forbidden to respond to the interrupt to be tested when executing the trigger code, and after the test code is executed, the number of clock cycles consumed by the processor for executing the test code is obtained and serves as a first number of cycles; enabling the processor to respond to the interrupt to be tested, executing the test code again, responding and processing the terminal to be tested before the test code is executed, and acquiring the number of clock cycles consumed by the processor for executing the test code as a second number of cycles; the response of the processor to the interrupt to be tested is enabled to execute the clock cycles which are consumed more by the test code than the response of the shielding processor to the interrupt to be tested, so that the difference value of the second cycle minus the first cycle is the clock cycles consumed by the processor to respond to the interrupt to be tested, the response time of the processor to the interrupt to be tested can be calculated according to the difference value, and the processing capacity of the processor to the interrupt to be tested is measured.
In addition, acquiring the number of clock cycles consumed by executing the test code specifically includes: the number of clock cycles consumed to execute the test code is obtained by a timer of the same clock cycle as the processor. In this embodiment, since the clock cycles of the timer and the processor are the same, the clock cycles of the timer and the processor are aligned, and the timer having the same clock cycle as the processor is used to obtain the number of clock cycles consumed by the processor to execute the test code, so that the calculated response time of the processor to the interrupt to be tested can be accurate to the clock cycle of the processor, and the accuracy is high.
In addition, the processor and the timer have the same clock source. In this embodiment, the processor and the timer have the same clock source to ensure that the clock periods of the processor and the timer are the same.
In addition, acquiring the number of clock cycles consumed by executing the test code through a timer of the same clock cycle as the processor includes: when the test code is started to be executed, recording the current clock period as a first clock period through a timer; executing the test code, and recording the current clock cycle as a second clock cycle again through the timer when the test code is executed; and subtracting the first clock period from the second clock period to obtain the number of the clock periods consumed by executing the test code. The embodiment provides a specific implementation mode for acquiring the number of clock cycles consumed by executing the test code through a timer with the same clock cycle as that of the processor.
In addition, when executing the trigger code, the processor sends a first trigger signal to a module corresponding to the interrupt to be detected in the processor, and after detecting an interrupt mark generated by the module, the processor executes the interrupt code corresponding to the interrupt to be detected; the module generates an interrupt flag when receiving a first trigger signal. The present embodiments provide a way to trigger an interrupt to be tested by the processor software.
In addition, when the processor executes the trigger code, the processor sends a second trigger signal to a pin of the peripheral corresponding to the interrupt to be detected, and responds to the interrupt to be detected generated by the peripheral. The embodiment provides a mode for triggering the interrupt to be tested through peripheral hardware.
In addition, the second trigger signal is a trigger level signal of the interrupt to be detected.
In addition, the test code is code written based on the C language. In the embodiment, the test codes are written by using the C language, so that the test codes are simpler and more universal, and the test difficulty is simplified.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a flow chart of a method of testing interrupt response time according to a first embodiment of the present application;
FIG. 2 is a flow chart of a method of testing interrupt response time according to a second embodiment of the present application;
FIG. 3 is a diagram of a processor coupled to a memory according to a fourth embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, some embodiments of the present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
A first embodiment of the present application relates to a method for testing interrupt response time, which is used to test the response time of a processor to an interrupt to be tested, where the processor may be a Central Processing Unit (CPU) or a microprocessor.
The specific flow of the interrupt response time testing method in this embodiment is shown in fig. 1.
Specifically, after the response of the processor to the interrupt to be tested is shielded, a preset test code is executed, the test code comprises a fixed operation code and a trigger code used for triggering the interrupt to be tested, the fixed operation code is executed by the processor firstly when the test code is executed, when the trigger code is executed, the processor prohibits the response to the interrupt to be tested due to the shielding of the response to the interrupt to be tested, the fixed operation code is continuously executed, after the execution of the fixed operation code is finished, the execution of the whole test code is finished, and the number of clock cycles consumed by the processor for executing the test code is obtained as a first number of cycles.
In one example, the test code is code written based on the C language. The test code is written by using the C language, so that the method is simpler and more universal, and the test difficulty is simplified.
And 102, executing the test code after enabling the processor to respond to the interrupt to be tested, responding to and processing the interrupt to be tested before the test code is executed, and acquiring the number of clock cycles consumed for executing the test code as a second number of cycles.
Specifically, after the response of the processor to the interrupt to be tested is enabled, the test code is executed; the processor executes a fixed operation code first, responds to the interrupt to be tested when a trigger code for triggering the interrupt to be tested is executed, stops executing the fixed operation code, continues to execute the fixed operation code after the interrupt to be tested is processed, and acquires the number of clock cycles consumed by the processor to execute the test code as a second number of cycles after the fixed operation code is executed and the whole test code is executed. When the processor executes a trigger code for triggering the interrupt to be tested, a time interval for generating the interrupt to be tested exists, then the interrupt to be tested is responded, and in the time interval, the processor can continue to execute the fixed operation code.
And 103, calculating a difference value obtained by subtracting the first cycle number from the second cycle number, and calculating the response time of the processor to the interrupt to be detected according to the difference value.
Specifically, as can be seen from the above, the first period number includes a number of clock cycles consumed by the processor to execute the test code, and the second period number includes a number of clock cycles consumed by the processor to execute the test code and a time of the processor responding to the interrupt to be tested, so that a difference value obtained by subtracting the first period number from the second period number is a number of time cycles consumed by the processor responding to the interrupt to be tested, and the difference value is multiplied by a unit time length of the clock cycle, so that the response time of the processor to the interrupt to be tested can be calculated.
Compared with the prior art, the method and the device have the advantages that after the response of the processor to the interrupt to be tested is shielded, the preset test code is executed, the test code comprises a trigger code for triggering the interrupt to be tested, the processor is forbidden to respond to the interrupt to be tested when executing the trigger code, and after the test code is executed, the number of clock cycles consumed by the processor for executing the test code is obtained and serves as a first number of cycles; enabling the processor to respond to the interrupt to be tested, executing the test code again, responding and processing the terminal to be tested before the test code is executed, and acquiring the number of clock cycles consumed by the processor for executing the test code as a second number of cycles; the response of the processor to the interrupt to be tested is enabled to execute the clock cycles which are consumed more by the test code than the response of the shielding processor to the interrupt to be tested, so that the difference value of the second cycle minus the first cycle is the clock cycles consumed by the processor to respond to the interrupt to be tested, the response time of the processor to the interrupt to be tested can be calculated according to the difference value, and the processing capacity of the processor to the interrupt to be tested is measured.
The second embodiment of the present application relates to a method for testing interrupt response time, and the second embodiment is an improvement on the first embodiment, and the main improvement is that in the second embodiment, the accuracy of the calculated response time of the processor to the interrupt to be tested is improved.
The specific flow of the interrupt response time testing method in this embodiment is shown in fig. 2.
Specifically, after the response of the processor to the interrupt to be tested is shielded, executing a preset test code, wherein the test code comprises a fixed operation code and a trigger code for triggering the interrupt to be tested, and recording the current clock cycle as a first clock cycle through a timer with the same clock cycle as the processor when the processor starts to execute the test code; the processor executes the fixed operation code first, when the trigger code for triggering the interrupt to be tested is executed, the processor forbids to respond to the interrupt to be tested because the response of the trigger code to the interrupt to be tested is shielded, the fixed operation code is continuously executed, after the execution of the fixed operation code is finished, the whole test code is executed, the current clock period is recorded as a second clock period again through a timer with the same clock period as the processor, the first clock period is subtracted from the second clock period, and the number of clock periods consumed for executing the test code, namely the number of first periods in the step, is obtained.
Specifically, after the response of the processor to the interrupt to be tested is enabled, the test code is executed, and when the processor starts to execute the test code, the current clock cycle is recorded as a first clock cycle through a timer with the same clock cycle as the processor; the processor executes a fixed operation code first, responds to the interrupt to be tested when executing the trigger code for triggering the interrupt to be tested, stops executing the fixed operation code, continues to execute the fixed operation code after processing the interrupt to be tested, finishes executing the whole test code after the fixed operation code is executed, records the current clock period as a second clock period again through a timer with the same clock period as the processor, and subtracts the first clock period from the second clock period to obtain the number of clock periods consumed by executing the test code, namely the number of the second periods in the step.
Specifically, as can be seen from the above, the first period number includes a number of clock cycles consumed by the processor to execute the test code, and the second period number includes a number of clock cycles consumed by the processor to execute the test code and a time of the processor responding to the interrupt to be tested, so that a difference value obtained by subtracting the first period number from the second period number is a number of time cycles consumed by the processor responding to the interrupt to be tested, and the difference value is multiplied by a unit time length of the clock cycle, so that the response time of the processor to the interrupt to be tested can be calculated.
In this embodiment, the timer may be set to zero when the processor starts to execute the test code, and the current clock cycle is recorded by the timer when the processor finishes executing the test code, so that the current clock cycle recorded by the timer may be directly used as the number of clock cycles consumed by the processor to execute the test code.
Compared with the first embodiment, the clock cycles of the timer and the processor are the same, so that the clock cycles of the timer and the processor are aligned, and the clock cycles consumed by the processor for executing the test code are acquired by using the timer with the same clock cycle as the processor, so that the calculated response time of the processor to the interrupt to be tested can be accurate to the clock cycle of the processor, and the accuracy is high.
A third embodiment of the present application relates to a method for testing interrupt response time, and is substantially the same as the first embodiment except that: a manner is provided by which a processor triggers an interrupt to be tested after executing a trigger code for triggering the interrupt to be tested.
In this embodiment, two ways for triggering the interrupt to be tested after the processor executes the trigger code for triggering the interrupt to be tested include, specifically, the following, where the response of the processor to the interrupt to be tested is enabled.
In the first mode, the interrupt to be tested is triggered by software of a software processor.
When the processor executes a trigger code used for triggering the interrupt to be tested in the test code, sending a first trigger signal to a module corresponding to the interrupt to be tested in the processor, generating an interrupt mark when the module receives the first trigger signal, executing the interrupt code corresponding to the interrupt to be tested after the processor detects the interrupt mark, stopping executing the test code, and continuing to execute the test code after the interrupt code is executed.
And in the second mode, the interrupt to be tested is triggered through peripheral hardware.
When the processor executes a trigger code which is used for triggering the interrupt to be tested in the test code, a second trigger signal is sent to a pin of the peripheral corresponding to the interrupt to be tested, the peripheral generates the interrupt to be tested, the processor responds to the interrupt to be tested and stops executing the test code, after the interrupt process to be tested is finished, the peripheral returns a completion signal to the processor, and the processor continues executing the test code. The second trigger signal may be a trigger level signal of the interrupt to be detected.
Compared with the first embodiment, the present embodiment provides a way for triggering an interrupt to be tested after a processor executes a trigger code for triggering the interrupt to be tested.
A fourth embodiment of the present application relates to a processor, which may be a Central Processing Unit (CPU) or a microprocessor, as shown in fig. 3, where the processor 1 is connected to at least one memory 2, the memory 2 stores instructions executable by the processor 1, and the instructions are executed by the processor 1, so that the processor 1 can execute the above method embodiments.
A fifth embodiment of the present application relates to an electronic device including the processor described above.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice.
Claims (10)
1. A method for testing interrupt response time is applied to a processor, and comprises the following steps:
after the response of the processor to the interrupt to be tested is shielded, executing a preset test code, and acquiring the number of clock cycles consumed by executing the test code as a first number of cycles, wherein the test code comprises a trigger code for triggering the interrupt to be tested;
enabling the processor to respond to the interrupt to be tested, executing the test code, responding to and processing the interrupt to be tested before the test code is executed, and acquiring the number of clock cycles consumed by executing the test code as a second number of cycles;
and calculating the difference value of subtracting the first period number from the second period number, and calculating the response time of the processor to the interrupt to be detected according to the difference value.
2. The method for testing interrupt response time according to claim 1, wherein the obtaining the number of clock cycles consumed for executing the test code includes:
acquiring the number of clock cycles consumed for executing the test code through a timer with the same clock cycle as the processor.
3. The method for testing interrupt response time of claim 2, wherein said processor and said timer have the same clock source.
4. The method for testing interrupt response time of claim 2, wherein said obtaining the number of clock cycles consumed by executing said test code by a timer of the same clock cycle as said processor comprises:
recording a current clock cycle as a first clock cycle through the timer when the test code starts to be executed;
executing the test code, and recording the current clock cycle as a second clock cycle again through the timer when the test code is executed;
and subtracting the first clock period from the second clock period to obtain the number of clock periods consumed by executing the test code.
5. The method for testing interrupt response time according to claim 1, wherein the processor sends a first trigger signal to a module corresponding to the interrupt to be tested in the processor when executing the trigger code, and the processor executes the interrupt code corresponding to the interrupt to be tested after detecting an interrupt flag generated by the module; wherein the module generates the interrupt flag upon receiving the first trigger signal.
6. The method for testing interrupt response time according to claim 1, wherein the processor sends a second trigger signal to a pin of the peripheral corresponding to the interrupt to be tested when executing the trigger code, in response to the interrupt to be tested generated by the peripheral.
7. The method for testing interrupt response time of claim 6, wherein the second trigger signal is a trigger level signal of the interrupt to be tested.
8. The method for testing interrupt response time of claim 1, wherein the test code is a code written based on C language.
9. A processor, wherein the processor is communicatively coupled to at least one memory; wherein,
the memory stores instructions executable by the processor to enable the processor to perform a method of testing interrupt response times as claimed in any one of claims 1 to 8.
10. An electronic device comprising the processor of claim 9.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6167479A (en) * | 1998-08-03 | 2000-12-26 | Unisys Corporation | System and method for testing interrupt processing logic within an instruction processor |
| CN101551777A (en) * | 2009-05-08 | 2009-10-07 | 刘志方 | Apparatus of mobile terminal software base on abnormity and interrupt mechanism and test method |
| US20110239070A1 (en) * | 2010-03-26 | 2011-09-29 | Morrison Gary R | Method and apparatus for testing a data processing system |
| JP2016045804A (en) * | 2014-08-25 | 2016-04-04 | キヤノン株式会社 | Interrupt controller and electronic device |
| CN106201802A (en) * | 2016-07-20 | 2016-12-07 | 中国航空工业集团公司航空动力控制系统研究所 | The CPU internal interrupt response time of logic-based analyser and the measuring method of recovery time |
| CN107038109A (en) * | 2016-02-03 | 2017-08-11 | 龙芯中科技术有限公司 | Interruption delay method of testing and device based on MIPS frameworks |
| CN107665159A (en) * | 2016-07-27 | 2018-02-06 | 上海华虹集成电路有限责任公司 | The method of testing for performing the time is fixed in safe processor jump instruction |
-
2019
- 2019-04-18 CN CN201910313946.6A patent/CN111831521B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6167479A (en) * | 1998-08-03 | 2000-12-26 | Unisys Corporation | System and method for testing interrupt processing logic within an instruction processor |
| CN101551777A (en) * | 2009-05-08 | 2009-10-07 | 刘志方 | Apparatus of mobile terminal software base on abnormity and interrupt mechanism and test method |
| US20110239070A1 (en) * | 2010-03-26 | 2011-09-29 | Morrison Gary R | Method and apparatus for testing a data processing system |
| JP2016045804A (en) * | 2014-08-25 | 2016-04-04 | キヤノン株式会社 | Interrupt controller and electronic device |
| CN107038109A (en) * | 2016-02-03 | 2017-08-11 | 龙芯中科技术有限公司 | Interruption delay method of testing and device based on MIPS frameworks |
| CN106201802A (en) * | 2016-07-20 | 2016-12-07 | 中国航空工业集团公司航空动力控制系统研究所 | The CPU internal interrupt response time of logic-based analyser and the measuring method of recovery time |
| CN107665159A (en) * | 2016-07-27 | 2018-02-06 | 上海华虹集成电路有限责任公司 | The method of testing for performing the time is fixed in safe processor jump instruction |
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