CN111816658B - Memory and forming method thereof - Google Patents

Memory and forming method thereof Download PDF

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Publication number
CN111816658B
CN111816658B CN201910283488.6A CN201910283488A CN111816658B CN 111816658 B CN111816658 B CN 111816658B CN 201910283488 A CN201910283488 A CN 201910283488A CN 111816658 B CN111816658 B CN 111816658B
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active region
sub
isolation structure
substrate
memory
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CN111816658A (en
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不公告发明人
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Abstract

A memory and a forming method thereof are provided, the forming method of the memory comprises the following steps: providing a substrate; forming a plurality of first grooves in the substrate, wherein the substrate between the adjacent first grooves is an active region, and the width of the top of each first groove is smaller than that of the bottom of each first groove; forming a first isolation structure in the first trench, wherein part of the first isolation structure is supported below the edge of the active region; forming a plurality of second grooves in the substrate, wherein the second grooves divide the active region into a plurality of sub-active regions and suspend the sub-active regions; and filling a second isolation structure in the second groove, wherein the second isolation structure is transversely connected with the first isolation structure and surrounds the side wall and the bottom of the sub-active region. The method can reduce the electric leakage of the memory.

Description

Memory and forming method thereof
Technical Field
The invention relates to the technical field of memories, in particular to a memory and a forming method thereof.
Background
A Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device, which is composed of many repetitive memory cells. Each memory cell typically includes a capacitor and a transistor; the grid electrode of the transistor is connected with a word line, the source electrode of the transistor is connected with a capacitor, the drain electrode of the transistor is connected with a bit line, a voltage signal on the word line can control the transistor to be turned on or turned off, and then data information stored in the capacitor is read through the bit line or written into the capacitor through the bit line for storage. Data information is stored in capacitors in the form of charges, typically representing a "0" with no charge and a "1" with charge, or vice versa.
Typically, there is a leakage current between the source and the substrate, resulting in the loss of charge stored on the capacitor. Leakage current can cause the data information stored by the capacitor to be lost; leakage current flowing along the substrate to adjacent memory cells can also cause charge transfer between the capacitors of adjacent memory cells, resulting in data errors.
Therefore, how to improve the current leakage problem of the conventional memory is a problem to be solved urgently.
Disclosure of Invention
The technical problem to be solved by the invention is how to reduce the leakage current of the memory.
In order to solve the above problems, the present invention provides a method for forming a memory, including: providing a substrate; forming a plurality of first grooves in the substrate, wherein the substrate between the adjacent first grooves is an active region, and the width of the top of each first groove is smaller than that of the bottom of each first groove; forming a first isolation structure in the first trench, wherein part of the first isolation structure is supported below the edge of the active region; forming a plurality of second grooves in the substrate, wherein the second grooves divide the active region into a plurality of sub-active regions and suspend the sub-active regions; and filling a second isolation structure in the second groove, wherein the second isolation structure is transversely connected with the first isolation structure and surrounds the side wall and the bottom of the sub-active region.
Optionally, the first trench has a sloped sidewall or a stepped sidewall.
Optionally, the forming method of the first trench includes: etching the substrate to form a plurality of first upper grooves, wherein an active region is arranged between every two adjacent first upper grooves; forming a side wall on the side wall of the active region; and continuously etching the substrate along the first upper groove to form a first lower groove communicated with the first upper groove, wherein the first lower groove is partially positioned below the edges of the active regions at two sides.
Optionally, the substrate is etched by an isotropic etching process to form the first lower trench.
Optionally, the forming method of the second trench includes: etching the substrate to form a plurality of second upper grooves, wherein the second upper grooves divide the active region into a plurality of sub active regions; forming a side wall on the side wall of the sub-active region; and continuously etching the substrate along the second upper groove, removing part of substrate material below the sub-active region, and forming a second lower groove communicated with the second upper groove.
Optionally, the substrate is etched by an isotropic etching process to form the second lower trench.
Optionally, the isotropic etching process is a wet etching process.
Optionally, the first trench extends along a length direction of the sub-active region.
Optionally, the method further includes: an access transistor is formed within the sub-active region.
Optionally, the access transistor includes two gate structures buried in the sub-active region, a drain located between adjacent gate structures, and a source located outside the gate structures.
In order to solve the above problem, the technical solution of the present invention further provides a memory, including: a plurality of sub-active regions; an isolation structure surrounding sidewalls and a bottom of the sub-active region, the isolation structure including a first isolation structure and a second isolation structure that are laterally connected.
Optionally, the top width of the first isolation structure is smaller than the bottom width.
Optionally, a portion of the first isolation structure is supported below an edge of the sub-active region.
Optionally, a portion of the second isolation structure is located below the bottom of the sub-active region.
Optionally, the first isolation structure has a sloped sidewall or a stepped sidewall.
Optionally, the first isolation structure extends along a length direction of the sub-active region.
Optionally, the method further includes: the access transistor is positioned in each sub-active area, and the capacitor is positioned above the sub-active area and connected with the source electrode of the access transistor.
Optionally, the access transistor includes two gate structures buried in the sub-active region, a drain located between adjacent gate structures, and a source located outside the gate structures.
The forming method of the memory of the invention supports the active region by forming the first isolation structure partially positioned below the edge of the active region; then, hollowing the lower part of the active region through a second groove, and forming a second isolation structure in the second groove; and enabling the first isolation structure and the second isolation structure to comprise the side wall and the bottom of the sub-active region, so that electrons in the active region cannot migrate outwards, thereby reducing the leakage current of the memory unit formed in the sub-active region and reducing the leakage current of the formed memory.
In the memory, the bottom and the side wall of each sub active region forming the memory unit are surrounded by the isolation structure, and electrons in the sub active regions cannot migrate outwards, so that the leakage current of the formed memory can be reduced, and the performance of the memory is improved.
Drawings
Referring to fig. 1A to 8, schematic structural diagrams of a memory formation process according to an embodiment of the invention are shown.
Detailed Description
The following describes in detail a specific embodiment of the memory and the forming method thereof according to the present invention with reference to the accompanying drawings.
Please refer to fig. 1 to 8, which are schematic structural diagrams illustrating a memory formation process according to an embodiment of the invention.
Firstly, providing a substrate, forming a plurality of first grooves in the substrate, wherein the substrate between the adjacent first grooves is an active region, and the width of the top of each first groove is smaller than that of the bottom of each first groove.
In this embodiment, please refer to fig. 1 to 3 for a method for forming the first trench.
Referring to fig. 1A to 1B, a substrate 100 is provided; the substrate 100 is etched to form a plurality of first upper trenches 102a, and an active region 101 is formed between adjacent first upper trenches 102 a. FIG. 1B is a schematic sectional view taken along the cut line AA' in FIG. 1A.
The semiconductor substrate 100 may be a single crystal silicon substrate, a single crystal germanium substrate, a germanium-silicon substrate, or the like. A doped well may be formed within the substrate 100.
The substrate 100 is etched by a dry etching process, and a plurality of first upper trenches 102a are formed in the substrate 100. In this embodiment, the first upper trenches 102a are arranged in parallel, and specifically, extend along the length direction of the active region 101. The first upper trench 102a divides an upper portion of the substrate 100 into a plurality of elongated active regions 101.
In this embodiment, the first upper trench 102a extends along the length direction (x direction) of the active region 101, and then divides the active region 101 along the y direction, so that the width of the sub-active region formed after the active region 101 is divided is consistent with the width of the active region 101. The first isolation structure formed subsequently has larger supporting area for the active region and better supporting effect.
In other specific embodiments, the first upper trench may also be disposed along the y direction, and the active region is subsequently divided along the x direction, so that the length of the sub-active region formed after the active region is divided is consistent with the width of the active region.
Referring to fig. 2A and 2B, a sidewall 201 is formed on the sidewall of the active region 101, and fig. 2B is a schematic cross-sectional view along a cut line AA' in fig. 2A.
The forming method of the side wall 201 comprises the following steps: forming a side wall material layer covering the active region 101 and the inner wall of the first upper groove 102 a; and etching the whole side wall material layer by adopting an anisotropic etching process along a direction vertical to the surface of the substrate 100 without forming a mask layer on the surface of the side wall material layer by adopting a maskless etching process, wherein the side wall material layer positioned on the top surface of the active region 101 and at the bottom of the first upper groove 102a can be removed due to the directionality of the etching process, and part of the side wall material layer covering the active region 101 is reserved as the side wall 201. The anisotropic etching process may be a plasma etching process.
The material of the sidewall 201 may be insulating dielectric material such as silicon oxide, silicon nitride, etc., and is used to protect the active region 101.
Referring to fig. 3A, the substrate 100 is etched along the first upper trench 102a to form a first lower trench 102b communicated with the first upper trench 102a, and the first lower trench 102b is partially located below the edges of the active regions 101 on both sides.
In this embodiment, a wet etching process or a dry etching process may be used to etch the substrate 100 below the first upper trench 102a, and the substrate 100 is etched in a direction perpendicular to the substrate 100 and at the same time, the substrate 100 is laterally etched, so that the width of the first lower trench 102b is greater than the width of the first upper trench 102a, and two sides of the first lower trench 102b are located below the edge of the active region 101.
In fig. 3A, the first lower trench 102b is only an example, and does not represent the profile of the first lower trench 102b formed in the actual process. Since the etching rate in each crystal direction may be the same or different during the etching process, the bottom of the first lower trench 102b may have a horizontal bottom surface, an arc-shaped bottom surface, and the like, and the cross section of the first lower trench 102b may be an ellipse, a semicircle, a rounded rectangle, a polygon, or other shapes, which may vary according to the selected etching process.
The etching process may be a dry etching process or a wet etching process.
In a specific embodiment, the substrate 100 is etched by a wet etching process, and an etching solution used in the wet etching process is an alkaline solution such as KOH or tetramethylammonium hydroxide. In a specific embodiment, the wet etching process may use a solution for performing isotropic etching on the substrate 100 to perform isotropic etching on the substrate 100, so that the substrate 100 has the same etching rate in each direction, the formed first lower trench 102b has a better morphology, the width of the first lower trench 102b is easier to control, and the dimension below the active region 101 can be accurately controlled.
In another embodiment, the substrate 100 is etched using a dry etching process. The dry etching process may be an isotropic etching process, and the substrate 100 is etched by using an etching gas, and the substrate 100 is etched by performing a chemical reaction between etching gas molecules or ions and a material of the substrate 100. In one embodiment, the etching gas may comprise a fluorine-or chlorine-containing gas, such as XeF2、CHF3、CF4、CCl4At least one of the etching gases can be used for directly reacting with the substrate 100 by natural diffusion and adsorption to etch the substrate 100Etching gas can be ionized, and ions such as F or Cl capable of reacting with the substrate 100 at the ionized position can improve the etching efficiency of the substrate 100 due to the higher energy of the reactive ions.
In another specific embodiment, the method for forming the first lower trench 102b may further include: vertically etching the substrate 100 along the first upper trench 102a by using an anisotropic etching process to expose a part of the substrate sidewall below the active region 101; and then, carrying out lateral etching on the substrate, and removing part of substrate material below the edge of the active region 101 to form the first lower trench 102 b.
The first lower trench 102b and the first upper trench 102a communicate with each other, and together form a first trench 102 having a stepped sidewall, with a projecting portion of the step being located below the edge of the active region 101.
In another embodiment, referring to fig. 3B, a first trench 102' having a sloped sidewall may also be formed. The concentration or energy of etching gas can be gradually adjusted in the etching process directly through a single etching process, the lateral etching rate of the substrate 100 in the etching process is improved, and the first trench 102 'having an inclined sidewall and a bottom width greater than a top width is directly formed, wherein the first trench 102' is partially located below the edge of the active region 101 and is located in the projection of the active region 101 on the plane of the substrate 100.
Referring to fig. 4A and 4B, a first isolation structure 401 is formed in the first trench 102, and a portion of the first isolation structure 401 is supported under the edge of the active region 101. FIG. 4B is a schematic sectional view taken along the cut line AA' in FIG. 4A.
In this embodiment, before forming the first isolation structure 401, the sidewall spacers 201 are removed.
An isolation material may be deposited in the first trench 102 by a chemical vapor deposition process, followed by planarization to form a first isolation structure 401 located in the first trench 102. The first isolation structure is made of insulating dielectric materials such as silicon oxide, silicon oxynitride, silicon oxycarbide and the like, and serves as an isolation structure between adjacent active regions 101.
Since the first trench 102 is partially located below the edge of the active region 101, the first isolation structure 401 formed in the first trench 102 is partially located below the active region 101, and can support the active region 101.
The width of the part of the first isolation structure 401 located below the active region 101 cannot be too small, so that the active region 101 is prevented from collapsing due to the fact that the first isolation structure 401 cannot support the active region 101 sufficiently after a substrate material located below the active region 101 and between adjacent first isolation structures 401 is hollowed out. On the principle that the active region 101 does not collapse in the subsequent process, the width of the first lower trench 102b is adjusted, so as to adjust the width of a portion of the first isolation structure 401 located below the active region 101. In one embodiment, the maximum width of a single side of the first isolation structure 401 under the active region 101 is 1/5-1/3 of the maximum width of the active region 101.
After the first isolation structure 401 is formed, a plurality of second trenches are formed in the substrate, and the second trenches divide the active region into a plurality of sub-active regions and suspend the sub-active regions.
Referring to fig. 5A to 5D, the substrate 100 is etched to form a plurality of second upper trenches 501a, and the second upper trenches 501a divide the active region 101 (see fig. 4A) into a plurality of sub active regions 502. Fig. 5B is a schematic cross-sectional view taken along a cut line BB 'in fig. 5A, fig. 5C is a schematic cross-sectional view taken along a cut line CC' in fig. 5A, fig. 5D is a schematic cross-sectional view taken along a cut line DD 'in fig. 5A, and fig. 5E is a schematic cross-sectional view taken along a cut line EE' in fig. 5A.
The method for forming the second upper trench 501a includes: forming a patterned mask layer on the surfaces of the active region 101 and the first isolation structure 401, wherein the patterned mask layer has a plurality of openings, the opening pattern intersects with the active region 101, and a part of the active region 101 and the first isolation structure 401 are exposed; the active region 101 is etched along the opening to form a second upper trench 501 a.
In this embodiment, the extending direction of the opening is perpendicular to the length direction of the active region 101; in other embodiments, the extending direction of the opening may also form other angles with the length direction of the active region 101.
Due to the fact that the active region 101 and the first isolation structure 401 are made of different materials, an etching process with high etching selectivity to the active region 101 can be adopted to etch the active region 101. The active region 101 may be etched by a wet or dry etching process to form the second upper trench 501a, and then the patterned mask layer is removed.
The second upper trench 501a divides the active region 101 into sub-active regions 502, forming an array of sub-active regions 502 on the substrate 100.
Referring to fig. 6A to 6D, a sidewall 601 is formed on the sidewall of the sub-active region 502; the substrate 100 is continuously etched along the second upper trench 501a, and a portion of the substrate material under the sub-active region 502 is removed, so as to form a second lower trench 501b communicated with the second upper trench 501 a. Fig. 6A to 6D correspond to the schematic cross-sectional views of fig. 5B to 5E, respectively.
The material of the sidewall 601 may be a dielectric material such as silicon oxide, silicon nitride, or the like. The forming method of the side wall 601 comprises the following steps: forming a side wall material layer covering the sub-active region 502, the first isolation structure 401 and the inner wall of the second upper trench 501 a; and etching the side wall material layer along the direction vertical to the surface of the substrate 100, removing the side wall material layer positioned at the top of the sub-active region 502 and the first isolation structure 401 and at the top of the second upper groove 501a, forming a side wall 601 covering the side walls of the active region 502 at two sides of the second upper groove 501a, wherein the side wall 601 also covers the side walls of the first isolation structure 401 at two sides of the second upper groove 501 a. The side walls 601 protect the side walls of the sub-active regions 502 during the subsequent etching process to form the second lower trenches 501 b.
The substrate 100 may be etched using a dry or wet etching process to form the second lower trench 501 b. The substrate material at the bottom of the sub-active region 502 is removed by etching the substrate 100 laterally while etching the substrate 100 vertically.
In a specific embodiment, the substrate 100 is etched by a wet etching process, and an etching solution used in the wet etching process is an alkaline solution such as KOH or tetramethylammonium hydroxide. In another embodiment, the substrate 100 is etched using a dry etching process. The dry etching process may be an isotropic etching process, and the substrate 100 is etched by using an etching gas, and the substrate 100 is etched by performing a chemical reaction between etching gas molecules or ions and a material of the substrate 100. In one embodiment, the etching gas may comprise a fluorine-or chlorine-containing gas, such as XeF2、CHF3、CF4、CCl4At least one of the etching gases can be used for etching the substrate 100 by directly reacting with the substrate 100 through natural diffusion and adsorption, and can also be used for ionizing the etching gas, ions such as F or Cl and the like can react with the substrate 100 at the ionization position, and the etching efficiency of the substrate 100 can be improved due to the higher energy of the reactive ions.
In another specific embodiment, the method for forming the second lower trench 501b may further include: vertically etching the substrate 100 along the first lower trench 501a by using an anisotropic etching process to expose a part of the substrate sidewall below the active region 101; then, the substrate 100 is laterally etched to remove a portion of the substrate material under the sub-active region 502, so that the bottom of the sub-active region 502 is suspended above the second lower trench 501 b. The second lower groove 501b and the second upper groove 501a communicate with each other to form a second groove 501.
Referring to fig. 6C, in the process of forming the second lower trench 501b, the first isolation structure 401 located under the edge of the sub-active region 502 supports the sub-active region 502, so as to prevent the sub-active region 502 from collapsing.
Referring to fig. 7A to 7E, a second isolation structure 701 is filled in the second trench 501, and the second isolation structure is laterally connected to the first isolation structure 401 to surround the sidewall and the bottom of the sub-active region 502. Fig. 7B is a schematic sectional view taken along a cut line BB 'in fig. 7A, fig. 7C is a schematic sectional view taken along a cut line CC' in fig. 7A, fig. 7D is a schematic sectional view taken along a cut line DD 'in fig. 7A, and fig. 7E is a schematic sectional view taken along a cut line EE' in fig. 7A.
In this embodiment, before forming the second isolation structure 701, the sidewall 601 is removed.
After depositing an isolation material in the second trench 501 by a chemical vapor deposition process, planarization is performed to form a second isolation structure 701 in the second trench 501. The second isolation structure 701 is made of insulating dielectric materials such as silicon oxide, silicon oxynitride, silicon oxycarbide, and the like, and is used as an isolation structure between adjacent sub-active regions 701.
The second isolation structure 701 is partially located in front of the adjacent sub-active regions 502, partially located below the sub-active regions 502, and laterally connected to the first isolation structure 401, so as to surround the sidewalls and the bottom of each sub-active region 502 and isolate the sidewalls and the bottom from the underlying substrate material. Thus, after the memory cell is formed on the sub-active region 502, carriers cannot migrate outward through the substrate, thereby reducing leakage current.
In addition, in this embodiment, the depths of the first trench and the second trench may be adjusted to make the sub-active region 502 have a sufficient thickness for forming a DRAM memory, without reducing the channel length of a DRAM memory cell, thereby maintaining the original characteristics of the DRAM.
Referring to fig. 8, an access transistor 800 is formed within the sub-active region 502.
The access transistor 800 includes two gate structures buried within the sub-active region 502, a drain 803 between adjacent gate structures, and a source 804 outside the gate structures. The gate structure comprises a gate 801 embedded in a sub-active region 502 and a gate dielectric layer 802 positioned between the gate 801 and the active region 502. A gate isolation layer 805 is also formed on top of the gate 801.
In this embodiment, the access transistor is a buried gate transistor structure. The access transistor may also be other transistor structures such as a planar gate type transistor or a gate all around type transistor.
The following also includes forming a capacitor over the sub-active region 501 connected to the source 803. Because the bottom and the side wall of the sub-active region 501 are both surrounded by the first isolation structure 401 and the second isolation structure 701, electrons in the sub-active region 501 cannot migrate outwards, so that the leakage current of the formed memory can be reduced, and the performance of the memory can be improved.
The invention further provides a memory according to the specific implementation mode.
Referring to fig. 7A to 7E and fig. 8, fig. 7B is a schematic cross-sectional view taken along a cut line BB 'in fig. 7A, fig. 7C is a schematic cross-sectional view taken along a cut line CC' in fig. 7A, fig. 7D is a schematic cross-sectional view taken along a cut line DD 'in fig. 7A, and fig. 7E is a schematic cross-sectional view taken along a cut line EE' in fig. 7A. Fig. 8 is based on fig. 7B, and shows a specific structure of the access transistor 800 in the sub-active region 502.
The memory comprises a plurality of sub-active regions 502, and isolation structures surrounding the sidewalls and the bottom of the sub-active regions 502, wherein the isolation structures comprise a first isolation structure 401 and a second isolation structure 701 which are laterally connected. The sub-active region 502 and the isolation structure are located on the substrate 100, and the bottom of the sub-active region 502 is isolated from the substrate 100 by the isolation structure.
The top width of the first isolation structure 401 is smaller than the bottom width such that a portion of the first isolation structure 401 is supported below the edge of the sub-active region 502.
In this embodiment, the first isolation structure 401 has a step-shaped sidewall, and a step protruding portion of the step-shaped sidewall is located below an edge of the sub-active region 502. In another specific embodiment, the first isolation structure 401 may further have a sloped sidewall, and the first isolation structure 401 is partially located below the edge of the sub-active region 502 and located within a projection of the sub-active region 502 on the plane of the substrate 100.
The depth of the first isolation structure 401 is greater than that of the sub-active region 502, the lower portion of the first isolation structure 401 below the sub-active region 502 may have a horizontal bottom surface, an arc bottom surface, and the like, and the cross section of the lower portion of the first isolation structure 401 below the sub-active region 502 may be an ellipse, a semicircle, a rounded rectangle, a polygon, or other shapes.
The first isolation structure 401 extends along the length direction of the sub-active regions 502, is located between adjacent sub-active regions 502, and is partially located below the long edge of the sub-active region 502, so as to better support the sub-active regions 502.
The second isolation structure 401 is partially located between short sides of the sub-active region 502, partially located below the bottom of the sub-active region 502, and arranged along the length direction of the sub-active region 502.
A hole may be further formed in the second isolation structure 401 under the sub-active region 502, so as to improve the isolation performance of the second isolation structure 401.
The memory further includes an access transistor 800 (see fig. 8) located in each sub-active region 502, and a capacitor (not shown) located above the sub-active region 502 and connected to the source of the access transistor 800.
The access transistor 800 includes two gate structures buried within the sub-active region 502, a drain 803 between adjacent gate structures, and a source 804 outside the gate structures. The gate structure comprises a gate 801 embedded in a sub-active region 502 and a gate dielectric layer 802 positioned between the gate 801 and the active region 502. A gate isolation layer 805 is also formed on top of the gate 801.
In this embodiment, the access transistor is a buried gate transistor structure. The access transistor may also be other transistor structures such as a planar gate type transistor or a gate all around type transistor.
Because the bottom and the side wall of the sub-active region 502 are both surrounded by the first isolation structure 401 and the second isolation structure 701, electrons of the sub-active region 502 cannot migrate outwards, so that the leakage current of the formed memory can be reduced, and the performance of the memory can be improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (17)

1. A method for forming a memory, comprising:
providing a substrate;
forming a plurality of first grooves in the substrate, wherein the substrate between the adjacent first grooves is an active region, and the width of the top of each first groove is smaller than that of the bottom of each first groove;
forming a first isolation structure in the first trench, wherein part of the first isolation structure is supported below the edge of the active region;
forming a plurality of second grooves in the substrate, wherein the second grooves divide the active region into a plurality of sub-active regions and suspend the sub-active regions, and the forming method of the second grooves comprises the following steps: etching the substrate to form a plurality of second upper grooves, wherein the second upper grooves divide the active region into a plurality of sub active regions; forming a side wall on the side wall of the sub-active region; continuing to etch the substrate along the second upper groove, removing part of substrate material below the sub-active region, and forming a second lower groove communicated with the second upper groove;
and filling a second isolation structure in the second groove, wherein the second isolation structure is transversely connected with the first isolation structure and surrounds the side wall and the bottom of the sub-active region.
2. The method of claim 1, wherein the first trench has a sloped sidewall or a step-like sidewall.
3. The method of claim 1, wherein the first trench is formed by a method comprising: etching the substrate to form a plurality of first upper grooves, wherein an active region is arranged between every two adjacent first upper grooves; forming a side wall on the side wall of the active region; and continuously etching the substrate along the first upper groove to form a first lower groove communicated with the first upper groove, wherein the first lower groove is partially positioned below the edges of the active regions at two sides.
4. The method as claimed in claim 3, wherein the substrate is etched by an isotropic etching process to form the first lower trench.
5. The method of claim 1, wherein the second lower trench is formed by etching the substrate using an isotropic etching process.
6. The method as claimed in claim 4 or 5, wherein the isotropic etching process is a wet etching process.
7. The method of claim 1, wherein the first trench extends along a length direction of the sub-active region.
8. The method of claim 1, further comprising: an access transistor is formed within the sub-active region.
9. The method of claim 8, wherein the access transistor comprises two gate structures buried within the sub-active region, a drain located between adjacent gate structures, and a source located outside the gate structures.
10. A memory formed by the method of any one of claims 1-9, comprising:
a plurality of sub-active regions;
an isolation structure surrounding sidewalls and a bottom of the sub-active region, the isolation structure including a first isolation structure and a second isolation structure that are laterally connected.
11. The memory of claim 10, wherein a top width of the first isolation structure is less than a bottom width.
12. The memory of claim 10, wherein a portion of the first isolation structures are supported below an edge of the sub-active region.
13. The memory of claim 10, wherein a portion of the second isolation structure is located below a bottom of the sub-active region.
14. The memory of claim 10, wherein the first isolation structure has a sloped sidewall or a stepped sidewall.
15. The memory of claim 10, wherein the first isolation structure extends along a length of the sub-active region.
16. The memory of claim 10, further comprising: the access transistor is positioned in each sub-active area, and the capacitor is positioned above the sub-active area and connected with the source electrode of the access transistor.
17. The memory of claim 16, wherein the access transistor comprises two gate structures buried within the sub-active region, a drain located between adjacent gate structures, and a source located outside of a gate structure.
CN201910283488.6A 2019-04-10 2019-04-10 Memory and forming method thereof Active CN111816658B (en)

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