CN111816626A - Wafer-level chip packaging structure and packaging method - Google Patents
Wafer-level chip packaging structure and packaging method Download PDFInfo
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- CN111816626A CN111816626A CN202010912689.0A CN202010912689A CN111816626A CN 111816626 A CN111816626 A CN 111816626A CN 202010912689 A CN202010912689 A CN 202010912689A CN 111816626 A CN111816626 A CN 111816626A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 33
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- 230000001737 promoting effect Effects 0.000 claims description 52
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- 229910052737 gold Inorganic materials 0.000 claims description 27
- 239000010931 gold Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 20
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000010949 copper Substances 0.000 description 17
- 239000000463 material Substances 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000005530 etching Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 9
- 238000000227 grinding Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 230000032798 delamination Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000011368 organic material Substances 0.000 description 4
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- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000013043 chemical agent Substances 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
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- Power Engineering (AREA)
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Abstract
The invention discloses a wafer-level chip packaging structure and a packaging method, wherein the structure comprises the following components: the wafer is provided with a first surface and a second surface opposite to the first surface, a plurality of chip units are integrated in the wafer, the first surface is provided with at least one metal gasket and an internal insulating layer, the internal insulating layer is provided with at least one opening structure, part or all of the metal gasket is exposed out of the opening structure, the metal gasket is electrically connected with the chip units, and the second surface is provided with at least one groove; the adhesion promotion layer is arranged in the groove and is flush with the second surface; the wafer comprises at least one through hole, and part or all of the metal gasket is exposed out of the through hole; and the wiring layer is arranged on the second surface and covers the adhesion-promoting layer and the bottom surface and the side surface of the through hole. According to the technical scheme provided by the embodiment of the invention, the bonding strength between the wafer and the wiring layer in the wafer-level chip packaging structure and the structure of the wiring layer at the side far away from the wafer is increased.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a wafer-level chip packaging structure and a packaging method.
Background
At present, wafer level chip size packaging is one of the integrated circuit packaging methods, and is a packaging method for obtaining single chips by packaging an entire chip and then cutting the packaged chip.
In the existing wafer level chip packaging structure, the layering phenomenon easily occurs on the wiring layer and the structure of the side of the wiring layer far away from the wafer.
Disclosure of Invention
In view of this, embodiments of the present invention provide a wafer level chip package structure and a wafer level chip package method, which increase the bonding strength between a wiring layer in the wafer level chip package structure and a structure of the wiring layer on a side away from a wafer and the wafer.
The embodiment of the invention provides a wafer-level chip packaging structure, which comprises:
the wafer is provided with a first surface and a second surface opposite to the first surface, a plurality of chip units are integrated in the wafer, the first surface is provided with at least one metal gasket and an internal insulating layer, the internal insulating layer is provided with at least one opening structure, part or all of the metal gasket is exposed out of the opening structure, the metal gasket is electrically connected with the chip units, and the second surface is provided with at least one groove;
the adhesion promotion layer is arranged in the groove, and the adhesion promotion layer is flush with the second surface; the wafer comprises at least one through hole, and the through hole exposes part or all of the metal gasket;
and the wiring layer is arranged on the second surface and covers the adhesion promoting layer and the bottom surface and the side surface of the through hole.
Optionally, the depth of the groove is greater than or equal to 0.1 micron and less than or equal to 100 microns.
Optionally, the cross-sectional shape of the groove comprises a rectangle or a circle.
Optionally, the longitudinal cross-sectional shape of the groove comprises an inverted trapezoid or an arc.
Optionally, the wiring layer includes a seed layer and a back gold layer which are stacked.
Optionally, the metal pad includes a ground metal pad and a signal metal pad, and the opening structure exposes the ground metal pad.
Optionally, the thickness of the wafer is greater than or equal to 20 micrometers and less than or equal to 500 micrometers.
The embodiment of the invention also provides a wafer-level chip packaging method, which comprises the following steps:
providing a wafer, wherein the wafer is provided with a first surface and a second surface opposite to the first surface, a plurality of chip units are integrated in the wafer, the first surface is provided with at least one metal gasket and an internal insulating layer, the insulating layer is provided with at least one opening structure, one opening structure exposes one metal gasket, the metal gasket is electrically connected with the chip units, and the second surface is provided with at least one groove;
forming an adhesion promoting layer in the groove, wherein the adhesion promoting layer is flush with the second surface;
forming at least one through hole in the wafer, wherein the through hole exposes part or all of the metal gasket;
and forming a wiring layer on the second surface, wherein the wiring layer covers the adhesion promoting layer and the bottom surface and the side surface of the through hole.
Optionally, the providing the wafer comprises:
temporarily bonding a support substrate on the first surface of the wafer, wherein the support substrate is used for supporting the wafer;
and thinning the surface of the wafer opposite to the first surface to obtain the second surface.
Optionally, forming a wiring layer on the second surface, wherein the wiring layer covers the adhesion promoting layer and the bottom and side surfaces of the through hole, and further includes:
removing the support substrate;
and cutting the wafer to obtain a single chip.
According to the technical scheme, the at least one groove is formed in the second surface of the wafer, the adhesion promoting layer is arranged in the groove, the adhesion promoting layer is flush with the second surface, the wiring layer is not protruded in the adhesion promoting layer, the adhesion promoting layer is a flat surface, the adhesion strength between the structure of the wiring layer and the structure of the wiring layer far away from one side of the wafer and the wafer in the wafer-level chip packaging structure is increased due to the arrangement of the adhesion promoting layer, and the layering phenomenon of the structure of the wiring layer and the structure of the wiring layer far away from one side of the wafer can be avoided. In addition, the adhesion promoting layer is only arranged in the groove and does not cover the whole second surface, so that the heat dissipation requirement of the wafer-level chip packaging structure can be met.
Drawings
Fig. 1 is a schematic structural diagram of a wafer level chip package structure according to an embodiment of the present invention;
fig. 2 is a top view of a second surface of a wafer according to an embodiment of the invention;
FIG. 3 is a top view of a second surface of another wafer according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another wafer-level chip package structure according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a wafer level chip packaging method according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating a wafer level chip packaging method according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating a wafer level chip packaging method according to an embodiment of the present invention;
fig. 8-17 are cross-sectional views corresponding to steps of a wafer level chip packaging method according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, in the conventional wafer level chip package structure, the wiring layer and the structure of the side of the wiring layer away from the wafer are prone to delamination. The conventional wafer-level chip packaging structure includes a wafer, a wiring layer and an adhesion-promoting layer, wherein the adhesion-promoting layer is located between the wafer and the wiring layer, and the adhesion-promoting layer is located on the surface of the wafer. Because the adhesion promoting layer has certain thickness, the wiring layer has certain degree of protrusion at the adhesion promoting layer, and the layering phenomenon easily occurs to the structure of the wiring layer and the side of the wiring layer far away from the wafer.
In view of the above technical problems, an embodiment of the present invention provides the following technical solutions:
fig. 1 is a schematic structural diagram of a wafer level chip package structure according to an embodiment of the present invention. Referring to fig. 1, the wafer level chip package structure includes: a wafer 10, the wafer 10 having a first surface 100 and a second surface 101 opposite to the first surface 100, the wafer 10 having a plurality of chip units (not shown) integrated therein, the first surface 100 being provided with at least one metal pad 11 and an internal insulating layer 12, the internal insulating layer 12 having at least one opening structure 12A, the opening structure 12A exposing part or all of the metal pad 11, the metal pad 11 being electrically connected to the chip units, the second surface 101 being provided with at least one groove 10A; the adhesion promoting layer 13 is arranged in the groove 10A, and the adhesion promoting layer 13 is flush with the second surface 101; the wafer 10 includes at least one through hole 10B, and the through hole 10B exposes part or all of the metal pad 11; and a wiring layer 14 disposed on the second surface 101 and covering the adhesion-promoting layer 13 and the bottom and side surfaces of the through hole 10B.
Specifically, the thermal expansion coefficient of the adhesion promoting layer 13 is generally located between the wafer 10 and the wiring layer 14, and the adhesion promoting layer 13 can increase the bonding strength between the wiring layer 14 and the structure of the wiring layer 14 far from the wafer 10 in the wafer level chip package structure and the wafer 10.
The wafer 10 may be silicon, germanium, or other semiconductor substrate material. The chip unit is a circuit structure formed by multiple layers of electronic components with specific functions formed on the first surface 100 of the wafer 10 through multiple processes such as photolithography, ion implantation, etching, and evaporation. The metal pads 11 are electrically connected to the chip units, and transmit the electrical signals of the chip units to the second surface 101 of the wafer 10 through the wiring layer 14, for example, other structures may be provided on the surface of the wiring layer 14 on the side away from the wafer 10, and the wiring layer 14 may lead out the electrical signals of the chip units to transmit the electrical signals to the structure on the side away from the wafer 10. The internal insulating layer 12 serves to electrically insulate the chip units within the wafer 10. Illustratively, the inner insulating layer 12 may be silicon dioxide or silicon nitride, and the inner insulating layer 12 at the opening structure 12A may be removed by etching the semiconductor dielectric layer, which is also a plasma dry etching method that uses a special gas to react only with silicon dioxide or silicon nitride and to remove the silicon dioxide or silicon nitride in an inert reaction manner with respect to the wafer. The via hole 10B may be formed by an etching process, for example.
Compared with the prior art, the wiring layer has a certain degree of protrusion at the position of the adhesion promoting layer, in the embodiment, the adhesion promoting layer 13 is arranged in the groove 10A, the adhesion promoting layer 13 is flush with the second surface 101, so that the wiring layer 14 does not have the protrusion at the position of the adhesion promoting layer 13 and is a flat surface, the arrangement of the adhesion promoting layer 13 increases the bonding strength between the structure of the wiring layer 14 and the side, away from the wafer 10, of the wiring layer 14 in the wafer level chip packaging structure and the wafer 10, and the delamination phenomenon of the structure of the wiring layer 14 and the side, away from the wafer 10, of the wiring layer 14 can be avoided. In addition, the adhesion promoting layer 13 is only disposed in the groove 10A, and does not cover the entire second surface 101, so that the heat dissipation requirement of the wafer level chip package structure can be met.
According to the technical scheme provided by the embodiment, the at least one groove 10A is formed in the second surface 101 of the wafer 10, the adhesion promoting layer 13 is arranged in the groove 10A, and the adhesion promoting layer 13 is flush with the second surface 101, so that the wiring layer 14 does not have a protrusion at the adhesion promoting layer 13 and is a flat surface, the arrangement of the adhesion promoting layer 13 increases the bonding strength between the wafer 10 and the structures of the wiring layer 14 and the side of the wiring layer 14 far from the wafer 10 in the wafer level chip packaging structure, and the delamination phenomenon of the structures of the wiring layer 14 and the side of the wiring layer 14 far from the wafer 10 can be avoided. In addition, the adhesion promoting layer 13 is only disposed in the groove 10A, and does not cover the entire second surface 101, so that the heat dissipation requirement of the wafer level chip package structure can be met.
Optionally, the depth of the groove 10A is greater than or equal to 0.1 micrometers and less than or equal to 100 micrometers.
Specifically, the depth of the groove 10A determines the thickness of the adhesion-promoting layer 13, and the depth of the groove 10A is too small to be smaller than 0.1 μm, which results in too thin thickness of the adhesion-promoting layer 13 and too low adhesion strength between the wiring layer 14 and the structure of the wiring layer 14 on the side away from the wafer 10 and the wafer 10. The depth of the recess 10A is too large to be greater than 100 microns, resulting in too thick a thickness of the adhesion-promoting layer 13, reducing the mechanical strength of the wafer 10.
For example, when the adhesion promoting layer 13 is an organic material, the adhesion promoting layer 13 may be prepared by a semiconductor coating method; when the adhesion-promoting layer 13 is a silicon dioxide material, a physical vapor chemical deposition (PECVD) may be used to fabricate the silicon dioxide material as the adhesion-promoting layer 13 on the second surface 101 of the wafer 10. Preferably, an organic material having characteristics of low thermal resistance, stable heat resistance, stable chemical resistance, low coefficient of thermal expansion of the material, and the like can be used as the adhesion promoting layer 13. It should be noted that the adhesion promoting layer 13 is a patterned structure, i.e., only the adhesion promoting layer 13 is disposed in the groove 10A. The patterned structure may be formed by semiconductor lithography, i.e., first applying a layer of photoresist over the adhesion-promoting layer 13, patterning the photoresist after photolithography, and finally removing the adhesion-promoting layer 13 by dry etching. According to the material characteristics of the adhesion promoting layer 13, the adhesion promoting layer 13 with a patterned structure can be realized by adopting a laser processing method.
Fig. 2 is a top view of a second surface of a wafer according to an embodiment of the invention. Fig. 3 is a top view of a second surface of another wafer according to an embodiment of the invention. Alternatively, referring to fig. 2 and 3, the cross-sectional shape of the groove 10A includes a rectangle or a circle.
Note that the cross-sectional shape of the groove 10A shown in fig. 2 includes a rectangle. The cross-sectional shape of the groove 10A shown in fig. 3 includes a circle.
Alternatively, referring to fig. 1, the longitudinal sectional shape of the groove 10A includes an inverted trapezoid or an arc.
It should be noted that the longitudinal cross-sectional shape of the groove 10A exemplarily shown in fig. 1 includes an inverted trapezoid, so as to facilitate formation of the adhesion-promoting layer 13 in the groove 10A.
Fig. 4 is a schematic structural diagram of another wafer-level chip package structure according to an embodiment of the present invention. Alternatively, referring to fig. 4, the wiring layer 14 includes a seed layer 14A and a back gold layer 14B which are stacked.
Specifically, the seed layer 14A may enhance the bonding force between the metal and the wafer 10, and may prepare for the subsequent deposition of the back gold layer 14B. The metal of seed layer 14A may be one or more of Ti/Cu, TiW/Cu, or Cr/Cu. In the embodiment of the present invention, preferably, the metal of the seed layer 14A is an environmentally-friendly and low-cost Ti/Cu structure, wherein the thickness of Ti is 0.05 to 0.5 micrometers, the thickness of Cu is 0.5 to 3 micrometers, and the specific thickness of the metal layer can be adjusted according to the actual shape of the through hole 10B. Preferably, copper, nickel, and gold are sequentially deposited on the surface of the seed layer 14A in the embodiment of the present invention to form the back gold layer 14B, where the thickness of copper may be 2 to 20 microns, the thickness of nickel may be 2 to 5 microns, and the thickness of gold may be 0.05 to 1 micron. Since the conductive metal used for the back gold layer 14B has a requirement of low connection resistance, the thicker the copper plating layer is, the better. The conductive metal used for the back gold layer 14B may be other metal or alloy material having excellent conductivity, such as pd, Sn, and Ag. The back gold layer 14B is arranged on the seed layer 14A, so that the problem that the back gold layer 14B is easy to generate insufficient bonding force such as bubbling delamination and the like to cause product failure can be avoided, the problems that the back gold layer 14B is insufficient in bonding force with the wafer 10 and easy to bubble delamination can be effectively solved, and the back gold material in the embodiment of the invention is corrosion-resistant, is not limited by use environment and time, and can improve reliability.
Alternatively, referring to fig. 4, the metal pad 11 includes a ground metal pad 11A and a signal metal pad 11B, and the opening structure 12A exposes the ground metal pad 11A.
Illustratively, the material above the grounding metal pad 11A is selectively removed to expose the inner insulating layer 12 of the grounding metal pad 11A. The wafer 10 on the signal metal pad 11B is not removed. Preferably, a photolithography process and a dry etching process may be used to etch away the excess wafer 10 and the internal insulation layer 12, exposing the grounding metal pad 11A.
Illustratively, the longitudinal cross-sectional shape of the via 10B may include an inverted trapezoid, and the cross-sectional shape of the via 10B may include a rectangle or a circle, so as to facilitate the preparation of the subsequent wiring layer 14. The preparation method of the through hole 10B is as follows: the second surface 101 is covered with a photoresist material having a photosensitive property, and then a mask having a specific pattern is used to perform a photosensitive process under light of a specific wavelength, and then a chemical agent is used to perform development to produce a photoresist pattern. The portions not covered by the photoresist are removed by reactive fluorine ion etching, thereby removing the wafer 10. A wet etch process may also be used instead of a dry etch process. After the silicon etching is completed, the resist on the surface is removed, and then the second surface 101 is cleaned.
Alternatively, referring to fig. 4, the thickness of the wafer 10 is greater than or equal to 20 microns and less than or equal to 500 microns.
For example, the wafer 10 may be thinned to a thickness greater than or equal to 20 micrometers and less than or equal to 500 micrometers by one or more of mechanical grinding using a diamond-impregnated wheel, mechanochemical grinding and polishing, dry plasma etching, or wet etching using a fluorine-containing chemical solution. The thickness of the thinned wafer 10 can be adjusted according to the specific application requirements. Preferably, a diamond-impregnated wheel may be used for mechanical grinding and then a plasma dry etching method may be used. The method has the advantages that the mechanical grinding processing is fast, but stress and micro-damage layers are generated on the silicon surface, and then the micro-damage layers are removed by using a plasma dry etching method, so that the surface stress is released, and the warping problem of the wafer 10 is solved.
The embodiment of the invention also provides a wafer-level chip packaging method. Fig. 5 is a flowchart of a wafer level chip packaging method according to an embodiment of the invention. Fig. 6 is a flowchart of another wafer level chip packaging method according to an embodiment of the invention. Fig. 7 is a flowchart of another wafer level chip packaging method according to an embodiment of the present invention. Referring to fig. 5, the wafer level chip packaging method includes the following steps:
Optionally, referring to fig. 6, step 110 before providing the wafer includes:
Referring to fig. 8, a support substrate 30 is temporarily bonded to the first surface 100 of the wafer 10, and the support substrate 30 is used to support the wafer 10. The support substrate 30 may be glass, for example. The thickness of the support substrate 30 may be 0.3-1.5 mm. In the subsequent thinning process of the wafer 10, the thickness is reduced to within 20-500 microns, the supporting substrate 30 plays a supporting role, and the wafer 10 is prevented from being broken in the subsequent processing process of the through hole 10B and the wiring layer 14. Illustratively, the metal pad 11 includes a ground metal pad 11A and a signal metal pad 11B, and the opening structure 12A exposes the ground metal pad 11A.
It should be noted that a temporary bonding layer 20 is further disposed between the wafer 10 and the support substrate 30 for bonding the wafer 10 and the support substrate 30. The wafer 10 has a first surface 100 and a surface 102 opposite to the first surface 100, a plurality of chip units are integrated in the wafer 10, and the first surface 100 is provided with at least one metal pad 11 and an inner insulating layer 12.
Referring to fig. 9, a surface 102 of the wafer 10 opposite to the first surface 100 is thinned to obtain a second surface 101.
For example, the wafer 10 may be thinned to a thickness greater than or equal to 20 micrometers and less than or equal to 500 micrometers by one or more of mechanical grinding using a diamond-impregnated wheel, mechanochemical grinding and polishing, dry plasma etching, or wet etching using a fluorine-containing chemical solution. The thickness of the thinned wafer 10 can be adjusted according to the specific application requirements. Preferably, a diamond-impregnated wheel may be used for mechanical grinding and then a plasma dry etching method may be used. The method has the advantages that the mechanical grinding processing is fast, but stress and micro-damage layers are generated on the silicon surface, and then the micro-damage layers are removed by using a plasma dry etching method, so that the surface stress is released, and the problem of wafer warping is solved.
Optionally, step 1102 is followed by the following steps:
at least one groove 10A is formed in the second surface 101, step 1103.
Preferably, referring to fig. 10, a photolithography process and a dry etching process may be used to etch away the excess wafer 10, so as to form a groove 10A of 0.1-100 μm. The cross-sectional shape of the groove 10A includes a rectangle or a circle. The longitudinal sectional shape of the groove 10A includes an inverted trapezoid or an arc. The specific etching process is as follows: the second surface 101 is covered with a photoresist material having a photosensitive property, and then a mask having a specific pattern is used to perform a photosensitive process under light of a specific wavelength, and then a chemical agent is used to perform development to produce a photoresist pattern. The portions not covered by the photoresist are removed by reactive fluorine ion etching, thereby removing the material from the second surface 101. A wet etch process may also be used instead of a dry etch process. After the silicon etching is completed, the resist on the surface is removed, and then the second surface 101 is cleaned.
And 120, forming an adhesion promoting layer in the groove, wherein the adhesion promoting layer is flush with the second surface.
Referring to fig. 11, an adhesion promoting layer 13 is formed in the groove 10A, and the adhesion promoting layer 13 is flush with the second surface 101; illustratively, when the adhesion promoting layer 13 is an organic material, the adhesion promoting layer 13 is prepared by a semiconductor coating method; when the adhesion-promoting layer 13 is made of silicon dioxide, a silicon dioxide material is formed on the second surface 101 of the wafer as the adhesion-promoting layer 13 by physical vapor chemical deposition (PECVD). Preferably, the adhesion promoting layer 13 is an organic material having characteristics of low thermal resistance, stable heat resistance, stable chemical resistance, low coefficient of thermal expansion of the material, and the like. It should be noted that the adhesion promoting layer 13 is a patterned structure, i.e., only the adhesion promoting layer 13 is disposed in the groove 10A. The patterned structure may be formed by semiconductor lithography, where a layer of photoresist is first applied to the adhesion-promoting layer 13, patterned after lithography, and finally removed by dry etching of the adhesion-promoting layer 13 to be removed. According to the material characteristics of the adhesion promoting layer 13, the adhesion promoting layer 13 with a patterned structure can be realized by adopting a laser processing method.
At step 130, at least one via is formed in the wafer, the via exposing a portion or all of the metal liner.
Referring to fig. 12 and 13, at least one via hole 10B is formed in the wafer 10, the via hole 10B exposing a part or all of the metal pad 11. Referring to fig. 12, first etching is performed in the wafer 10 to expose the internal insulating layer 12. Referring to fig. 13, a second etching is then performed on the basis of the first etching to form an opening structure 12A exposing part or all of the metal pad 11. Illustratively, the opening structure 12A in fig. 13 exposes the grounding metal pad 11A. The first etching and the second etching collectively form the via hole 10B.
Illustratively, the longitudinal sectional shape of the through-hole 10B may include an inverted trapezoid. The cross-sectional shape of the via 10B includes a rectangle or a circle, which is convenient for the preparation of the subsequent wiring layer 14. The preparation method of the through hole 10B is as follows: the second surface 101 is covered with a photoresist material having a photosensitive property, and then a mask having a specific pattern is used to perform a photosensitive process under light of a specific wavelength, and then a chemical agent is used to perform development to produce a photoresist pattern. The portions not covered by the photoresist are removed by reactive fluorine ion etching, thereby removing the wafer 10. A wet etch process may also be used instead of a dry etch process. After the silicon etching is completed, the resist on the surface is removed, and then the second surface 101 is cleaned.
And 140, forming a wiring layer on the second surface, wherein the wiring layer covers the adhesion-promoting layer and the bottom surface and the side surface of the through hole.
Referring to fig. 14 and 15, a wiring layer 14 is formed on the second surface, covering the adhesion-promoting layer and the bottom and side surfaces of the through-hole. Optionally, the wiring layer 14 includes a seed layer 14A and a back gold layer 14B.
In order to achieve a back gold layer with good conduction and uniform thickness, the implementation needs to be performed in 2 steps: referring to fig. 14, a thin seed layer 14A is deposited on the second surface 101 of the wafer and the bottom and sidewalls of the via hole 10B by magnetron sputtering. Referring to fig. 15, a back gold layer 14B is formed by sequentially depositing copper, nickel and gold on the surface of the seed layer 14A by using an electroplating or electroless plating technique.
Specifically, the seed layer 14A may enhance the bonding force between the metal and the wafer 10, and may prepare for the subsequent deposition of the back gold layer 14B. The metal of seed layer 14A may be one or more of Ti/Cu, TiW/Cu, or Cr/Cu. In the embodiment of the present invention, preferably, the metal of the seed layer 14A is an environmentally-friendly and low-cost Ti/Cu structure, wherein the thickness of Ti is 0.05 to 0.5 micrometers, the thickness of Cu is 0.5 to 3 micrometers, and the specific thickness of the metal layer can be adjusted according to the actual shape of the through hole 10B. Preferably, copper, nickel, and gold are sequentially deposited on the surface of the seed layer 14A in the embodiment of the present invention to form the back gold layer 14B, where the thickness of copper may be 2 to 20 microns, the thickness of nickel may be 2 to 5 microns, and the thickness of gold may be 0.05 to 1 micron. Since the conductive metal used for the back gold layer 14B has a requirement of low connection resistance, the thicker the copper plating layer is, the better. The conductive metal used for the back gold layer 14B may be other metal or alloy material having excellent conductivity, such as pd, Sn, and Ag. The back gold layer 14B is arranged on the seed layer 14A, so that the problem that the back gold layer 14B is easy to generate insufficient bonding force such as bubbling delamination and the like to cause product failure can be avoided, the problems that the back gold layer 14B is insufficient in bonding force with the wafer 10 and easy to bubble delamination can be effectively solved, and the back gold material in the embodiment of the invention is corrosion-resistant, is not limited by use environment and time, and can improve reliability.
Optionally, referring to fig. 7, step 140, forming a wiring layer on the second surface, the wiring layer covering the adhesion promoting layer and the bottom and side surfaces of the through hole, and further comprising:
Referring to fig. 16, the support substrate 30 is removed, i.e., the temporary bonding layer 20 is removed. The material of the temporary bonding layer 20 is different, corresponding to different ways of removing the temporary bonding layer 20. The bonding and detachment of the wafer 10 and the supporting substrate 30 according to the present invention may be performed by any one of a laser method, a UV light method, a chemical method, a mechanical method, and a thermal slide method. In a preferred embodiment of the present invention, the wafer 10 and the supporting substrate 30 are bonded by laser bonding or UV light bonding.
And 160, cutting the wafer to obtain single chips.
Referring to fig. 17, the wafer 10 is diced to obtain individual chips 111. Illustratively, the wafer 10 may be processed using a metal blade or laser cutting.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A wafer level chip package structure, comprising:
the wafer is provided with a first surface and a second surface opposite to the first surface, a plurality of chip units are integrated in the wafer, the first surface is provided with at least one metal gasket and an internal insulating layer, the internal insulating layer is provided with at least one opening structure, part or all of the metal gasket is exposed out of the opening structure, the metal gasket is electrically connected with the chip units, and the second surface is provided with at least one groove;
the adhesion promotion layer is arranged in the groove, and the adhesion promotion layer is flush with the second surface; the wafer comprises at least one through hole, and the through hole exposes part or all of the metal gasket;
and the wiring layer is arranged on the second surface and covers the adhesion promoting layer and the bottom surface and the side surface of the through hole.
2. The wafer-level chip package structure of claim 1, wherein the depth of the groove is greater than or equal to 0.1 microns and less than or equal to 100 microns.
3. The wafer-level chip package structure of claim 1, wherein a cross-sectional shape of the groove comprises a rectangle or a circle.
4. The wafer-level chip package structure of claim 1, wherein a longitudinal cross-sectional shape of the groove comprises an inverted trapezoid or an arc.
5. The wafer-level chip package structure of claim 1, wherein the wiring layer comprises a seed layer and a back gold layer arranged in a stacked manner.
6. The wafer-level chip package structure of claim 1, wherein the metal pads comprise a ground metal pad and a signal metal pad, and the opening structure exposes the ground metal pad.
7. The wafer-level chip package structure of claim 1, wherein the thickness of the wafer is greater than or equal to 20 microns and less than or equal to 500 microns.
8. A wafer level chip packaging method is characterized by comprising the following steps:
providing a wafer, wherein the wafer is provided with a first surface and a second surface opposite to the first surface, a plurality of chip units are integrated in the wafer, the first surface is provided with at least one metal gasket and an internal insulating layer, the insulating layer is provided with at least one opening structure, one opening structure exposes one metal gasket, the metal gasket is electrically connected with the chip units, and the second surface is provided with at least one groove;
forming an adhesion promoting layer in the groove, wherein the adhesion promoting layer is flush with the second surface;
forming at least one through hole in the wafer, wherein the through hole exposes part or all of the metal gasket;
and forming a wiring layer on the second surface, wherein the wiring layer covers the adhesion promoting layer and the bottom surface and the side surface of the through hole.
9. The wafer-level chip packaging method of claim 8, wherein providing the wafer comprises:
temporarily bonding a support substrate on the first surface of the wafer, wherein the support substrate is used for supporting the wafer;
and thinning the surface of the wafer opposite to the first surface to obtain the second surface.
10. The wafer level chip packaging method according to claim 9, wherein forming a wiring layer on the second surface, the wiring layer covering the adhesion promoting layer and the bottom and side surfaces of the through hole further comprises:
removing the support substrate;
and cutting the wafer to obtain a single chip.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661929A (en) * | 2008-08-27 | 2010-03-03 | 日月光半导体制造股份有限公司 | Stacked type chip package structure |
| JP2014072403A (en) * | 2012-09-28 | 2014-04-21 | Sumitomo Metal Mining Co Ltd | Wiring board for solar cell, solar cell with wiring board using the same and method for manufacturing the same |
| US20150014027A1 (en) * | 2013-07-11 | 2015-01-15 | Shinko Electric Industries Co., Ltd. | Wiring board and method for manufacturing the same |
| CN106876356A (en) * | 2017-03-09 | 2017-06-20 | 华天科技（昆山）电子有限公司 | Chip insertion silicon substrate formula fan-out package structure and preparation method thereof |
| US20190333849A1 (en) * | 2018-04-27 | 2019-10-31 | Shinko Electric Industries Co., Ltd. | Wiring substrate and semiconductor device |
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2020
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661929A (en) * | 2008-08-27 | 2010-03-03 | 日月光半导体制造股份有限公司 | Stacked type chip package structure |
| JP2014072403A (en) * | 2012-09-28 | 2014-04-21 | Sumitomo Metal Mining Co Ltd | Wiring board for solar cell, solar cell with wiring board using the same and method for manufacturing the same |
| US20150014027A1 (en) * | 2013-07-11 | 2015-01-15 | Shinko Electric Industries Co., Ltd. | Wiring board and method for manufacturing the same |
| CN106876356A (en) * | 2017-03-09 | 2017-06-20 | 华天科技（昆山）电子有限公司 | Chip insertion silicon substrate formula fan-out package structure and preparation method thereof |
| US20190333849A1 (en) * | 2018-04-27 | 2019-10-31 | Shinko Electric Industries Co., Ltd. | Wiring substrate and semiconductor device |
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