CN111816602A - Chip preparation method and chip - Google Patents
Chip preparation method and chip Download PDFInfo
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- CN111816602A CN111816602A CN202010708169.8A CN202010708169A CN111816602A CN 111816602 A CN111816602 A CN 111816602A CN 202010708169 A CN202010708169 A CN 202010708169A CN 111816602 A CN111816602 A CN 111816602A
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- wafer body
- layer
- chip
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- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Abstract
The embodiment that this application provided fixes through first fixed bed and can prevent at the in-process to the wafer body back attenuate, wafer body warpage, then sets up the second fixed bed through the second metal level lower surface at the wafer body back in order to prevent to get rid of first fixed bed, wafer body warpage, get rid of behind the first fixed bed, and right the wafer body is cut apart the processing, obtains a plurality of chips, and the technical scheme process that this application provided is simple, and can obtain thinner, miniaturized chip in batches.
Description
Technical Field
The embodiment of the application belongs to the technical field of semiconductors, and particularly relates to a chip preparation method and a chip.
Background
Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile handsets, digital cameras, and other electronic devices, and the semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuing to reduce the minimum feature size, which allows many components to be integrated into a given area.
In the existing manufacturing process, a chip with a small size and a thin thickness cannot be obtained, and the manufacturing process is complex.
Disclosure of Invention
It is an aim of embodiments of the present application to overcome the above problems or to at least partially solve or mitigate them.
The embodiment of the application provides a chip preparation method, which comprises the following steps,
providing a wafer body, wherein a plurality of chips are formed on the wafer body;
forming metal columns above first metal layers arranged on the front surface of the wafer body at intervals;
arranging a first fixing layer covering the metal column on the front surface of the wafer body;
thinning the back of the wafer body, and forming a second metal layer on the back of the wafer body;
arranging a second fixed layer on one surface of the second metal layer, which is far away from the wafer body, and then removing the first fixed layer;
and carrying out segmentation processing on the wafer body to obtain a plurality of chips.
As a preferred embodiment of the present application, the first fixing layer and the second fixing layer are made of the same material.
In a preferred embodiment of the present application, the first anchor layer and the second anchor layer are made of a film-like material.
As a preferred embodiment of the present application, adhesive materials are disposed on the surfaces of the first fixing layer and the second fixing layer close to the wafer body, and the first fixing layer and the second fixing layer are respectively adhered to the front surface and the back surface of the wafer body through the adhesive materials.
As a preferred embodiment of the present application, the second metal layer is formed on the back surface of the wafer body by electroplating.
As a preferred embodiment of the present application, the first metal layer is an aluminum metal layer, the second metal layer sequentially includes an additional nickel-silicon metal layer and a copper metal layer from inside to outside, and the metal pillar is a copper metal pillar.
As a preferred embodiment of the present application, the chip is a MOS transistor.
Compared with the prior art, the embodiment that this application provided fixes through first fixed bed can prevent at the in-process to the wafer body back attenuate, wafer body warpage, then sets up the second fixed bed through the second metal level lower surface at the wafer body back in order to prevent to get rid of first fixed bed, wafer body warpage gets rid of behind the first fixed bed, and right the wafer body is cut apart the processing, obtains a plurality of chips, and the technical scheme process that this application provided is simple, and can obtain miniaturized chip in batches.
In a second aspect, an embodiment of the present application provides a chip, and the chip is prepared by the chip preparation method according to any one of the technical solutions of the first aspect.
As a preferred embodiment of the present application, the wafer body has a thickness of no more than 35 microns.
Compared with the prior art, the technical solutions provided in the embodiments of the present application have the same beneficial effects as the technical solutions provided in the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a chip manufacturing method according to an embodiment of the present disclosure;
fig. 2 to fig. 7 are cross-sectional views illustrating a chip manufacturing method according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.
The applicant has found through research that in the prior art, it is difficult to obtain a chip with a smaller size and the preparation process is complicated.
The embodiment that this application provided fixes through first fixed bed can prevent at the in-process to the wafer body back attenuate, wafer body warpage, then sets up the second fixed bed through the second metal level lower surface at the wafer body back in order to prevent to get rid of first fixed bed, wafer body warpage, get rid of behind the first fixed bed, and right the wafer body is cut apart the processing, obtains a plurality of chips, and the technical scheme process that this application provided is simple, and can obtain miniaturized chip in batches.
Fig. 1 is a schematic flow chart of a chip manufacturing method according to an embodiment of the present application;
step S01, providing a wafer body, wherein a plurality of chips are formed on the wafer body;
step S02, forming metal posts above the first metal layers arranged at intervals on the front surface of the wafer body;
step S03, arranging a first fixed layer covering the metal column on the front surface of the wafer body;
step S04, thinning the back of the wafer body and forming a second metal layer on the back of the wafer body;
step S05, arranging a second fixed layer on one surface of the second metal layer far away from the wafer body, and then removing the first fixed layer;
and step S06, performing segmentation processing on the wafer body to obtain a plurality of chips.
Fig. 2 to 7 are schematic cross-sectional views illustrating intermediate structures in an embodiment of a method for manufacturing a chip provided by the present application, and the embodiment is described in detail below with reference to fig. 1 and fig. 2 to 7.
With reference to fig. 1 and fig. 2, step S01 is executed to provide a wafer body 01, a first metal layer 02 is disposed on the upper surface of the wafer body 01 at intervals, the first metal layer 01 is an aluminum metal layer, and a plurality of chips are formed on the wafer body 01, wherein the chips may be MOS transistors including a source, a drain, and a gate, or other types of chips.
With reference to fig. 1 and fig. 3, step S02 is performed, and a metal pillar 03 is formed above the first metal layer 01 by ball-planting or wire-bonding, in the embodiment of the present invention, the metal pillar 03 is a copper metal pillar, and may also be a metal pillar of another metal, which is not limited in the embodiment of the present invention, if the chip is a double-drain multi-channel MOS, the double-drain multi-channel MOS includes a source S1, a source S2, a drain D, and a gate G1, a gate G2 (not shown), the source S1, the source S2, the gate G1, and the gate G2 (not shown) of the MOS are disposed on the front surface of the wafer body 01 and respectively led out through the metal pillar 03, and the drain D is disposed on the back surface of the wafer body 01 and.
Referring to fig. 1 and 4, step S03 is executed to dispose a first fixing layer 04 covering the metal pillar 03 on the front surface of the wafer body 01, where the first fixing layer 04 has a film-like structure, a viscous material is disposed on a surface of the first fixing layer 04 close to the wafer body 01, and the first fixing layer 04 is adhered to the front surface of the wafer body 01 by the viscous material, so that the wafer body 01 can be thinned by the first fixing layer 04, and the wafer body 01 can be prevented from warping.
With reference to fig. 1 and 5, step S04 is performed to thin the back surface of the wafer body 01, and form a second metal layer 05 on the back surface of the wafer body 01, where the second metal layer 05 includes an additional nickel-silicon metal layer and a copper metal layer in sequence from inside to outside, so that heat dissipation and impedance reduction can be performed better.
With reference to fig. 1 and fig. 6, step S05 is performed to dispose the second fixing layer 06 on the side of the second metal layer 05 away from the wafer body 01, and then remove the first fixing layer 04; the second fixing layer 06 is a film-like structure, the second fixing layer 06 is adhered to the back surface of the wafer body 01 by an adhesive material, and the wafer body 01 can be prevented from warping when the first fixing layer 04 is removed by the second fixing layer 06.
With reference to fig. 1 and 7, step S06 is executed to perform a dicing process on the wafer body 01 to obtain a plurality of chips, and specifically, the diced chips are sucked from the second fixing layer 06 by the suction pen, so as to obtain miniaturized chips, wherein the thickness of the wafer body 01 is not greater than 35 μm.
The embodiment that this application provided fixes through first fixed bed can prevent at the in-process to the wafer body back attenuate, wafer body warpage, then sets up the second fixed bed through the second metal level lower surface at the wafer body back in order to prevent to get rid of first fixed bed, wafer body warpage, get rid of behind the first fixed bed, and right the wafer body is cut apart the processing, obtains a plurality of chips, and the technical scheme process that this application provided is simple, and can obtain miniaturized chip in batches.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A method for preparing a chip is characterized by comprising the following steps,
providing a wafer body, wherein a plurality of chips are formed on the wafer body;
forming metal columns above first metal layers arranged on the front surface of the wafer body at intervals;
arranging a first fixing layer covering the metal column on the front surface of the wafer body;
thinning the back of the wafer body, and forming a second metal layer on the back of the wafer body;
arranging a second fixed layer on one surface of the second metal layer, which is far away from the wafer body, and then removing the first fixed layer;
and carrying out segmentation processing on the wafer body to obtain a plurality of chips.
2. The method of claim 1, wherein the first anchor layer and the second anchor layer are the same material.
3. The method of claim 2, wherein the first anchor layer and the second anchor layer are made of a film-like material.
4. The method for manufacturing a chip as claimed in claim 3, wherein the first fixing layer and the second fixing layer are provided with adhesive materials on their surfaces close to the wafer body, and the first fixing layer and the second fixing layer are respectively adhered to the front surface and the back surface of the wafer body by the adhesive materials.
5. The method of claim 1, wherein the second metal layer is formed on the back surface of the wafer body by electroplating.
6. The method for manufacturing a chip according to claim 1, wherein the first metal layer is an aluminum metal layer, the second metal layer sequentially comprises an additional nickel-silicon metal layer and a copper metal layer from inside to outside, and the metal pillar is a copper metal pillar.
7. A method for preparing a chip as claimed in any one of claims 1 to 4, characterized in that the chip is a MOS transistor.
8. A chip produced by a method for producing a chip according to any one of claims 1 to 7.
9. The chip of claim 9, wherein the wafer native has a thickness of no greater than 35 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010708169.8A CN111816602A (en) | 2020-07-21 | 2020-07-21 | Chip preparation method and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010708169.8A CN111816602A (en) | 2020-07-21 | 2020-07-21 | Chip preparation method and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111816602A true CN111816602A (en) | 2020-10-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010708169.8A Pending CN111816602A (en) | 2020-07-21 | 2020-07-21 | Chip preparation method and chip |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499579A (en) * | 2002-10-25 | 2004-05-26 | ��ʽ���������Ƽ� | Method for mfg. semiconductor circuit element |
| CN103811536A (en) * | 2014-01-24 | 2014-05-21 | 南通富士通微电子股份有限公司 | Wafer thinning structure for wafer level packaging technology |
| CN105448854A (en) * | 2014-08-29 | 2016-03-30 | 万国半导体股份有限公司 | Wafer manufacturing method for thickly-back-metalized molded chip-scale package |
| CN110838439A (en) * | 2019-11-01 | 2020-02-25 | 上海韦尔半导体股份有限公司 | Wafer slicing method and chip |
| CN210837765U (en) * | 2019-12-10 | 2020-06-23 | 上海韦尔半导体股份有限公司 | Semiconductor device structure and electronic product |
| JPWO2021166963A1 (en) * | 2020-02-21 | 2021-08-26 |
-
2020
- 2020-07-21 CN CN202010708169.8A patent/CN111816602A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499579A (en) * | 2002-10-25 | 2004-05-26 | ��ʽ���������Ƽ� | Method for mfg. semiconductor circuit element |
| CN103811536A (en) * | 2014-01-24 | 2014-05-21 | 南通富士通微电子股份有限公司 | Wafer thinning structure for wafer level packaging technology |
| CN105448854A (en) * | 2014-08-29 | 2016-03-30 | 万国半导体股份有限公司 | Wafer manufacturing method for thickly-back-metalized molded chip-scale package |
| CN110838439A (en) * | 2019-11-01 | 2020-02-25 | 上海韦尔半导体股份有限公司 | Wafer slicing method and chip |
| CN210837765U (en) * | 2019-12-10 | 2020-06-23 | 上海韦尔半导体股份有限公司 | Semiconductor device structure and electronic product |
| JPWO2021166963A1 (en) * | 2020-02-21 | 2021-08-26 |
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