CN111814416B

CN111814416B - Method for automatically converting ASIC memory into IP core of FPGA and readable medium

Info

Publication number: CN111814416B
Application number: CN202010504751.2A
Authority: CN
Inventors: 王书浩
Original assignee: Shanghai Saifang Technology Co ltd
Current assignee: Shanghai Saifang Technology Co ltd
Priority date: 2020-06-05
Filing date: 2020-06-05
Publication date: 2023-08-25
Anticipated expiration: 2040-06-05
Also published as: CN111814416A

Abstract

The invention relates to the technical field of integrated circuits, in particular to a method for automatically converting an ASIC memory into an IP core of an FPGA and a readable medium, aiming at the memroy with the bin of the ASIC, the invention is not as flexible as the memory with the bin in the ASIC because of the special process of the FPGA, the invention uses python to process texts and splice and convert the memory with special requirements, the problem is reasonably solved, dcp, stub and xci files in IP needed by the prototype verification of the FPGA can be generated, the prototype synthesis, the layout and the wiring of the follow-up FPGA are all very important helpful, and the prototype verification of the whole FPGA is very important helpful. According to the invention, the bram and the dram of the FPGA can be automatically generated according to the memory size of the ASIC, the memory model of the emulgator can be generated, the simulation file can be automatically generated, and the generated memory is self-checked. Prototype verification can be performed more quickly and intelligently. And simultaneously, the timing sequence convergence of the FPGA can be better carried out.

Description

Method for automatically converting ASIC memory into IP core of FPGA and readable medium

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a method for automatically converting an ASIC memory into an IP core of an FPGA and a readable medium.

Background

FPGA (Field-programmable gate array), a Field-programmable gate array, is a product of further development on the basis of programmable devices such as PAL, GAL, CPLD. The programmable device is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device.

An ASIC is considered to be an integrated circuit designed for a specific purpose. Refers to integrated circuits that are designed and manufactured to meet the needs of a particular user and a particular electronic system. The ASIC is characterized by being oriented to the requirements of specific users, and has the advantages of smaller volume, lower power consumption, improved reliability, improved performance, enhanced confidentiality, reduced cost and the like compared with a general integrated circuit during mass production.

In ASIC design, the FPGA is often used for prototype verification. FPGA verification is an important link for ASIC design, and 50-80% of the whole process of the ASIC can be said to be completed after FPGA verification is completed. In ASIC design, there are a large number of memories (memories) of different types, and the FPGA needs to be replaced manually step by step when performing prototype verification, which consumes a large amount of time for research and development personnel, and leads to lengthening of verification period, lengthening of research and development period of the whole chip and delay of the time to market of the chip when performing prototype verification. For example, when I do a large video chip, there are hundreds of different types of memory in the chip, and the manual replacement needs about 1 week, and it takes days to verify the correctness after the replacement, but by using the technology, 8 hours can be completely replaced.

Python: is a high-level scripting language that combines interpretive, compiled, interactive, and object-oriented. The text file is handled predominantly.

Tcl: a scripting language supporting FPGA development tools vivado.

The invention is based on the cross development of python and tcl, uses python to process a large number of text files, and uses tcl to perform fpga development.

Disclosure of Invention

Aiming at the defects of the prior art, the invention discloses a method for automatically converting an ASIC memory into an IP core of an FPGA and a readable medium thereof, which are used for solving the problems that the prior prototype design adopts manual replacement, which leads to more and more work, research personnel operate on a computer side, occasional artificial errors can lead to the whole verification progress, the prior program operation uses a plurality of scripts to execute, only parameters of a memory model of the ASIC are simply extracted to generate a memory code which can be synthesized by the FPGA, thus a large amount of lut resources of the FPGA are occupied, thereby wasting BRAM in the FPGA, leading to poor time sequence analysis and unstable functions and bottleneck in performance when the FPGA performs prototype verification.

The invention is realized by the following technical scheme:

in a first aspect, the present invention discloses a method for automatically transferring an ASIC memory to an IP core of an FPGA, the method comprising the steps of:

s1, scanning a memory file used by an ASIC by using a python script language, capturing port information, and automatically screening the type of the memory;

s2, extracting names of memory packages, and generating a list of memory types and a list of package names;

s3, comparing the transmission parameters with a list of memory types by using a python script, and selecting the memory type to be used;

s4, selecting a memory IP file in the FPGA according to the memory type by the python script, and modifying parameters in an IP file in the FPGA;

s5, calculating the number of BRAMs according to the memory size, and generating an IP list file after modifying parameters;

s6, calling an embedded tcl script by the python script, generating a memory IP of the FPGA according to the IP list file, and automatically copying to generate dcp to a memory_dcp directory;

s7, processing the memory package name extracted by the ASIC through the python script to generate a model with the same port information;

s8, instantiating the memory ip generated by the FPGA again, and carrying out batch processing on the memory with the bin;

s9, generating a memory required by an Emulator through a python script;

s10, the python script runs a corresponding test program, performs self-test on the memory, prints the 'Pass' with the same function and prints the 'Fail' with the different functions.

Further, in the step S3, the optional memory type is a memory of a dram, a bram or an emulgator type, and the memory of the emulgator type is a memory built by a two-dimensional array, which is completely different from a memory model of the dram and the bram.

Further, when the type of memory is selected, according to the size of the memory, dram is selected by default below 1K, and bram is selected above 1K.

Further, the selection of the memory of the emulgator type is selected according to the parameters transmitted by the python script, or the simulation ram model required by the emulgator is automatically generated while the dram and the bram are generated, and the simulation ram model is put into a separate emulgator catalog.

Furthermore, when the FPGA performs verification, the script uniformly calls the dcp file by the memory_dcp directory to be used as verification.

In a second aspect, the present invention discloses a readable medium, including a processor and a memory storing execution instructions, where when the processor executes the execution instructions stored in the memory, the processor hardware executes the method for automatically transferring the ASIC memory of the first aspect to the IP core of the FPGA.

The beneficial effects of the invention are as follows:

according to the invention, the automation level is better, the bram and the dram of the FPGA can be automatically generated according to the memory size of the ASIC, the memory model of the simulator can be generated, the simulation file can be automatically generated, and the generated memory is subjected to self-inspection. Prototype verification can be performed more quickly and intelligently. And simultaneously, the timing sequence convergence of the FPGA can be better carried out.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic step diagram of a method for automatically transferring ASIC memory to an IP core of an FPGA;

fig. 2 is a schematic diagram of the implementation of the present embodiment.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

The invention discloses a method for automatically transferring an ASIC memory to an IP core of an FPGA, which is shown in figure 1, and comprises the following steps:

s9, generating a memory required by an Emulator through a python script;

In S3, the optional memory type is a memory of the dram, the bram or the emulgator type, and the memory of the emulgator type is built by a two-dimensional array, which is completely different from the memory model of the dram and the bram.

When the type of the memory is selected, according to the size of the memory, the default is selected to be dram below 1K, and the default is selected to be bram above 1K.

The selection of the memory of the emulgator type is selected according to the parameters transmitted by the python script, or the simulation ram model required by the emulgator is automatically generated at the same time of generating the dram and the bram and is put into a separate emulgator catalog.

When the FPGA performs verification, the script uniformly calls the dcp file by the memory_dcp directory to be used as verification.

According to the embodiment, the method and the device can automatically generate the bram and the dram of the FPGA according to the memory size of the ASIC, can generate a memory model of an emulgator, can automatically generate a simulation file, and perform self-test on the generated memory. Prototype verification can be performed more quickly and intelligently. And simultaneously, the timing sequence convergence of the FPGA can be better carried out.

Example 2

Referring to fig. 2, this embodiment illustrates a process of IP core router generation, which is specifically as follows:

1: memory list of ASIC: the python script language scans the memory file used by the ASIC, captures port information, and automatically screens the type of the memory. At the same time, the names of the memory packages are extracted, a list of memory types is generated, and a list of package names is generated, corresponding codes please see later pictures.

2: memory IP type: the python script compares the list of transfer parameters (depth, bit width) and memory types, selects either dram or bram or memory of the emulgator type, and the memory model of dram and bram is quite different because the emulgator needs to go to memory built with two-dimensional arrays. The selection method can select the dram according to the size of the memory, select the ram with a default value below 1K and select the bram with a default value above 1K, select the emulgator according to the parameters transmitted by the python script, or automatically generate the simulation ram model required by the emulgator while generating the dram and the bram, and put the simulation ram model into a separate emulgator catalog

3: FPGA memory IP modification: the script selects a file of a memory IP inside the FPGA according to a memory type (single_port, true_dual_port, simple_dual), modifies parameters (write_rate, enable_rate, memory_type, wirte_width) inside an IP file inside the FPGA, calculates the number of BRAMs according to the memory size, and generates an IP list file after modifying the parameters;

4: FPGA memory IP generation: and the python calls an embedded tcl script, generates a memory IP of the FPGA according to the IP list file, then uniformly and automatically copies the generated dcp to a memory_dcp directory, and when the FPGA is verified later, the script can uniformly call the dcp file, so that the management is convenient.

5: memory encapsulation of FPGA: python processes the memory package name extracted by ASIC to generate a model with the same port information, again instantiates the memory ip generated by FPGA, processes the memory with the bits in batches, and processes the useless port to avoid unnecessary warning generated in prototype verification.

6: memory of the emulgator is generated: the python generates the memory needed by the Emulator, and finally automatically generates the memory of the Emulator for selection for standby;

7: self-test: python runs the corresponding test program to self-test memory, print "Pass" and print "Fail" with different functions.

The method and the device are used for processing the memroy with the bin of the ASIC, and are not as flexible as the memory with the bin of the ASIC due to the special process of the FPGA;

the embodiment can generate dcp, stub and xci files in the IP needed for the prototype verification of the FPGA, which is very important for the prototype synthesis, layout and wiring of the subsequent FPGA, and the prototype verification of the whole FPGA.

Example 3

The embodiment discloses a video chip project recently made by the inventor, the memory of the chip has hundreds, and the memory is manually replaced in the early stage by being verified by the FPGA and the emulgator, 50 memories are replaced, 8 hours are spent, and a lot of time is delayed for individuals. All written automation scripts are processed, and a makefile script is made. Directly with the make xci command:

1: gen_xci.py grabs the memory parameter model of the asic

2: xci_list.py to generate a list of parameters

3: run_ip_vivado.tcl generates a memory ip core of the FPGA

4: memory model with embedded meke emu call gen_emu. Py generating emulators

5: built-in make check, call check. Py, auto-check correct error to generate memory model

6: the make_dcp_stub is embedded and the copy generates a good dcp to the corresponding directory for continued use in later verification.

The command is used for working at 6 pm, all the generation and verification are completed at 9 am the next day, and the developer does not need to be kept at the computer side, so that other verification works can be completed. Greatly improves the working efficiency.

Example 4

The embodiment discloses a readable medium, which comprises a processor and a memory storing execution instructions, wherein when the processor executes the execution instructions stored in the memory, the processor hardware executes a method for automatically transferring an ASIC memory to an IP core of an FPGA.

As the current chip design is more and more complex, the task of prototype verification is more and more difficult, and after the memory ip of the FPGA is generated, the memory model required by the emulators can be generated. Meanwhile, the model is also suitable for the FPGA, so that the verification efficiency of the ASIC is improved.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for automatically transferring ASIC memory to an IP core of an FPGA, comprising the steps of:

s1, scanning a memory file used by an ASIC (application specific integrated circuit) by using a python script language, capturing port information, and automatically screening the type of the memory; s2, extracting names of memory packages, and generating a list of memory types and a list of package names; s3, comparing a list of transmission parameters and types of memory by using a python script, and selecting the type of memory to be used, wherein in S3, the type of the optional memory is a memory of a dram, a bram or an emulgator type, and the memory of the emulgator type is a memory built by a two-dimensional array, which is completely different from a memory model of the dram and the bram; s4, the python script selects a memory IP file in the FPGA according to the memory type, and modifies parameters in the IP file in the FPGA; s5, calculating the number of BRAMs according to the memory size, and generating an IP list file after modifying parameters; s6, calling an embedded tcl script by the python script, generating a memory IP of the FPGA according to the IP list file, and automatically copying to generate dcp to a memory_dcp directory; s7, processing the memory package name extracted by the ASIC through the python script to generate a model with the same port information; s8, instantiating the memory ip generated by the FPGA again, and carrying out batch processing on the memory with the bin; s9, generating a memory required by an Emulator through a python script; s10, the python script runs a corresponding test program, performs self-test on the memory, prints the 'Pass' with the same function and prints the 'Fail' with the different functions.

2. The method for automatically transferring ASIC memory to IP core of FPGA as in claim 1, wherein when selecting the type of memory, according to the size of memory, 1K or less default is selected for dram, and 1K or more is selected for bram.

3. The method for automatically transferring ASIC memory to IP core of FPGA according to claim 1, wherein the selection of the memory of the Emulator type is selected according to the parameters transmitted by the python script, or the simulation ram model required by the emulgator is automatically generated at the same time of generating dram and bram and is put in a separate emulgator catalog.

4. The method for automatically transferring ASIC memory to IP core of FPGA according to claim 1, wherein when the FPGA performs verification, script is unified to call dcp file from memory_dcp directory for verification.

5. A computer readable medium comprising a processor and a memory storing execution instructions that, when executed by the processor, cause the processor hardware to perform a method of automatically transferring ASIC memory to an IP core of an FPGA as claimed in any of claims 1 to 4.