CN111812902A

CN111812902A - Array substrate, display panel and display device

Info

Publication number: CN111812902A
Application number: CN202010749492.XA
Authority: CN
Inventors: 金慧俊
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2020-07-30
Filing date: 2020-07-30
Publication date: 2020-10-23
Anticipated expiration: 2040-07-30
Also published as: CN111812902B

Abstract

The application discloses array substrate, display panel and display device. The array substrate comprises a display area and a non-display area surrounding the display area; the display area comprises a plurality of gate lines; the non-display area comprises a shift register group and at least one stage of virtual shift register unit cascaded with at least one end part of the shift register group, the shift register group comprises a plurality of cascaded shift register units, and the number of transistors, the number of capacitors and the electrical connection relationship among all components in each virtual shift register unit and each shift register unit are the same; the channel width-length ratio of the first output driving transistor in the virtual shift register unit is smaller than that of the second output driving transistor in the shift register unit, so that the light transmittance of the virtual shift register unit is larger than that of the shift register unit. According to the embodiment of the application, the narrow frame can be realized without influencing the curing effect of the frame glue.

Description

Array substrate, display panel and display device

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

With the continuous development of electronic technology, various displays have come along, and accordingly, the display technology has been changing day by day. In many display technologies, the narrow frame of the display panel is one of the mainstream display effects that people pursue at present, and the display panel with the narrow frame can provide better display effect and better visual experience, and becomes a hot spot for research in the display field.

The display panel may include a straight line segment edge and an arc-shaped edge, and the virtual shift register in the gate driving circuit is generally adjacent to the arc-shaped edge of the display panel, but the existing virtual shift register cannot be directly arranged below the sealant at the arc-shaped edge of the display panel, which is not beneficial to realizing a narrow frame of the display panel.

Content of application

The embodiment of the application provides an array substrate, a display panel and a display device.

In a first aspect, an embodiment of the present application provides an array substrate, which includes: a display area and a non-display area surrounding the display area; the display area comprises a plurality of gate lines; the non-display area comprises a shift register group and at least one stage of virtual shift register unit cascaded with at least one end part of the shift register group, the shift register group comprises a plurality of cascaded shift register units, and the output end of each shift register unit is electrically connected with the corresponding gate line; each virtual shift register unit and each shift register unit respectively comprise a plurality of transistors and a plurality of capacitors, and the number of the transistors and the number of the capacitors in each virtual shift register unit and each shift register unit are the same as well as the electrical connection relationship among all components; the virtual shift register unit comprises a first output driving transistor, the shift register unit comprises a second output driving transistor which is connected with the first output driving transistor in the same relation, and the channel width-length ratio of the first output driving transistor is smaller than that of the second output driving transistor, so that the light transmittance of the virtual shift register unit is larger than that of the shift register unit.

In a second aspect, the present application provides a display panel, which includes the array substrate according to the embodiments of the first aspect.

In a third aspect, the present application provides a display device comprising the display panel according to the embodiment of the second aspect.

According to the array substrate, the display panel and the display device provided by the embodiment of the application, in order to improve the light transmittance of the virtual shift register unit, the channel width-to-length ratio of the first output driving transistor in the virtual shift register unit is adjusted. Specifically, the channel width-to-length ratio of the first output driving transistor in the virtual shift register unit is set to be smaller than the channel width-to-length ratio of the second output driving transistor in the shift register unit, so that the light transmittance of the virtual shift register unit is greater than that of the shift register unit. Because the light transmittance of the virtual shift register unit is larger, the virtual shift register unit can be directly arranged below the frame glue, and the narrow frame can be realized without influencing the curing effect of the frame glue.

Drawings

Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an array substrate according to another embodiment of the present application;

FIG. 3 is a schematic diagram of a circuit structure of a shift register unit according to an embodiment of the present application;

FIG. 4 illustrates a schematic diagram of a transistor provided in accordance with an embodiment of the present application;

FIG. 5 shows a schematic diagram of a shift register cell provided according to an embodiment of the present application;

FIG. 6 illustrates a schematic diagram of a virtual shift register cell provided in accordance with an embodiment of the present application;

FIG. 7 is a schematic diagram of a virtual shift register cell provided in accordance with another embodiment of the present application;

FIG. 8 illustrates a schematic cascade of a shift register cell and a dummy shift register cell provided according to an embodiment of the present application;

FIG. 9 shows a schematic cascade diagram of a shift register cell and a dummy shift register cell provided in accordance with another embodiment of the present application;

FIG. 10 is a schematic diagram of a display panel according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a display panel according to another embodiment of the present application;

fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The embodiments will be described in detail below with reference to the accompanying drawings.

Embodiments of the present invention provide an array substrate, which may be in various forms, some examples of which will be described below.

Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application. As shown in fig. 1, the array substrate 100 includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a plurality of gate lines 10 extending in a first direction X and a plurality of data lines 20 extending in a second direction Y. The second direction Y intersects the first direction X. For example, the second direction Y may be perpendicular to the first direction X, the first direction X may be a row direction, and the second direction Y may be a column direction.

The shape of the array substrate 100 may not be rectangular. For example, the array substrate 100 may include at least one segment of the shaped edge a1, and the extending direction of the shaped edge a1 intersects both the first direction X and the second direction Y. Illustratively, the shaped edge a1 may be a rounded edge. The dummy shift register unit 41 in the array substrate 100 may be disposed adjacent to the profiled edge.

The non-display area NA includes a shift register group 30 and at least one stage of dummy shift register units 41 cascaded with at least one end portion of the shift register group 30. The shift register group 30 includes a plurality of cascaded shift register units 31, and output terminals of the shift register units 31 are electrically connected to the gate lines 10 corresponding to the shift register units. The number of the shift register units 31 may be the same as the number of the gate lines 10, and one shift register unit 31 is electrically connected to one gate line 10. Each shift register unit 31 supplies a scanning signal to the corresponding gate line 10 through an output terminal.

In the present application, the cascade connection method of the shift register units 31 in the shift register group 30 and the cascade connection method of the dummy shift register units 41 and the shift register units 31 are not limited. In fig. 1 and 2, the cascade relationship of the shift register units 31 in the shift register group 30 and the cascade relationship of the dummy shift register units 41 and the shift register units 31 are not shown, and for this, some specific examples will be provided in the following description of fig. 8 and 9.

Illustratively, the shift register group includes M cascaded shift register units, M is greater than or equal to 2, during forward scanning, the mth stage shift register unit is the last stage shift register unit, and during reverse scanning, the first stage shift register unit is the last stage shift register unit. If the last stage shift register unit is not provided with a pull-down signal, the last stage shift register unit may be unstable, for example, the last stage shift register unit may repeatedly output the scan signal to its corresponding gate line.

In some embodiments, the pull-down signal may be provided to the last stage shift register unit through the driving chip, but this may cause an increase in output ports of the driving chip. In other embodiments, a dummy shift register unit cascaded with the last stage shift register unit may be provided, so that a pull-down signal can be provided to the last stage shift register unit through the dummy shift register unit without increasing an output port of the driving chip, so as to ensure stability of the last stage shift register unit and prevent the last stage shift register unit from repeatedly outputting a scan signal to its corresponding gate line.

Each of the dummy shift register units 41 and each of the shift register units 31 includes a plurality of transistors and a plurality of capacitors, and the number of transistors, the number of capacitors, and the electrical connection relationship between the components in each of the dummy shift register units 41 and each of the shift register units 31 are the same. That is, the circuit configurations of the dummy shift register units 41 and the shift register units 31 are the same.

The virtual shift register unit 41 includes a first output driving transistor, the shift register unit 31 includes a second output driving transistor connected to the first output driving transistor in the same relationship, and the channel width-to-length ratio of the first output driving transistor is smaller than that of the second output driving transistor, that is, the layout area occupied by the first output driving transistor is smaller than that occupied by the second output driving transistor, so that the virtual shift register unit has more light-transmitting regions, and the light transmittance of the virtual shift register unit is greater than that of the shift register unit.

In the embodiment of the present application, the number of transistors and the number of capacitors in the dummy shift register unit 41 and the shift register unit 31 are not specifically limited, and the electrical connection relationship between the components in the dummy shift register unit 41 and the shift register unit 31 is also not specifically limited.

Illustratively, if a first electrode of one of the transistors of the dummy shift register unit 41 is electrically connected to the clock signal terminal and a second electrode of the one transistor is electrically connected to the output terminal of the dummy shift register unit 41, the one transistor may be a first output driving transistor of the dummy shift register unit 41. Similarly, if a first electrode of one of the transistors in the shift register unit 31 is electrically connected to the clock signal terminal, and a second electrode of the one of the transistors is electrically connected to the output terminal of the shift register unit 31, the transistor may be a second output driving transistor of the shift register unit 31.

In order to clearly illustrate the technical solutions of the embodiments of the present application, the present application exemplarily provides a specific circuit structure of a shift register unit. Fig. 3 shows a circuit configuration diagram of a shift register unit of 9T 2C.

The shift register circuit of 9T2C shown in fig. 3 includes 9 transistors (T) and 2 capacitance elements (C). The 9 transistors are a transistor T0 to a transistor T8, respectively, and the 2 capacitance elements are a capacitance element C1 and a capacitance element C2, respectively. Each transistor includes a gate terminal, a first pole, and a second pole. Each capacitor includes a first plate and a second plate.

The gate terminal of the transistor T0 is electrically connected to the initialization signal terminal SET, the first terminal of the transistor T0 is electrically connected to the high-potential signal terminal DIR1, and the second terminal of the transistor T0 is electrically connected to the node P.

A gate terminal of the transistor T1 is electrically connected to the gate signal terminal Gn +1, a first terminal of the transistor T1 is electrically connected to the node P, and a second terminal of the transistor T1 is electrically connected to the low potential signal line DIR 2.

A capacitor element C1 is arranged between the transistor T2 and the clock signal terminal CKB, wherein a first polar plate of the capacitor element C1 is electrically connected with the clock signal terminal CKB, and a second polar plate of the capacitor element C1 is electrically connected with the grid terminal of the transistor T2; a first pole of the transistor T2 is electrically connected to the node P, and a second pole of the transistor T2 is electrically connected to the low potential signal terminal VGL.

A gate terminal of the transistor T3 is electrically connected to the node P, and a capacitive element C1 is present between a first terminal of the transistor T3 and the clock signal terminal CKB, wherein a first plate of the capacitive element C1 is electrically connected to the clock signal terminal CKB, a second plate of the capacitive element C1 is electrically connected to a first electrode of the transistor T3, and a second plate of the transistor T3 is electrically connected to the low potential signal line VGL.

The gate terminal of the transistor T4 is electrically connected to the node P, the first terminal of the transistor T4 is electrically connected to the clock signal terminal CKB, and the second terminal of the transistor T4 is connected to the gate signal output terminal GOUT; a capacitor C2 is present between the gate terminal of the transistor T4 and the second pole thereof, wherein the first plate of the capacitor C2 is electrically connected to the gate terminal of the transistor T4, and the second plate of the capacitor C2 is electrically connected to the second pole of the transistor T4.

The gate terminal of the transistor T5 is electrically connected to the first pole of the transistor T3, the first pole of the transistor T5 is electrically connected to the gate signal output terminal GOUT, and the second pole of the transistor T5 is electrically connected to the low potential signal terminal VGL.

The gate terminal of the transistor T6 is electrically connected to the clock signal terminal CK, the first terminal of the transistor T6 is electrically connected to the gate signal output terminal GOUT, and the second terminal of the transistor T6 is electrically connected to the low potential signal terminal VGL.

The gate terminal of the transistor T7 is electrically connected to the RESET signal terminal RESET, the first terminal of the transistor T7 is electrically connected to the node P, and the second terminal of the transistor T7 is electrically connected to the low potential signal terminal VGL.

The gate terminal of the transistor T8 is electrically connected to the RESET signal terminal RESET, the first terminal of the transistor T8 is electrically connected to the gate signal output terminal GOUT, and the second terminal of the transistor T8 is electrically connected to the low potential signal terminal VGL.

Taking the circuit structures of the dummy shift register unit 41 and the shift register unit 31 as the 9T2C circuit shown in fig. 3 as an example, the gate signal output terminal GOUT is the output terminals of the dummy shift register unit 41 and the shift register unit 31. The first pole of the transistor T4 shown in fig. 3 is electrically connected to the clock signal terminal CKB, the second pole of the transistor T4 is electrically connected to the gate signal output terminal GOUT, and the transistor T4 is the first output driving transistor of the dummy shift register unit 41 and the second output driving transistor of the shift register unit 31.

The variation of the channel width-to-length ratio of the transistors affects the operation performance of the shift register unit, and the shift register unit 31 provides effective driving signals to the display area AA, so that the channel width-to-length ratio of the second output driving transistor in the shift register unit 31 can be kept unchanged, and only the channel width-to-length ratio of the first output driving transistor in the dummy shift register unit 41 is changed, so that the channel width-to-length ratio of the first output driving transistor is smaller than that of the second output driving transistor.

Illustratively, as shown in fig. 4, the transistor includes a gate G, a semiconductor portion B, a source S, and a drain D. The distance between the source S and the drain D is the channel length L of the transistor, and the direction perpendicular to L is the channel width W of the transistor. Illustratively, the gate G may be formed of a metal.

It should be noted that there are various specific structures of the transistor, and the transistor shown in fig. 4 is a "comb" transistor. For example, each transistor structure in the dummy shift register unit 41 and the shift register unit 31 may be a "comb" transistor as shown in fig. 4. The transistors in the dummy shift register unit 41 and the shift register unit 31 may also be transistors with other structures, which are not listed herein, and the specific structures of the transistors in the dummy shift register unit 41 and the shift register unit 31 are not limited in this application.

Taking as an example that the circuit structures of the dummy shift register unit 41 and the shift register unit 31 are both the 9T2C circuit shown in fig. 3, and the transistors in the dummy shift register unit 41 and the shift register unit 31 are both the "comb" shaped transistors shown in fig. 4, fig. 5 shows a schematic structural diagram of a shift register unit, and fig. 6 shows a schematic structural diagram of a dummy shift register unit. Fig. 5 and 6 only illustrate the distribution structure of the respective elements, and the connection relationship of the respective elements is not illustrated.

The distribution of the transistors T0-T8 and the capacitors C1, C2 in the shift register unit 31 is shown in fig. 5, in which the transistor T4 is the second output driving transistor 311 of the shift register unit 31. The applicant of the present application finds that the channel width-to-length ratio of a transistor affects the driving capability of the transistor, and generally, the larger the channel width-to-length ratio of the transistor is, the stronger the driving capability thereof is, the driving capability of the transistor with different functions is changed, and the influence on the working performance of the corresponding shift register unit is different. The driving capability of the output driving transistor has a relatively large influence on the working performance of the shift register unit. In order to ensure the operating performance of the shift register unit 31, as shown in fig. 5, the channel width-to-length ratio of the second output drive transistor 311 (transistor T4) in the shift register unit 31 may be set to be larger.

For example, the structures of the transistors T0 to T8 may be all "comb" shaped transistors as shown in fig. 4, the channel lengths of the transistors T0 to T8 may be the same, and the channel widths of the transistors T0 to T8 may be different. Among them, the channel width of the transistor T4 may be the largest, i.e., the layout area occupied by the transistor T4 is the largest with respect to the other transistors.

The distribution of the transistors T0-T8 and the capacitors C1, C2 in the dummy shift register unit 41 is shown in fig. 6, in which the transistor T4 is the first output driving transistor 411 of the dummy shift register unit 41. Fig. 6 may differ from fig. 5 in that the channel width-to-length ratio of first output drive transistor 411 in fig. 6 is smaller than the channel width-to-length ratio of second output drive transistor 311 in fig. 5, that is, the layout area occupied by first output drive transistor 411 in fig. 6 is smaller than the layout area occupied by second output drive transistor 311 in fig. 5. Compared to fig. 5, the dummy shift register cell 41 shown in fig. 6 has a larger light-transmitting area, and it can be understood that before the channel width-length ratio of the first output driving transistor 411 is reduced, the channel width-length ratio of the first output driving transistor 411 is the same as the channel width-length ratio of the second output driving transistor 311, and after the channel width-length ratio of the first output driving transistor 411 is reduced, the reduced area constitutes the light-transmitting area 412 of the dummy shift register cell 41, thereby increasing the light transmittance of the dummy shift register cell 41 so that the light transmittance of the dummy shift register cell 41 is greater than the light transmittance of the shift register cell 31.

The display panel generally includes an array substrate 100 according to an embodiment of the present disclosure and a counter substrate disposed opposite to the array substrate 100, and the array substrate and the counter substrate are bonded by sealant. In the process of curing the sealant, Ultraviolet (UV) is required to cure the sealant. Generally, a gate electrode in a transistor is formed of a metal block through which ultraviolet rays cannot pass. The dummy shift register unit 41 is usually adjacent to the irregular edge a1 of the array substrate 100, and if the dummy shift register unit 41 is directly disposed under the sealant without increasing the light transmittance of the dummy shift register unit 41, the sealant is not cured; the space of the non-display area at the irregular edge a1 is relatively tight, and if the light transmittance of the virtual shift register unit 41 is not increased and the virtual shift register unit 41 is not disposed under the sealant, a narrow frame is not required.

In the embodiment of the present application, the channel width-to-length ratio of the first output driving transistor 411 in the dummy shift register unit 41 is set to be smaller than the channel width-to-length ratio of the second output driving transistor 311 in the shift register unit 31, that is, the area of the light-transmitting region of the dummy shift register unit 41 is larger, so that the light transmittance of the dummy shift register unit 41 is larger than the light transmittance of the shift register unit 31. Because the light transmittance of the virtual shift register unit 41 is relatively high, the virtual shift register unit 41 can be directly placed under the sealant, and the narrow frame can be realized without affecting the curing effect of the sealant.

In some embodiments, the channel length of first output drive transistor 411 in fig. 6 and the channel length of second output drive transistor 311 in fig. 5 may be the same, and the channel width of first output drive transistor 411 in fig. 6 is smaller than the channel width of second output drive transistor 311 in fig. 5.

In some embodiments, referring to fig. 1, the array substrate 100 may further include a dummy gate line 11, and the dummy gate line 11 is located in a non-display region of the array substrate 100. The number of dummy gate lines 11 may be the same as the number of dummy shift register cells 41. One dummy gate line 11 is electrically connected to an output terminal of one dummy shift register unit 41. That is, the output terminal of the dummy shift register cell 41 is electrically connected not only to the dummy gate line 11 but also to the cascade terminal of the shift register cell 31 cascaded thereto. The cascade terminal of the shift register unit 31 can be understood as an input terminal of the shift register unit 31 receiving the initialization signal and the gate signal. For example, as shown in fig. 3, the circuit structure of the shift register unit 31 is that the gate of the transistor T0 in the shift register unit 31 is electrically connected to the initialization signal terminal SET, and the gate of the transistor T1 is electrically connected to the gate signal terminal Gn +1, that is, the gates of the transistors T0 and T1 in the shift register unit 31 may be the cascade terminal of the shift register unit 31. Similarly, the gates of the transistors T0 and T1 in the dummy shift register unit 41 may be the cascade terminals of the dummy shift register unit 41.

In other embodiments, referring to fig. 2, the difference between fig. 2 and fig. 1 is that the array substrate 100 is not provided with the dummy gate lines 11, i.e., the output terminal of the dummy shift register unit 41 is electrically connected to the cascade terminal of the shift register unit 31 cascaded thereto. Usually, the line width of the dummy gate line 11 is about 50um, and if the dummy gate line 11 is disposed, the width of the non-display area NA about 50um needs to be occupied, which is not favorable for realizing a narrow frame. In the present application, the dummy gate line 11 is not provided, which is advantageous for implementing a narrow bezel.

In addition, the inventors of the present application found that, in the case where the dummy gate line 11 is not provided, the output terminal load of the dummy shift register unit 41 is smaller than the output terminal load of the shift register unit 31. The load size will cause the signal output delay at the output terminal to be different, and generally, the larger the load is, the larger the delay is, that is, the output signal output delay at the output terminal of the dummy shift register unit 41 is smaller than the output signal output delay at the output terminal of the shift register unit 31, which affects the display effect. In this application, the channel width-to-length ratio of the first output driving transistor in the virtual shift register unit 41 is smaller than the channel width-to-length ratio of the second output driving transistor in the shift register unit 31, that is, the driving capability of the virtual shift register unit 41 is smaller than that of the shift register unit 31, so that the problem of inconsistent output delay of the output end signal of the virtual shift register unit 41 and the output delay of the output end signal of the shift register unit 31 can be solved, and the display effect is further improved.

In some alternative embodiments, the light-transmissive region 412 of the dummy shift register cell 41 is a continuous light-transmissive region. For example, as shown in fig. 6, the first output driving transistor 411 in the dummy shift register unit 41 may be disposed near an edge of the dummy shift register unit 41. For example, the first output driving transistor 411 is disposed near the upper edge of the dummy shift register unit 41, and thus, the area under the first output driving transistor 411 may constitute the continuous light-transmitting region 412. The continuous light-transmitting area 412 is more likely to transmit ultraviolet light, thereby being more beneficial to improving the curing effect of the sealant.

Still taking the circuit structures of the dummy shift register unit 41 and the shift register unit 31 as the 9T2C circuit shown in fig. 3 as an example, wherein the transistor T4 is the first output driving transistor of the dummy shift register unit 41 and the second output driving transistor of the shift register unit 31, and the capacitor element C2 is electrically connected to the gate of the transistor T4, that is, the capacitor element C2 is the first capacitor 413 of the dummy shift register unit 41 and the second capacitor 312 of the shift register unit 31.

For example, the array substrate 100 may include a clock signal line CKB, and the first pole of the first output driving transistor (the transistor T4) is electrically connected to the clock signal terminal CKB through the clock signal line CKB. The clock signal line CKB couples the gate potential of the first output driving transistor through the parasitic capacitance on the gate of the first output driving transistor, which increases the leakage current of the first output driving transistor, and makes the driving capability of the first output driving transistor unstable. The inventors of the present application have found that increasing the capacitance value of the capacitive element electrically connected to the gate of the first output drive transistor in the dummy shift register cell 41, i.e., setting the capacitance value of the first capacitor 413 of the dummy shift register cell 41 to be larger than the capacitance value of the second capacitor 312 of the shift register cell 31, can reduce the influence caused by the above coupling.

Illustratively, the channel width-to-length ratio of the first output driving transistor 411 is taken as a first value, and the channel width-to-length ratio of the second output driving transistor 311 is taken as a second value. The inventor of the present application finds, through a large amount of experimental data, that when the ratio of the first value to the second value is less than or equal to 0.2, the light transmittance of the virtual shift register unit 41 can be better made to be greater than the light transmittance of the shift register unit 31, so that the virtual shift register unit 41 is directly placed below the sealant, and the curing effect of the sealant can be better ensured.

In addition, as shown in fig. 2, in the case that the output terminal of the dummy shift register unit 41 is electrically connected to only the cascade terminal of the shift register unit 31 cascaded thereto, the inventors of the present application found through a large amount of experimental data that the problem that the output signal delay of the output terminal of the dummy shift register unit 41 is inconsistent with the output signal delay of the output terminal of the shift register unit 31 can be better improved by setting the ratio of the first value to the second value to be less than or equal to 0.2.

Illustratively, the channel width-to-length ratio of the first output driving transistor 411 may be reduced while keeping the channel width-to-length of the second output driving transistor 311 unchanged. For example, the channel width of the first output driving transistor 411 may be reduced. That is, the ratio of the channel width of the first output driving transistor 411 to the channel width of the second output driving transistor 311 may be set to be less than or equal to 0.2.

The inventor of the present application further finds, through a large amount of experimental data, that when the ratio of the capacitance value of the first capacitor 413 to the capacitance value of the second capacitor 312 is greater than or equal to 2, the influence caused by the coupling can be better reduced.

The capacitance value of the capacitor is in direct proportion to the area of the polar plates of the capacitor, and the capacitance value of the capacitor is in inverse proportion to the distance between the polar plates. Illustratively, the first capacitor 413 and the second capacitor 312 each include two opposite plates. For example, the capacitance of the first capacitor 413 may be increased by increasing the plate area of the first capacitor 413. For another example, the capacitance of the first capacitor 413 may be increased by decreasing the distance between the two plates of the first capacitor 413. However, the plate area of the first capacitor 413 is increased, which is relatively easy to realize in terms of process.

Fig. 7 is a schematic structural diagram of a dummy shift register unit according to another embodiment of the present application. Fig. 7 may differ from fig. 5 in that the channel width-to-length ratio of first output drive transistor 411 in fig. 7 is smaller than the channel width-to-length ratio of second output drive transistor 311 in fig. 5, i.e., the layout area occupied by first output drive transistor 411 in fig. 6 is smaller than the layout area occupied by second output drive transistor 311 in fig. 5; the plate area of the first capacitor 413 in fig. 7 is larger than the plate area of the second capacitor 312 in fig. 5, i.e. the layout area occupied by the plate of the first capacitor 413 in fig. 7 is larger than the layout area occupied by the plate of the second capacitor 312 in fig. 5. For example, as shown in fig. 7, the layout area occupied by the first output driving transistor 411 and the first capacitor 413 together may be substantially equal to the layout area occupied by the second output driving transistor 311 and the second capacitor 312 together in fig. 5, and thus, it may not be necessary to increase the overall layout area occupied by the dummy shift register unit 41.

With reference to fig. 7, at least partial regions of the two plates of the first capacitor 413 may be hollow structures. Orthographic projections of the hollowed-out regions 4130 of the two plates of the first capacitor 413 on the array substrate are overlapped, the hollowed-out regions 4130 are bar-shaped regions, and the hollowed-out regions 4130 form the light transmitting region 412 of the array substrate 100. Two polar plates of the first capacitor 413 are arranged to be hollow structures, ultraviolet light can penetrate through the first capacitor 413 when the capacitance value of the first capacitor is increased, and the strip-shaped hollow area 4130 can penetrate through the ultraviolet light more easily, so that the curing effect of the frame glue can be improved.

Illustratively, the two plates of the first capacitor 413 may be non-transparent conductive structures. The plate of the first capacitor 413 is a hollow structure, and it can be understood that each plate of the first capacitor 413 is formed by connecting a plurality of conductive blocks. In some embodiments, as shown in FIG. 7, each plate of the first capacitor 413 comprises three conductive bumps 4132, and the width d of each conductive bump 4132 may be less than or equal to 40 μm. The hollowed-out region 4130 may be located between two adjacent conductive blocks 4132.

In some alternative embodiments, as shown in fig. 1 or fig. 2, the non-display area NA may include a frame glue area NA1, and the frame glue area NA1 is disposed around the display area AA. A sealant may be coated in the sealant region NA1 to bond the array substrate 100 and the opposite substrate. At least the first capacitor 413 of the dummy shift register unit 41 is located in the frame glue area NA 1. As shown in fig. 7, the first capacitor 413 is a hollow structure, and the first capacitor 413 is disposed in the frame sealant area NA1, so that a narrow frame can be realized without affecting the curing effect of the frame sealant.

In fig. 1 and 2, the frame rubber area NA1 is not provided with a filling pattern, and is only indicated by a wire frame in order to clearly illustrate the technical solution of the embodiment of the present application.

In some alternative embodiments, as shown in fig. 8, the shift register group 30 may include N stages of shift register units 31, where N is a positive integer greater than or equal to 4. Adjacent two-stage shift register units in all odd-numbered stage shift register units from the first-stage shift register unit to the Nth-stage shift register unit are mutually cascaded, for example, the first-stage shift register unit is cascaded with the third-stage shift register unit, and the third-stage shift register unit is cascaded with the fifth-stage shift register unit; and adjacent two stages of shift register units in all the even-numbered stage shift register units are cascaded with each other, for example, the second-stage shift register unit is cascaded with the fourth-stage shift register unit, and the fourth-stage shift register unit is cascaded with the sixth-stage shift register unit.

The array substrate 100 may include at least two dummy shift register units 41. For example, the array substrate 100 includes two dummy shift register units 41, which are a first dummy shift register unit and a second dummy shift register unit. The first virtual stage shift register unit and the N-1 stage shift register unit are cascaded, and the second virtual stage shift register unit and the N stage shift register unit are cascaded.

The cascade connection between the first virtual stage shift register unit and the N-1 stage shift register unit means that the output end OUT of the first virtual stage shift register unit is connected with the cascade end of the N-1 stage shift register unit, and the output end OUT of the N-1 stage shift register unit is connected with the cascade end of the first virtual stage shift register unit. The cascade connection between the second virtual stage shift register unit and the Nth stage shift register unit means that the output end OUT of the second virtual stage shift register unit is connected with the cascade end of the Nth stage shift register unit, and the output end OUT of the Nth stage shift register unit is connected with the cascade end of the second virtual stage shift register unit.

Still taking the circuit structures of the dummy shift register unit 41 and the shift register unit 31 as the 9T2C circuit shown in fig. 3 as an example, the gate of the transistor T0 in the shift register unit 31 can be understood as the initialization signal input terminal Set of the shift register unit 31, and the gate of the transistor T1 can be understood as the gate signal input terminal Gn +1 of the shift register unit 31; similarly, the gate of the transistor T0 in the dummy shift register unit 41 can be understood as the initialization signal input Set of the dummy shift register unit 41, and the gate of the transistor T1 can be understood as the gate signal input Gn +1 of the dummy shift register unit 41. As shown in fig. 8, in particular, the output terminal OUT of the first dummy stage shift register unit may be connected to the gate signal input terminal Gn +1 of the N-1 th stage shift register unit, and the output terminal OUT of the N-1 th stage shift register unit is connected to the initialization signal input terminal Set of the first dummy stage shift register unit; the output end OUT of the second virtual level shift register unit is connected with the gate signal input end Gn +1 of the Nth level shift register unit, and the output end OUT of the Nth level shift register unit is connected with the initialization signal input end Set of the second virtual level shift register unit.

During forward scanning, the N-1 st stage shift register unit provides an initialization signal to the first virtual stage shift register unit, and the N-th stage shift register unit provides an initialization signal to the second virtual stage shift register unit; in the reverse scan, the first dummy stage shift register unit supplies a gate signal to the N-1 th stage shift register unit, and the second dummy stage shift register unit supplies a gate signal to the nth stage shift register unit.

In other alternative embodiments, as shown in fig. 9, the array substrate 100 includes four dummy shift register units 41, which are a first dummy shift register unit, a second dummy shift register unit, a third dummy shift register unit, and a fourth dummy shift register unit. Fig. 9 is different from fig. 8 in that a third dummy stage shift register unit is cascade-connected to the first stage shift register unit, and a fourth dummy stage shift register unit is cascade-connected to the second stage shift register unit.

Still taking the circuit structures of the dummy shift register unit 41 and the shift register unit 31 as the 9T2C circuits shown in fig. 3 as an example, the cascade connection between the third dummy shift register unit and the first stage shift register unit may specifically be that the output terminal OUT of the third dummy shift register unit is connected to the initialization signal input terminal Set of the first stage shift register unit, and the output terminal OUT of the first stage shift register unit is connected to the gate signal input terminal Gn +1 of the third dummy shift register unit. The cascade connection between the fourth virtual shift register unit and the second shift register unit may specifically be that an output end OUT of the fourth virtual shift register unit is connected to an initialization signal input end Set of the second shift register unit, and an output end OUT of the second shift register unit is connected to a gate signal input end Gn +1 of the fourth virtual shift register unit.

During forward scanning, the third virtual stage shift register unit provides an initialization signal for the first stage shift register unit, and the fourth virtual stage shift register unit provides an initialization signal for the second stage shift register unit; in the reverse scanning, the first stage shift register unit supplies a gate signal to the third dummy stage shift register unit, and the second stage shift register unit supplies a gate signal to the fourth dummy stage shift register unit.

Alternatively, as shown in fig. 8 and 9, the array substrate may further include clock signal lines CK1/CK2/CKB1/CKB2 and a RESET signal line RESET. The elements in the dummy shift register unit and the shift register unit are connected to the corresponding signal terminals through the clock signal lines CK1/CK2/CKB1/CKB2 and the RESET signal line RESET.

The application also provides a display panel. Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present application. As shown in fig. 10, a display panel 1000 provided in an embodiment of the present application may include an array substrate 100, a counter substrate 200, and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200. The array substrate 100 is the array substrate according to any of the above embodiments. The opposite substrate 200 may be a color filter substrate.

Fig. 11 is a schematic structural diagram of a display panel according to another embodiment of the present application. As shown in fig. 11, a display panel 1000 provided in an embodiment of the present invention may include an array substrate 100 and a counter substrate 200. The array substrate 100 is the array substrate according to any of the above embodiments. The counter substrate 200 may be a protective cover plate, for example a glass cover plate. The display panel shown in fig. 11 may be an Organic Light-Emitting Diode (OLED) display panel.

It should be understood by those skilled in the art that in other implementations of the present application, the display panel may also be a Micro light emitting diode (Micro LED) display panel, a quantum dot display panel, or the like.

The display panel provided in the embodiments of the present application has the advantages of the array substrate provided in the embodiments of the present application, and specific descriptions of the array substrate in the embodiments above may be specifically referred to, and the details of the embodiments are not repeated herein.

The application also provides a display device which comprises the display panel provided by the application. Referring to fig. 12, fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 12 provides a display device 2000 including a display panel 1000 according to any of the above embodiments of the present application. The embodiment of fig. 12 is described with reference to a mobile phone as an example, and it is understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, comprising:

a display area and a non-display area surrounding the display area;

the display area comprises a plurality of gate lines;

the non-display area comprises a shift register group and at least one stage of virtual shift register unit cascaded with at least one end part of the shift register group, the shift register group comprises a plurality of cascaded shift register units, and the output end of each shift register unit is electrically connected with a corresponding gate line;

each virtual shift register unit and each shift register unit respectively comprise a plurality of transistors and a plurality of capacitors, and the number of the transistors, the number of the capacitors and the electrical connection relationship among the components in each virtual shift register unit and each shift register unit are the same;

the virtual shift register unit comprises a first output driving transistor, the shift register unit comprises a second output driving transistor which is connected with the first output driving transistor in the same relation, and the channel width-length ratio of the first output driving transistor is smaller than that of the second output driving transistor, so that the light transmittance of the virtual shift register unit is larger than that of the shift register unit.

2. The array substrate of claim 1, wherein the dummy shift register cells comprise light transmissive regions, the light transmissive regions being continuous light transmissive regions.

3. The array substrate of claim 2, wherein the dummy shift register unit further comprises a first capacitor electrically connected to the gate of the first output driving transistor, the shift register unit comprises a second capacitor connected to the first capacitor in the same relationship, and the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

4. The array substrate of any one of claims 1 to 3, wherein the channel width and length of the first output driving transistor is a first value, the channel width and length ratio of the second output driving transistor is a second value, and the ratio of the first value to the second value is less than or equal to 0.2.

5. The array substrate of claim 3, wherein a ratio of a capacitance of the first capacitor to a capacitance of the second capacitor is greater than or equal to 2.

6. The array substrate of claim 3, wherein the first capacitor and the second capacitor each comprise two opposite plates, and the plate area of the first capacitor is larger than the plate area of the second capacitor.

7. The array substrate of claim 6, wherein at least some regions of the two plates of the first capacitor are both hollow structures, orthogonal projections of the hollow regions of the two plates of the first capacitor on the array substrate overlap, the hollow regions are bar-shaped regions, and the hollow regions constitute the light-transmitting regions.

8. The array substrate of claim 7, wherein the non-display area comprises a frame glue area, the frame glue area is disposed around the display area, and at least the first capacitor in the dummy shift register unit is located in the frame glue area.

9. The array substrate of claim 1, wherein the array substrate comprises at least a first dummy shift register unit and a second dummy shift register unit;

the first virtual stage shift register unit and the N-1 stage shift register unit are cascaded, the second virtual stage shift register unit and the N stage shift register unit are cascaded, adjacent two stages of shift register units in all odd stage shift register units from the first stage shift register unit to the N stage shift register unit are cascaded mutually, and adjacent two stages of shift register units in all even stage shift register units are cascaded mutually; n is a positive integer greater than or equal to 4.

10. A display panel comprising the array substrate according to any one of claims 1 to 9.

11. A display device characterized by comprising the display panel according to claim 10.