CN111786604A - Permanent magnet synchronous motor finite set model prediction control method based on multi-core parallel computation - Google Patents
Permanent magnet synchronous motor finite set model prediction control method based on multi-core parallel computation Download PDFInfo
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Abstract
A permanent magnet synchronous motor finite set model prediction control method based on multi-core parallel computation comprises two processing cores CPU1 and CPU2, an AD conversion module, current-voltage conversion and Clarke conversion in a single-core sequential control strategy are distributed to CPU1, an eQEP module, rotation speed position computation, Park inverse conversion and back electromotive force computation are distributed to CPU2, and meanwhile, a voltage vector V in the single-core sequential control strategy is distributed to CPU20～V7The prediction process, the cost function and the comparison optimization process are distributed to the CPU1 and the CPU2 respectively, namely, a dual-core parallel control strategy of the CPU1 and the CPU2 FCS-MPC is formed, and data exchange is carried out between the two control strategies. On the basis of an FCS-MPC dual-core parallel control strategy, the prediction, evaluation and optimization processes of partial voltage vectors are distributed into CLA cores, so that a four-core parallel control strategy of 'double CPUs + double CLAs' is realized. The control method can maintain the control performance and control characteristics of the original algorithmOn the basis of points, the algorithm execution time is effectively reduced.
Description
Technical Field
The invention belongs to the field of permanent magnet synchronous motor control, and particularly relates to a permanent magnet synchronous motor finite set model prediction control method based on multi-core parallel computation.
Background
The permanent magnet synchronous motor is widely applied to industry and life due to the advantages of high power factor, good safety, low power consumption and the like, and the research on the control strategy of the permanent magnet synchronous motor is gradually deepened. Currently, FCS-MPC is mainly used to realize current inner loop control of a permanent magnet synchronous motor in a permanent magnet synchronous motor drive system control strategy (as shown in FIG. 1) based on FCS-MPC, and a speed outer loop controller can be realized by other control methods including linear control. Although FCS-MPC reduces the complex rotation coordinate transformation, it needs back electromotive force calculation, Clarke transformation, and Park inverse transformation to obtain the input amount of the prediction process due to its high dependency on the motor state variables. The FCS-MPC control strategy mainly comprises a prediction process, a cost function and a comparison optimization. The theoretical basis is as follows.
Under a static coordinate system, the voltage balance equation of the surface-mounted permanent magnet synchronous motor can be expressed as
In the formula, R, L is a motor stator resistance and a stator inductance respectively; i is a stator current vector with i ═ iαiβ]T(ii) a e is the stator back electromotive force vector, e ═ eαeβ]T(ii) a u is the inverter output voltage, and has u ═ uαuβ]TFor all 8 switching states S of the inverter0～S7The value of u corresponds to 8 voltage vectors V0～V7Its value is equal to the DC side voltage udcAnd (4) correlating.
The prediction process of the FCS-MPC in FIG. 1 corresponds to the current prediction equation. According to the forward Euler method, the current prediction equation can be obtained from equation (1), i.e.
In the formula, T is a control period; i (k) is the current vector measurement at time kT; i.e. inAnd (k +1) is a predicted value of the current vector at the time (k +1) T.
The core idea of FCS-MPC is: by predicting the voltage vector V0～V7To the current, the distance current reference value i is screened out*(wherein i*＝[iα *iβ *]T) Most recent current prediction value in(k +1) and corresponding optimum voltage vector VoThe switching state of (2) is output to the inverter. Before the optimization process, a cost function needs to be constructed to evaluate each predicted value, some
The optimum voltage vector is
Wherein argmin gn(k +1) represents the minimum gnVoltage vector V corresponding to (k +1) valuen。
FCS-MPC converts voltage vector V into voltage vector V in each control cycle0～V7Substituting the current prediction formula, evaluating and comparing all current prediction results by adopting a cost function, and outputting a voltage vector of which the cost function reaches the minimum value to the inverter as an optimal vector. The control flow chart is shown in fig. 2.
The flow chart of the FCS-MPC single-core sequence control strategy is shown in FIG. 4, and has three characteristics:
1. the steps are executed in sequence (the variable output by the step is marked below the partial step). When all variables required by the prediction process are obtained, the control flow sequentially enters three steps of prediction process, cost function and comparison optimization (also called prediction, evaluation and optimization) of the FCS-MPC algorithm. In this process, the control algorithm will be on V0～V7And performing prediction, evaluation and optimization one by one to finally obtain the optimal voltage vector.
2. As can be seen by observing each step, most steps have dependency relationships, i.e., after the previous step is completed, the next step can be performed. For example, Clarke conversion must be performed after AD conversion, voltage current conversion; on the other hand, no dependency relationship exists between partial steps, for example, the AD conversion and the eQEP module can run simultaneously, and similarly, Clarke transformation and back electromotive force calculation can be carried out simultaneously, because no variable dependency relationship exists between the AD conversion and the eQEP module.
3. In FCS-MPC algorithm pair V0～V7In two stages of prediction one by one and cost function calculation, 8 voltage vectors have no precedence requirement, and a time sequence dependency relationship does not exist between the voltage vectors.
By analyzing the data dependence relationship of each step in the FCS-MPC, certain basis can be provided for algorithm segmentation. However, the FCS-MPC has a high dependency on data and timing inside, and it is difficult to separate each part that operates independently of each other.
Currently, based on the parallel calculation method of FCS-MPC of TMS320F28379D (as shown in fig. 3), the TMS320F28379D microcontroller has two 32-bit processing cores, namely, CPU1 and CPU2, each of which can provide 200MHz processing performance; in addition, the microcontroller has two programmable Control Law Accelerators (CLA), namely CPU1.CLA1 and CPU2.CLA1, and the CLA is an independent 32-bit floating-point processor and runs at the same speed as the main CPU.
As can be seen in FIG. 3, there are multiple modes of data exchange between CPU1 and CPU2, namely IPC module, global shared memory, MSG memory. Because the CPU1 and the CPU2 read and write the same data area at the same time, a conflict problem occurs, and all three exchange modes include memory read and write permissions, for example, in the MSG memory, the CPU1 → CPU2 MSG memory allows the CPU1 to perform read and write operations, but prohibits the CPU2 from performing write operations; in contrast, the CPU2 → CPU1MSG memory allows the CPU2 to read and write, but prohibits the CPU1 from writing. Considering that the arbitration mechanism in the IPC module is complex, the data exchange speed is affected. The global shared memory requires the CPU1 to perform register configuration in advance, and the CPU2 has no configuration authority. Compared with the prior art, the MSG memory between the CPU1 and the CPU2 has the advantages of simple structure and no need of pre-configuration, and can realize higher data exchange speed by reasonably designing a data exchange strategy. Similar to the above situation, the MSG memory is mainly used for data exchange between the CPU and the CLA, and it should be noted that data exchange between the two CLA cores cannot be performed directly.
In conclusion, the traditional finite set model predictive control algorithm has the defects of contradiction between longer program execution time and shorter control period, lower algorithm execution efficiency than the traditional linear control algorithm, high data and time sequence dependence of the algorithm and contradictory characteristics with independent operation of multiple cores in a microcontroller, so that the further improvement of the switching frequency and the control precision is influenced.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a finite set model predictive control method of a permanent magnet synchronous motor based on multi-core parallel computation, and the control method can effectively reduce the execution time of the algorithm on the basis of keeping the control performance and the control characteristics of the original algorithm.
As conceived above, the technical scheme of the invention is as follows: a permanent magnet synchronous motor finite set model prediction control method based on multi-core parallel computation is characterized by comprising the following steps: the system comprises two processing cores CPU1 and CPU2, an AD conversion module, current-voltage conversion and Clarke conversion in a single-core sequential control strategy are distributed to the CPU1, an eQEP module, rotation speed position calculation, Park inverse conversion and back electromotive force calculation are distributed to the CPU2, and meanwhile, a voltage vector V in the single-core sequential control strategy is distributed to the CPU20～V7The prediction process, the cost function and the comparison optimization process are respectively distributed to the CPU1 and the CPU2, namely a dual-core parallel control module of the CPU1 and the CPU2 FCS-MPC is formed, data exchange is carried out between the two control modules, and the CPU1 carries out AD conversion → current-voltage conversion → u-Clarke conversion processdc、iα、iβThe data is transmitted to the CPU2 to complete the first data exchange, and simultaneously, the CPU2 obtains the eQEP module → the rotating speed position calculation → the Park inverse transformation → the back electromotive force calculation process
eα、eβThe voltage vectors are transmitted to the CPU1 to complete the second data exchange, the CPU2 sends the obtained local optimal voltage vectors to the CPU1, and the CPU1 compares the local optimal voltage vectors respectively obtained by the two cores to obtain the final output voltage vector.
Further, after the first data exchange between the CPU1 and the CPU2 is completed, the programmable control law accelerator CPU1.cLA1 and CPU2.cla1 respectively obtain variable value V required by prediction process from CPU1 and CPU2 corresponding to each other0～V1，V6～V7And aiming at the responsible voltage vector, corresponding calculation of prediction process, cost function and comparative optimization is gradually realized, and when the CLA core obtains a local optimal voltage vector, the optimal value is transmitted to the corresponding CPU before the CPU1 and the CPU2 carry out second data exchange.
Further, the data exchange method between the CPU1 and the CPU2 is: setting flag bits to ensure that the CPU1 and the CPU2 exchange data according to a certain time sequence, wherein:
F1: the first stage CPU1 → the flag bit of CPU2 for data transmission completion;
F2: the first stage CPU2 → the flag bit of CPU1 for data transmission completion;
F3: second stage CPU2 → flag bit of CPU1 data transfer completion;
p represents data output completion;
in the first phase, the CPU1 sends the variable u to the CPU1 → CPU2 MSG memorydc、iα、iβAfter that, F is put1The flag bit is assigned as P; at the same time, CPU2 is constantly on F1The flag bit is checked when F is detected1When the value is P, the CPU1 is judged to have finished sending data, and the corresponding variable u in the MSG memory is read according to the datadc、iα、iβ(ii) a After the CPU2 reads the variables, the variables are read
eα、eβSending to CPU2 → CPU1MSG memory, and sending F2The flag bit is assigned as P; on the other hand, after the CPU1 completes data transmission, it will continue to be connected to F2The flag bit is checked when F is detected2When the value is P, the CPU2 is judged to have finished sending data, and corresponding variable of MSG memory is read according to the data
eα、eβ；
In the second stage, after the CPU2 obtains the local optimum voltage vector, the vector sequence number and the corresponding calculation result of the cost function are sent to the memory of CPU2 → CPU1MSG, and F is sent3The flag bit is assigned as P; on the other hand, after the CPU1 calculates the local optimum voltage vector, the pair F is continuously selected3The flag bit is checked when F is detected3When P, the optimum value will be read, and final comparison and output will be made.
The flag bit F1～F3Using dynamic flag bits, i.e.
In the formula, "-P" represents the inversion operation of the variable P.
Furthermore, the data exchange method between the CPU and the CLA adopts a method of combining a preset flag bit and an interrupt flag bit to ensure the correctness of the time sequence, and when the data exchange process in the first stage is completed, the CPU1 predicts a variable u required by the processdc、iα、iβ、
eα、eβSending the data to the CPU1 → CLA 1MSG memory, and setting the flag bit F in advance4The value is 1 and at the same time CLA1 constantly checks flag bit F4When F is detected4When the value is 1, it means that the data transmission is completed, CLA1 will read the variables one by one, after which CPU1 and CLA1 perform the prediction, evaluation and optimization processes of the respective assigned voltage vectors, and obtain the local optimum value; before the control algorithm enters the second stage of data exchange, CLA1 will send local optimum to CLA1 → CPU1MSG memory, while CPU1 will continuously check flag H to determine if CLA1 completes data transmission, when flag H is 0, CPU1 will read local optimum in MSG memory and flag F4Resetting to 0, and performing a comparison process of local optimum value, wherein the flag bit H is an interrupt flag bit Cla1Regs. MIRUN. bit. INT1, and the flag bit H is set to 0 when the execution of the CLA1 program is completedThe bit will transition from a1 to a 0 and thus may be used as a flag indicating completion of data transmission by CLA 1.
The invention designs a dual-core and quad-core control strategy architecture, and provides a data exchange strategy and a dynamic zone bit, so that the algorithm execution time can be effectively reduced on the basis of keeping the control performance and the control characteristics of the original algorithm.
According to the invention, on the basis of ensuring the data integrity, the data exchange between the CPU1 and the CPU2 and between the CPU and the CLA is adopted, the time sequence of multi-core parallel computation is kept correct, so that the situation that some cores perform data exchange prematurely before other cores do not complete corresponding computation, and then variables of the previous control period are used in the computation of the control period, and finally prediction errors and control deviation are caused is avoided.
The data exchange method between the CPU1 and the CPU2 adopts the flag bit to ensure that the CPU1 and the CPU2 synchronously predict, evaluate and optimize the future state of the motor by using the latest collected motor state quantity in each control cycle. On the contrary, if there is no flag bit to perform timing control on the switching process, in the first stage, the CPU1 or the CPU2 may predict in advance without receiving the other side data; in the second stage, the CPU1 may make a final comparison and output in advance in the case where the CPU2 does not obtain a locally optimal voltage vector. Both of these conditions cause FCS-MPC control errors that affect overall motor control system stability. And the flag bit adopts a dynamic flag bit, in the dynamic flag bit resetting method, each core only needs to perform negation operation on the variable P, the algorithm is simple, and basically no delay exists. F1～F3The meaning of the corresponding values of (a) is alternated with the control period. At the end of the control period of t 2kT, F1～F3P means that both phases of the data exchange have been completed, and at the start of the next control cycle, i.e. t 2kT +1, F1～F3P indicates that neither data exchange is complete. The corresponding flag bit resetting process is simplified through the dynamic alternate conversion of the flag bit assignment significance.
Drawings
FIG. 1 is a block diagram of a FCS-MPC control method;
FIG. 2 is a flow chart of FCS-MPC control;
FIG. 3 is a TMS320F28379D microcontroller multi-core architecture diagram;
FIG. 4 is a flow chart of a FCS-MPC single core sequence control method;
FIG. 5 is a schematic diagram of FCS-MPC dual core parallel control strategy;
FIG. 6 is a diagram of a FCS-MPC quad-core parallel control strategy;
FIG. 7 is a data exchange strategy diagram for CPU1 and CPU 2;
FIG. 8 is a comparison of a conventional flag bit reset method and a dynamic flag bit reset method, wherein (a) is a diagram of the conventional flag bit reset method and (b) is a diagram of the dynamic flag bit reset method;
fig. 9 is a data exchange strategy diagram of the CPU1 and CLA 1.
Detailed Description
The following description of the embodiments of the present invention is provided in conjunction with the accompanying drawings:
the invention provides a permanent magnet synchronous motor finite set model prediction control method based on multi-core parallel computing, which is characterized in that the flows without dependency relationship in a single-core sequence control strategy are respectively distributed to a CPU1 and a CPU 2; at the same time, will be for V0～V7The prediction process, the cost function and the comparative optimization process are equally divided and respectively distributed to the CPU1V0～V1Is distributed to CPU2V6～V7Therefore, an FCS-MPC dual-core parallel control strategy can be obtained, and a flow chart thereof is shown in fig. 5.
As can be seen from fig. 5, unlike the single-core sequential control strategy, the dual-core parallel control strategy requires data exchange to ensure the normal performance of the prediction, evaluation, and optimization processes in each processing core. Wherein the first data exchange occurs before the prediction process is performed, in which process the CPU1 performs AD conversion → current-voltage conversion → Clarke conversion process to obtain udc、iα、iβTo the CPU2. Meanwhile, the CPU2 needs to obtain the result of the eQEP module → the rotation speed position calculation → Park inverse transformation → the back electromotive force calculation process
eα、eβTo the CPU1. The second data exchange occurs after the prediction, evaluation and optimization processes of each processing core are completed, in the process, the CPU2 sends the obtained local optimal voltage vector to the CPU1, so that the CPU1 compares the local optimal voltage vectors respectively obtained by the two cores to obtain the final output voltage vector.
In the FCS-MPC dual-core parallel control strategy, the data exchange strategy between the CPU1 and the CPU2 is performed in two stages, respectively before and after the FCS-MPC algorithm, as shown in FIG. 7.
The CPU1 and the CPU2 can not directly transmit data, but indirectly transmit data through the MSG memory; meanwhile, the difference in read-write permission exists between the two MSGs, and in the design of the data exchange strategy: 1. a specific MSG memory is required to be selected in the data receiving and transmitting process; 2. the flag bit is set to ensure that the CPU1 and the CPU2 exchange data according to a certain time sequence. Among them are:
F1: first stage CPU1 → CPU2 flag bit for completion of data transfer.
F2: first stage CPU2 → CPU1 flag bit for completion of data transfer.
F3: second stage CPU2 → CPU1 flag bit for completion of data transfer.
In the first phase, the CPU1 sends the variable u to the CPU1 → CPU2 MSG memorydc、iα、iβAfter that, F is put1The flag bit is assigned as P; at the same time, CPU2 is constantly on F1The flag bit is checked when F is detected1When the value is P, the CPU1 is judged to have finished sending data, and the corresponding variable u in the MSG memory is read according to the datadc、iα、iβ. When the CPU2 reads the variable, the variable i is read* α、
eα、eβSending to CPU2 → CPU1MSG memory, and sending F2The flag bit is assigned as P; on the other hand, in CPAfter the U1 finishes data transmission, the data will be continuously transmitted to F2The flag bit is checked when F is detected2When the value is P, the CPU2 is judged to have finished sending data, and corresponding variable of MSG memory is read according to the data
eα、eβ。
In the second stage, after the CPU2 obtains the local optimum voltage vector, the vector sequence number and the corresponding calculation result of the cost function are sent to the memory of CPU2 → CPU1MSG, and F is sent3The flag bit is assigned as P; on the other hand, after the CPU1 calculates the local optimum voltage vector, the pair F is continuously selected3The flag bit is checked when F is detected3When P, the optimum value will be read, and final comparison and output will be made.
The process can be seen that the flag bit can ensure that the CPU1 and the CPU2 synchronously predict, evaluate and optimize the future state of the motor by using the latest collected motor state quantity in each control cycle. On the contrary, if there is no flag bit to perform timing control on the switching process, in the first stage, the CPU1 or the CPU2 may predict in advance without receiving the other side data; in the second stage, the CPU1 may make a final comparison and output in advance in the case where the CPU2 does not obtain a locally optimal voltage vector. Both of these conditions cause FCS-MPC control errors that affect overall motor control system stability.
As can be seen, the flag bit F is set after the two stages are completed1～F3Are all assigned to P, and since the meaning of P in this control cycle is that the data transmission is completed, the flag bit F must be set before the next control cycle begins1～F3And resetting. However, in the dual core system, the CPU1 and the CPU2 only have write authority to the respective MSG memories, so resetting all flag bits requires multiple data transfers and judgments between the CPU1 and the CPU2, which increases the complexity of the algorithm to some extent. To solve this problem, a dynamic flag bit is designed, namely
In the formula, "-P" represents the inversion operation of the variable P.
It can be seen that F1～F3The meaning of the corresponding values of (a) is alternated with the control period. At the end of the control period of t 2kT, F1～F3P means that both phases of the data exchange have been completed, and at the start of the next control cycle, i.e. t 2kT +1, F1～F3P indicates that neither data exchange is complete. The corresponding flag bit resetting process is simplified through the dynamic alternate conversion of the flag bit assignment significance.
Fig. 8 shows the difference between the dynamic flag bit reset method and the conventional flag bit reset method.
As can be seen, in the conventional flag bit resetting method, the flag bit F1Must precede F2、F3Reset, otherwise, CPU2 makes a pair of F's, which may cause CPU1 to not complete the second phase data exchange3Reset in advance, causing control timing errors. Therefore, the flag bit resetting process has a large number of MSG memory reading and writing and flag bit detection processes, which all cause a certain delay and affect the algorithm execution efficiency. Compared with the dynamic zone bit resetting method, each core only needs to perform negation operation on the variable P, and the algorithm is simple and basically has no delay.
On the basis of an FCS-MPC dual-core parallel control strategy, the method distributes the prediction, evaluation and optimization processes of partial voltage vectors into CLA cores, thereby realizing a four-core parallel control strategy of 'dual CPU + dual CLA'.
As can be seen from the flowchart shown in fig. 6, after the CPU1 and the CPU2 complete data exchange, the CPU1.cla1 and the CPU2.cla1 respectively obtain variable values required for the prediction process from their corresponding CPU cores, and gradually implement corresponding calculations of the prediction process, the cost function, and the comparison optimization with respect to the responsible voltage vector, thereby further optimizing the execution efficiency of the FCS-MPC. When the CLA core obtains the locally optimal voltage vector, the optimal value needs to be transmitted to the respective corresponding CPU before the CPU1 performs the second data exchange with the CPU2. It can be seen that the four-core parallel control strategy increases the data exchange between the CPU and the CLA compared to the two-core parallel control strategy.
The data exchange strategy between the CPU and the CLA is similar to that between the CPU, and the data exchange between the CPU and the CLA is also divided into two stages. The difference is that the data transmission directions of the two stages are unidirectional, and in addition, the data exchange strategy adopts a method of combining a preset mark bit and an interruption mark bit to ensure the correctness of the time sequence. Taking the data exchange between the CPU1 and CLA1 as an example, the corresponding exchange strategy is shown in fig. 9.
Upon completion of the first stage data exchange process, the CPU1 will predict the variables u required by the processdc、iα、iβ、
eα、eβSending the data to the CPU1 → CLA 1MSG memory, and setting the flag bit F in advance4The value is assigned to 1. At the same time, CLA1 constantly checks flag F4When F is detected4When 1, meaning that the data transfer is complete, CLA1 will read the variables one by one. After that, the CPU1 and CLA1 perform the prediction, evaluation, and optimization processes of the respective assigned voltage vectors, and obtain local optimum values. Before the control algorithm enters the second stage of data exchange, CLA1 will send local optimum to CLA1 → CPU1MSG memory, while CPU1 will continuously check flag H to determine if CLA1 completes data transmission, when flag H is 0, CPU1 will read local optimum in MSG memory and flag F4Reset to 0 and perform a comparison process of the local optimum. The flag H is an interrupt flag cla1regs.mirun.bit.int1, which will be changed from 1 to 0 after the execution of the CLA1 program is completed, and thus can be used as a flag of CLA1 data transmission completion.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (4)
1. A permanent magnet synchronous motor finite set model prediction control method based on multi-core parallel computation is characterized by comprising the following steps: the system comprises two processing cores CPU1 and CPU2, an AD conversion module, current-voltage conversion and Clarke conversion in a single-core sequential control strategy are distributed to the CPU1, an eQEP module, rotation speed position calculation, Park inverse conversion and back electromotive force calculation are distributed to the CPU2, and meanwhile, a voltage vector V in the single-core sequential control strategy is distributed to the CPU20～V7The prediction process, the cost function and the comparison optimization process are respectively distributed to the CPU1 and the CPU2, namely a dual-core parallel control module of the CPU1 and the CPU2 FCS-MPC is formed, data exchange is carried out between the two control modules, and the CPU1 carries out AD conversion → current-voltage conversion → u-Clarke conversion processdc、iα、iβThe data is transmitted to the CPU2 to complete the first data exchange, and simultaneously, the CPU2 obtains the eQEP module → the rotating speed position calculation → the Park inverse transformation → the back electromotive force calculation process
eα、eβThe voltage vectors are transmitted to the CPU1 to complete the second data exchange, the CPU2 sends the obtained local optimal voltage vectors to the CPU1, and the CPU1 compares the local optimal voltage vectors respectively obtained by the two cores to obtain the final output voltage vector.
2. The permanent magnet synchronous motor finite set model predictive control method based on multi-core parallel computing according to claim 1, characterized in that: after the first data exchange between the CPU1 and the CPU2 is completed, the programmable control law accelerators CPU1.cla1 and CPU2.cla1 respectively obtain the variable value V required by the prediction process from the corresponding CPU1 and CPU20～V1，V6～V7And aiming at the responsible voltage vector, gradually realizing the corresponding calculation of prediction process, cost function and comparative optimization, and when the CLA core obtains the local optimal voltage vector, carrying out the second calculation on the CPU1 and the CPU2And before the secondary data exchange, transmitting the optimal values to the corresponding CPUs respectively.
3. The permanent magnet synchronous motor finite set model predictive control method based on multi-core parallel computing according to claim 1, characterized in that: the data exchange method between the CPU1 and the CPU2 is as follows: setting flag bits to ensure that the CPU1 and the CPU2 exchange data according to a certain time sequence, wherein:
F1: the first stage CPU1 → the flag bit of CPU2 for data transmission completion;
F2: the first stage CPU2 → the flag bit of CPU1 for data transmission completion;
F3: second stage CPU2 → flag bit of CPU1 data transfer completion;
p represents data output completion;
in the first phase, the CPU1 sends the variable u to the CPU1 → CPU2 MSG memorydc、iα、iβAfter that, F is put1The flag bit is assigned as P; at the same time, CPU2 is constantly on F1The flag bit is checked when F is detected1When the value is P, the CPU1 is judged to have finished sending data, and the corresponding variable u in the MSG memory is read according to the datadc、iα、iβ(ii) a After the CPU2 reads the variables, the variables are read
eα、eβSending to CPU2 → CPU1MSG memory, and sending F2The flag bit is assigned as P; on the other hand, after the CPU1 completes data transmission, it will continue to be connected to F2The flag bit is checked when F is detected2When the value is P, the CPU2 is judged to have finished sending data, and corresponding variable of MSG memory is read according to the data
eα、eβ；
In the second stage, after the CPU2 obtains the local optimum voltage vector, the vector sequence number and the corresponding cost function calculation result are sent toCPU2 → CPU1MSG memory, and stores F3The flag bit is assigned as P; on the other hand, after the CPU1 calculates the local optimum voltage vector, the pair F is continuously selected3The flag bit is checked when F is detected3When P, the optimum value will be read, and final comparison and output will be made.
The flag bit F1～F3Using dynamic flag bits, i.e.
In the formula, "-P" represents the inversion operation of the variable P.
4. The permanent magnet synchronous motor finite set model predictive control method based on multi-core parallel computing according to claim 2, characterized in that: the data exchange method between the CPU and the CLA adopts a method of combining a preset flag bit and an interrupt flag bit to ensure the correctness of time sequence, and when the data exchange process in the first stage is finished, the CPU1 predicts a variable u required by the processdc、iα、iβ、
eα、eβSending the data to the CPU1 → CLA 1MSG memory, and setting the flag bit F in advance4The value is 1 and at the same time CLA1 constantly checks flag bit F4When F is detected4When the value is 1, it means that the data transmission is completed, CLA1 will read the variables one by one, after which CPU1 and CLA1 perform the prediction, evaluation and optimization processes of the respective assigned voltage vectors, and obtain the local optimum value; before the control algorithm enters the second stage of data exchange, CLA1 will send local optimum to CLA1 → CPU1MSG memory, while CPU1 will continuously check flag H to determine if CLA1 completes data transmission, when flag H is 0, CPU1 will read local optimum in MSG memory and flag F4Resetting to 0 and performing a comparison process of local optimal values, wherein the flag bit H is an interrupt flag bit Cla1RegsN. bit. int1, when execution of the CLA1 program is complete, the flag bit will be changed from 1 to 0, so it can be used as a CLA1 data transmission complete flag.
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